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From: Sven Van Asbroeck <thesven73@gmail.com>
To: shawnguo@kernel.org, fugang.duan@nxp.com, robh+dt@kernel.org
Cc: "David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>,
	netdev@vger.kernel.org, devicetree@vger.kernel.org,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v5 2/3] dt-bindings: fec: add fsl,ptpclk-bypass-pad boolean property
Date: Thu,  2 Jul 2020 13:53:51 -0400	[thread overview]
Message-ID: <20200702175352.19223-2-TheSven73@gmail.com> (raw)
In-Reply-To: <20200702175352.19223-1-TheSven73@gmail.com>

If present, sources the fec's PTP clock straight from
the enet PLL, instead of having to be routed via a SoC pad.

This is only possible on certain SoCs, notably the imx6 (quad) plus.

Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com>
---

Tree: v5.8-rc3

Patch history: see [PATCH v5 3/3]

To: Shawn Guo <shawnguo@kernel.org>
To: Andy Duan <fugang.duan@nxp.com>
To: Rob Herring <robh+dt@kernel.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: netdev@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

 Documentation/devicetree/bindings/net/fsl-fec.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index 9b543789cd52..e34df25a38f6 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -39,6 +39,9 @@ Optional properties:
   tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts.
   For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse
   per second interrupt associated with 1588 precision time protocol(PTP).
+- fsl,ptpclk-bypass-pad: If present, sources the fec's PTP clock straight from
+  the enet PLL, instead of having to be routed via a SoC pad. This is only
+  possible on certain SoCs, notably the imx6 (quad) plus.
 
 Optional subnodes:
 - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
-- 
2.17.1


  reply	other threads:[~2020-07-02 17:54 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-02 17:53 [PATCH v5 1/3] ARM: imx: mach-imx6q: Search for fsl,imx6q-iomuxc-gpr earlier Sven Van Asbroeck
2020-07-02 17:53 ` Sven Van Asbroeck [this message]
2020-07-02 17:53 ` [PATCH v5 3/3] ARM: imx6plus: optionally enable internal routing of clk_enet_ref Sven Van Asbroeck
2020-07-02 22:29   ` Fabio Estevam
2020-07-03  0:50     ` Sven Van Asbroeck
2020-07-03  2:01       ` [EXT] " Andy Duan
2020-07-04 14:08     ` Sven Van Asbroeck
2020-07-05 14:45       ` [EXT] " Andy Duan
2020-07-05 15:34         ` Sven Van Asbroeck
2020-07-06  5:30           ` Andy Duan
2020-07-06 13:46             ` Fabio Estevam
2020-07-06 14:58               ` Sven Van Asbroeck
2020-07-06 14:59                 ` Sven Van Asbroeck
2020-07-07  3:38                   ` Andy Duan
2020-07-07 15:21                     ` Sven Van Asbroeck
2020-07-08  5:16                       ` Andy Duan
2020-07-06 14:53             ` Sven Van Asbroeck

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