From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CE13C433E0 for ; Thu, 2 Jul 2020 17:54:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1D5CC21531 for ; Thu, 2 Jul 2020 17:54:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="elhYe95R" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728006AbgGBRyH (ORCPT ); Thu, 2 Jul 2020 13:54:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727963AbgGBRyA (ORCPT ); Thu, 2 Jul 2020 13:54:00 -0400 Received: from mail-qt1-x842.google.com (mail-qt1-x842.google.com [IPv6:2607:f8b0:4864:20::842]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17291C08C5C1; Thu, 2 Jul 2020 10:54:00 -0700 (PDT) Received: by mail-qt1-x842.google.com with SMTP id x62so21933527qtd.3; Thu, 02 Jul 2020 10:54:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZKWKuZ/GqJQ2tlXnv5kEi5eyCWfh4Zy6tKRJWrUWoaM=; b=elhYe95RAW43tw1m88MdkH7kBUzi2ZgOftqKEM9l9fBrUR+wpcM6JpeDVnUgXkmEvg MjdNaswFysDTZb5Ogb9Gzi8XJil6h3Qr/G4xFrbeE5rTwc80GepH2raQTAZw5oOdZHHv G+3lA2iAL0MrgKy8XV0CPVbtv8YFw98N7Sm21Aq10wvpAnPWvNuT6hh2VBft0Cw/cl/k lk08LrNF3tDD62jegfVBQXJMWg6FW9Ew1/Zwm7aropH+ZbZtewjo3N/nAZ9MttWG58P9 arwAPDh6T+OAQIDjjnaouHW6EfGZ9YSq6TMkYUJBO3+ftnghUXqwTZ0/YOKQv1mhwGIT 5KnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZKWKuZ/GqJQ2tlXnv5kEi5eyCWfh4Zy6tKRJWrUWoaM=; b=eeISvj9vxfEyYydyv5cX1K7M2HKEIqzOg8mJ5D8on6WE9QxMtRZ92MgAC/cc1I5Tt/ 6mGvSm/0DDAH1PsFCKbhs4p9iXVvO+xu5iPQDvcLxTyJGBNxNpWtjv2FC1RWYxmQhsBv h5cPaamuJu5tFL523TbhxpiecndXb2OQAhN0a5U8FoBzO7IYlKkGwjhl3drn24UhzKbZ rvv3kB+XBNW75qkePhvLrCQzZixjYXs+LtwrJvaK9HZ72lwrqseJgupB96airZ6sYWhU LBIXwSVxIYwW5STZST3P2PSURT2/g5WtDjMblGAijfdPsqXEyIf4BbgSDuVXQ78mNTUq sabA== X-Gm-Message-State: AOAM533NU+Kce8HMcJ0UUX2HwCUjDlU28IhMNDJQe6JBncqS4iZPeZLn 4W6QGsfFgwubeL104/WTCFE= X-Google-Smtp-Source: ABdhPJxFIU3UKxBx6qN2dHiZNWiq9jLcasvtl0GEwPexqj0BW1YbvA10GOwT5IelBz2Hv/a92nrH0Q== X-Received: by 2002:ac8:429b:: with SMTP id o27mr21249400qtl.124.1593712438939; Thu, 02 Jul 2020 10:53:58 -0700 (PDT) Received: from localhost.localdomain ([72.53.229.195]) by smtp.gmail.com with ESMTPSA id w204sm9149937qka.41.2020.07.02.10.53.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2020 10:53:58 -0700 (PDT) From: Sven Van Asbroeck X-Google-Original-From: Sven Van Asbroeck To: shawnguo@kernel.org, fugang.duan@nxp.com, robh+dt@kernel.org Cc: "David S. Miller" , Jakub Kicinski , netdev@vger.kernel.org, devicetree@vger.kernel.org, Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/3] ARM: imx6plus: optionally enable internal routing of clk_enet_ref Date: Thu, 2 Jul 2020 13:53:52 -0400 Message-Id: <20200702175352.19223-3-TheSven73@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200702175352.19223-1-TheSven73@gmail.com> References: <20200702175352.19223-1-TheSven73@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On imx6, the ethernet reference clock (clk_enet_ref) can be generated by either the imx6, or an external source (e.g. an oscillator or the PHY). When generated by the imx6, the clock source (from ANATOP) must be routed to the input of clk_enet_ref via two pads on the SoC, typically via a dedicated track on the PCB. On an imx6 plus however, there is a new setting which enables this clock to be routed internally on the SoC, from its ANATOP clock source, straight to clk_enet_ref, without having to go through the SoC pads. Enable internal routing if the fsl,ptpclk-bypass-pad boolean property is present in the "fsl,imx6q-fec" devicetree node. Link: https://lore.kernel.org/lkml/CAOMZO5BYC3DmE_G0XRwRH9vSJiVVvKbtznODyntsAuorF=HoqA@mail.gmail.com/ Signed-off-by: Sven Van Asbroeck --- Tree: v5.8-rc3 v4 -> v5: - identified that existing imx6q-plus boards could break ethernet if v4 patch is applied. reached consensus: prevent breakage by requiring an explicit devicetree property for internal ptp clk routing. Link: https://lore.kernel.org/lkml/CAOMZO5BYC3DmE_G0XRwRH9vSJiVVvKbtznODyntsAuorF=HoqA@mail.gmail.com/ v3 -> v4: - avoid double-check for IS_ERR(gpr) by including Fabio Estevam's patch. v2 -> v3: - remove check for imx6q, which is already implied when of_machine_is_compatible("fsl,imx6qp") v1 -> v2: - Fabio Estevam: use of_machine_is_compatible() to determine if we are running on an imx6 plus. To: Shawn Guo To: Andy Duan To: Rob Herring Cc: "David S. Miller" Cc: Jakub Kicinski Cc: netdev@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org arch/arm/mach-imx/mach-imx6q.c | 14 ++++++++++++++ include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index ae89ad93ca83..ac62994eb7ba 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -204,6 +204,20 @@ static void __init imx6q_1588_init(void) regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_ENET_CLK_SEL_MASK, clksel); + /* + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to + * be the PTP clock source, instead of having to be routed through + * pads. + */ + if (of_machine_is_compatible("fsl,imx6qp")) { + clksel = of_property_read_bool(np, "fsl,ptpclk-bypass-pad") ? + IMX6Q_GPR5_ENET_TXCLK_SEL_PLL : + IMX6Q_GPR5_ENET_TXCLK_SEL_PAD; + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6Q_GPR5_ENET_TXCLK_SEL_MASK, clksel); + } + + clk_put(enet_ref); put_ptp_clk: clk_put(ptp_clk); diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d4b5e527a7a3..58377002427f 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -240,6 +240,9 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TXCLK_SEL_MASK BIT(9) +#define IMX6Q_GPR5_ENET_TXCLK_SEL_PAD 0 +#define IMX6Q_GPR5_ENET_TXCLK_SEL_PLL BIT(9) #define IMX6Q_GPR5_SATA_SW_PD BIT(10) #define IMX6Q_GPR5_SATA_SW_RST BIT(11) -- 2.17.1