From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDEE0C433E6 for ; Fri, 17 Jul 2020 01:53:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C42902076D for ; Fri, 17 Jul 2020 01:53:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726809AbgGQBxM (ORCPT ); Thu, 16 Jul 2020 21:53:12 -0400 Received: from lucky1.263xmail.com ([211.157.147.135]:39852 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726130AbgGQBxM (ORCPT ); Thu, 16 Jul 2020 21:53:12 -0400 Received: from localhost (unknown [192.168.167.209]) by lucky1.263xmail.com (Postfix) with ESMTP id CB4D7A157F; Fri, 17 Jul 2020 09:53:08 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P17009T140099932980992S1594950787566122_; Fri, 17 Jul 2020 09:53:08 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <918b3b7cdf0ed7d2ab8dc91c94b75d1a> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Cc: linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, david.wu@rock-chips.com, Jianqun Xu Subject: [PATCH 07/13] pinctrl: rockchip: do codingstyle Date: Fri, 17 Jul 2020 09:53:05 +0800 Message-Id: <20200717015305.14202-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add RK3368 definitions to separate from other SoCs. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 34 ++++++++++++++++++------------ 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 71335ed003b3..8e3fa9011165 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1987,6 +1987,9 @@ static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, #define RK3368_PULL_GRF_OFFSET 0x100 #define RK3368_PULL_PMU_OFFSET 0x10 +#define RK3368_PULL_BITS_PER_PIN 2 +#define RK3368_PULL_PINS_PER_REG 8 +#define RK3368_PULL_BANK_STRIDE 16 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -1999,25 +2002,28 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *regmap = info->regmap_pmu; *reg = RK3368_PULL_PMU_OFFSET; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); - *bit = pin_num % RK3188_PULL_PINS_PER_REG; - *bit *= RK3188_PULL_BITS_PER_PIN; + *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3368_PULL_PINS_PER_REG; + *bit *= RK3368_PULL_BITS_PER_PIN; } else { *regmap = info->regmap_base; *reg = RK3368_PULL_GRF_OFFSET; /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; - *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3368_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4); - *bit = (pin_num % RK3188_PULL_PINS_PER_REG); - *bit *= RK3188_PULL_BITS_PER_PIN; + *bit = (pin_num % RK3368_PULL_PINS_PER_REG); + *bit *= RK3368_PULL_BITS_PER_PIN; } } #define RK3368_DRV_PMU_OFFSET 0x20 #define RK3368_DRV_GRF_OFFSET 0x200 +#define RK3368_DRV_BITS_PER_PIN 2 +#define RK3368_DRV_PINS_PER_REG 8 +#define RK3368_DRV_BANK_STRIDE 16 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -2030,20 +2036,20 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *regmap = info->regmap_pmu; *reg = RK3368_DRV_PMU_OFFSET; - *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); - *bit = pin_num % RK3288_DRV_PINS_PER_REG; - *bit *= RK3288_DRV_BITS_PER_PIN; + *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3368_DRV_PINS_PER_REG; + *bit *= RK3368_DRV_BITS_PER_PIN; } else { *regmap = info->regmap_base; *reg = RK3368_DRV_GRF_OFFSET; /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; - *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; - *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3368_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4); - *bit = (pin_num % RK3288_DRV_PINS_PER_REG); - *bit *= RK3288_DRV_BITS_PER_PIN; + *bit = (pin_num % RK3368_DRV_PINS_PER_REG); + *bit *= RK3368_DRV_BITS_PER_PIN; } } -- 2.17.1