From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Claudiu Beznea <claudiu.beznea@microchip.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org,
nicolas.ferre@microchip.com, ludovic.desroches@microchip.com,
bbrezillon@kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 07/19] clk: at91: sam9x60-pll: use frac when setting frequency
Date: Fri, 17 Jul 2020 11:12:38 +0200 [thread overview]
Message-ID: <20200717091238.GL3428@piout.net> (raw)
In-Reply-To: <1594812267-6697-8-git-send-email-claudiu.beznea@microchip.com>
On 15/07/2020 14:24:15+0300, Claudiu Beznea wrote:
> In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
> the fractional part of PLL wasn't set on registers but it was
> calculated and taken into account for determining div and mul
> (see sam9x60_pll_get_best_div_mul()).
>
I think this becomes an issue only once 4/19 is applied so you should
probably squash those two together.
> Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> drivers/clk/at91/clk-sam9x60-pll.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index 00f2afd6e9b6..13e15bd48770 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -16,6 +16,7 @@
>
> #define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
> #define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)
> +#define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
>
> #define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
> #define UPLL_DIV 2
> @@ -55,7 +56,7 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
> unsigned long flags;
> u8 div;
> u16 mul;
> - u32 val;
> + u32 val, frac;
>
> spin_lock_irqsave(pll->lock, flags);
> regmap_write(regmap, AT91_PMC_PLL_UPDT, pll->id);
> @@ -65,9 +66,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
>
> regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
> mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
> + frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val);
>
> if (sam9x60_pll_ready(regmap, pll->id) &&
> - (div == pll->div && mul == pll->mul)) {
> + (div == pll->div && mul == pll->mul && frac == pll->frac)) {
> spin_unlock_irqrestore(pll->lock, flags);
> return 0;
> }
> @@ -80,7 +82,8 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
> regmap_write(regmap, AT91_PMC_PLL_ACR, val);
>
> regmap_write(regmap, AT91_PMC_PLL_CTRL1,
> - FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul));
> + FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul) |
> + FIELD_PREP(PMC_PLL_CTRL1_FRACR_MSK, pll->frac));
>
> if (pll->characteristics->upll) {
> /* Enable the UTMI internal bandgap */
> --
> 2.7.4
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
next prev parent reply other threads:[~2020-07-17 9:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-15 11:24 [PATCH 00/19] clk: at91: add sama7g5 clock support Claudiu Beznea
2020-07-15 11:24 ` [PATCH 01/19] clk: at91: clk-generated: continue if __clk_determine_rate() returns error Claudiu Beznea
2020-07-17 9:09 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 02/19] clk: at91: clk-generated: check best_rate against ranges Claudiu Beznea
2020-07-17 9:10 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 03/19] clk: at91: clk-sam9x60-pll: fix mul mask Claudiu Beznea
2020-07-17 9:11 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 04/19] clk: at91: sam9x60-pll: use frac when computing pll frequency Claudiu Beznea
2020-07-15 11:24 ` [PATCH 05/19] clk: at91: sam9x60-pll: use logical or for range check Claudiu Beznea
2020-07-17 9:13 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 06/19] clk: at91: sam9x60-pll: check fcore against ranges Claudiu Beznea
2020-07-17 9:23 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 07/19] clk: at91: sam9x60-pll: use frac when setting frequency Claudiu Beznea
2020-07-17 9:12 ` Alexandre Belloni [this message]
2020-07-20 10:34 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 08/19] clk: at91: sam9x60: fix main rc oscillator frequency Claudiu Beznea
2020-07-17 9:17 ` Alexandre Belloni
2020-07-15 11:24 ` [PATCH 09/19] clk: at91: sckc: register slow_rc with accuracy option Claudiu Beznea
2020-07-15 15:39 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 10/19] clk: at91: replace conditional operator with double logical not Claudiu Beznea
2020-07-17 15:07 ` Alexandre Belloni
2020-07-20 10:36 ` Claudiu.Beznea
2020-07-15 11:24 ` [PATCH 11/19] clk: at91: clk-generated: pass the id of changeable parent at registration Claudiu Beznea
2020-07-16 16:57 ` Codrin.Ciubotariu
2020-07-15 11:24 ` [PATCH 12/19] clk: at91: clk-generated: add mux_table option Claudiu Beznea
2020-07-15 11:24 ` [PATCH 13/19] clk: at91: clk-master: add master clock support for SAMA7G5 Claudiu Beznea
2020-07-15 11:24 ` [PATCH 14/19] clk: at91: clk-peripheral: add support for changeable parent rate Claudiu Beznea
2020-07-15 11:24 ` [PATCH 15/19] clk: at91: clk-programmable: add mux_table option Claudiu Beznea
2020-07-15 11:24 ` [PATCH 16/19] clk: at91: add macro for pll ids mask Claudiu Beznea
2020-07-15 11:24 ` [PATCH 17/19] clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs Claudiu Beznea
2020-07-15 11:24 ` [PATCH 18/19] clk: at91: clk-utmi: add utmi support for sama7g5 Claudiu Beznea
2020-07-15 11:24 ` [PATCH 19/19] clk: at91: sama7g5: add clock " Claudiu Beznea
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