From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA03BC433E3 for ; Fri, 24 Jul 2020 17:22:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C326220674 for ; Fri, 24 Jul 2020 17:22:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726942AbgGXRWb (ORCPT ); Fri, 24 Jul 2020 13:22:31 -0400 Received: from mga17.intel.com ([192.55.52.151]:2758 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726553AbgGXRWa (ORCPT ); Fri, 24 Jul 2020 13:22:30 -0400 IronPort-SDR: iom1tFWo+f7GA+6Oat+YV0gk/vKJmrUP/cqh3LrP14fXazXKbBb9E1QW1pGTJVgOQP8jFL0dAn hZH4vHkBWWyA== X-IronPort-AV: E=McAfee;i="6000,8403,9692"; a="130823244" X-IronPort-AV: E=Sophos;i="5.75,391,1589266800"; d="scan'208";a="130823244" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jul 2020 10:22:30 -0700 IronPort-SDR: 9O8vtli5y+nZdsVOSbnTk6bWsPxd5MqQ7GUWcjS0oy557P5BpoSCxHE1+LsmRoAOMgei5GA2hR /Jg3/X1J6vaQ== X-IronPort-AV: E=Sophos;i="5.75,391,1589266800"; d="scan'208";a="302730265" Received: from seokjaeb-mobl1.amr.corp.intel.com (HELO arch-ashland-svkelley.intel.com) ([10.254.24.239]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jul 2020 10:22:29 -0700 From: Sean V Kelley To: bhelgaas@google.com, Jonathan.Cameron@huawei.com, rjw@rjwysocki.net, ashok.raj@kernel.org, tony.luck@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Qiuxu Zhuo Subject: [RFC PATCH 1/9] pci_ids: Add class code and extended capability for RCEC Date: Fri, 24 Jul 2020 10:22:15 -0700 Message-Id: <20200724172223.145608-2-sean.v.kelley@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200724172223.145608-1-sean.v.kelley@intel.com> References: <20200724172223.145608-1-sean.v.kelley@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Qiuxu Zhuo A PCIe Root Complex Event Collector(RCEC) has the base class 0x08, sub-class 0x07, and programming interface 0x00. Add the class code 0x0807 to identify RCEC devices and add the defines for the RCEC Endpoint Association Extended Capability. See PCI Express Base Specification, version 5.0-1, section "1.3.4 Root Complex Event Collector" and section "7.9.10 Root Complex Event Collector Endpoint Association Extended Capability" Signed-off-by: Qiuxu Zhuo --- include/linux/pci_ids.h | 1 + include/uapi/linux/pci_regs.h | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 0ad57693f392..de8dff1fb176 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -81,6 +81,7 @@ #define PCI_CLASS_SYSTEM_RTC 0x0803 #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 #define PCI_CLASS_SYSTEM_SDHCI 0x0805 +#define PCI_CLASS_SYSTEM_RCEC 0x0807 #define PCI_CLASS_SYSTEM_OTHER 0x0880 #define PCI_BASE_CLASS_INPUT 0x09 diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index f9701410d3b5..f335f65f65d6 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -828,6 +828,13 @@ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ #define PCI_EXT_CAP_PWR_SIZEOF 16 +/* Root Complex Event Collector Endpoint Association */ +#define PCI_RCEC_RCIEP_BITMAP 4 /* Associated Bitmap for RCiEPs */ +#define PCI_RCEC_BUSN 8 /* RCEC Associated Bus Numbers */ +#define PCI_RCEC_BUSN_REG_VER 0x02 /* Least capability version that BUSN present */ +#define PCI_RCEC_BUSN_NEXT(x) (((x) >> 8) & 0xff) +#define PCI_RCEC_BUSN_LAST(x) (((x) >> 16) & 0xff) + /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */ #define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) -- 2.27.0