From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Vinod Koul <vkoul@kernel.org>, Viresh Kumar <vireshk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Serge Semin <fancer.lancer@gmail.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
Peter Ujfalusi <peter.ujfalusi@ti.com>,
Rob Herring <robh+dt@kernel.org>,
dmaengine@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/5] dmaengine: dw: Add DMA-channels mask cell support
Date: Thu, 30 Jul 2020 19:41:46 +0300 [thread overview]
Message-ID: <20200730164146.GX3703480@smile.fi.intel.com> (raw)
In-Reply-To: <20200730154545.3965-6-Sergey.Semin@baikalelectronics.ru>
On Thu, Jul 30, 2020 at 06:45:45PM +0300, Serge Semin wrote:
> DW DMA IP-core provides a way to synthesize the DMA controller with
> channels having different parameters like maximum burst-length,
> multi-block support, maximum data width, etc. Those parameters both
> explicitly and implicitly affect the channels performance. Since DMA slave
> devices might be very demanding to the DMA performance, let's provide a
> functionality for the slaves to be assigned with DW DMA channels, which
> performance according to the platform engineer fulfill their requirements.
> After this patch is applied it can be done by passing the mask of suitable
> DMA-channels either directly in the dw_dma_slave structure instance or as
> a fifth cell of the DMA DT-property. If mask is zero or not provided, then
> there is no limitation on the channels allocation.
>
> For instance Baikal-T1 SoC is equipped with a DW DMAC engine, which first
> two channels are synthesized with max burst length of 16, while the rest
> of the channels have been created with max-burst-len=4. It would seem that
> the first two channels must be faster than the others and should be more
> preferable for the time-critical DMA slave devices. In practice it turned
> out that the situation is quite the opposite. The channels with
> max-burst-len=4 demonstrated a better performance than the channels with
> max-burst-len=16 even when they both had been initialized with the same
> settings. The performance drop of the first two DMA-channels made them
> unsuitable for the DW APB SSI slave device. No matter what settings they
> are configured with, full-duplex SPI transfers occasionally experience the
> Rx FIFO overflow. It means that the DMA-engine doesn't keep up with
> incoming data pace even though the SPI-bus is enabled with speed of 25MHz
> while the DW DMA controller is clocked with 50MHz signal. There is no such
> problem has been noticed for the channels synthesized with
> max-burst-len=4.
...
> + if (dws->channels && !(dws->channels & dwc->mask))
You can drop the first check if...
> + return false;
...
> + if (dma_spec->args_count >= 4)
> + slave.channels = dma_spec->args[3];
...you apply sane default here or somewhere else.
...
> + fls(slave.channels) > dw->pdata->nr_channels))
Does it really make sense?
I think it can also be simplified to faster op, i.e.
BIT(nr_channels) < slave.channels
(but check for off-by-one errors)
...
> + * @channels: mask of the channels permitted for allocation (zero
> + * value means any)
Perhaps on one line?
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2020-07-30 16:41 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-30 15:45 [PATCH 0/5] dmaengine: dw: Introduce non-mem peripherals optimizations Serge Semin
2020-07-30 15:45 ` [PATCH 1/5] dt-bindings: dma: dw: Add optional DMA-channels mask cell support Serge Semin
2020-07-31 22:42 ` Rob Herring
2020-07-30 15:45 ` [PATCH 2/5] dmaengine: dw: Activate FIFO-mode for memory peripherals only Serge Semin
2020-07-30 16:24 ` Andy Shevchenko
2020-07-30 16:31 ` Serge Semin
2020-07-30 16:47 ` Andy Shevchenko
2020-07-30 17:13 ` Serge Semin
2020-07-31 16:52 ` Vinod Koul
2020-07-31 16:57 ` Serge Semin
2020-07-30 15:45 ` [PATCH 3/5] dmaengine: dw: Discard dlen from the dev-to-mem xfer width calculation Serge Semin
2020-07-30 16:28 ` Andy Shevchenko
2020-07-30 15:45 ` [PATCH 4/5] dmaengine: dw: Ignore burst setting for memory peripherals Serge Semin
2020-07-30 16:31 ` Andy Shevchenko
2020-07-30 16:37 ` Serge Semin
2020-07-30 15:45 ` [PATCH 5/5] dmaengine: dw: Add DMA-channels mask cell support Serge Semin
2020-07-30 16:41 ` Andy Shevchenko [this message]
2020-07-30 17:11 ` Serge Semin
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