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Mon, 17 Aug 2020 16:55:33 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 549FFC433A1; Mon, 17 Aug 2020 16:55:31 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1BA23C433CB; Mon, 17 Aug 2020 16:55:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1BA23C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Mon, 17 Aug 2020 10:55:25 -0600 From: Jordan Crouse To: Rob Clark Cc: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan , Will Deacon , freedreno@lists.freedesktop.org, Bjorn Andersson , Sibi Sankar , Vivek Gautam , Stephen Boyd , Robin Murphy , Joerg Roedel , linux-arm-kernel@lists.infradead.org, Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jonathan Marek , Shawn Guo , Sharat Masetty , AngeloGioacchino Del Regno , open list Subject: Re: [PATCH 07/19] drm/msm: set adreno_smmu as gpu's drvdata Message-ID: <20200817165524.GJ3221@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Rob Clark , dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan , Will Deacon , freedreno@lists.freedesktop.org, Bjorn Andersson , Sibi Sankar , Vivek Gautam , Stephen Boyd , Robin Murphy , Joerg Roedel , linux-arm-kernel@lists.infradead.org, Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jonathan Marek , Shawn Guo , Sharat Masetty , AngeloGioacchino Del Regno , open list References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-8-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200814024114.1177553-8-robdclark@gmail.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 13, 2020 at 07:41:02PM -0700, Rob Clark wrote: > From: Rob Clark > > This will be populated by adreno-smmu, to provide a way for coordinating > enabling/disabling TTBR0 translation. > Reviewed-by: Jordan Crouse > Signed-off-by: Rob Clark > --- > drivers/gpu/drm/msm/adreno/adreno_device.c | 2 -- > drivers/gpu/drm/msm/msm_gpu.c | 2 +- > drivers/gpu/drm/msm/msm_gpu.h | 6 +++++- > 3 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index 26664e1b30c0..58e03b20e1c7 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -417,8 +417,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) > return PTR_ERR(gpu); > } > > - dev_set_drvdata(dev, gpu); > - > return 0; > } > > diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c > index 6aa9e04e52e7..806eb0957280 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.c > +++ b/drivers/gpu/drm/msm/msm_gpu.c > @@ -892,7 +892,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, > gpu->gpu_cx = NULL; > > gpu->pdev = pdev; > - platform_set_drvdata(pdev, gpu); > + platform_set_drvdata(pdev, &gpu->adreno_smmu); > > msm_devfreq_init(gpu); > > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > index 8bda7beaed4b..f91b141add75 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.h > +++ b/drivers/gpu/drm/msm/msm_gpu.h > @@ -7,6 +7,7 @@ > #ifndef __MSM_GPU_H__ > #define __MSM_GPU_H__ > > +#include > #include > #include > #include > @@ -73,6 +74,8 @@ struct msm_gpu { > struct platform_device *pdev; > const struct msm_gpu_funcs *funcs; > > + struct adreno_smmu_priv adreno_smmu; > + > /* performance counters (hw & sw): */ > spinlock_t perf_lock; > bool perfcntr_active; > @@ -143,7 +146,8 @@ struct msm_gpu { > > static inline struct msm_gpu *dev_to_gpu(struct device *dev) > { > - return dev_get_drvdata(dev); > + struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev); > + return container_of(adreno_smmu, struct msm_gpu, adreno_smmu); > } > > /* It turns out that all targets use the same ringbuffer size */ > -- > 2.26.2 > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project