From: Rob Clark <robdclark@gmail.com>
To: dri-devel@lists.freedesktop.org,
iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org
Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
Will Deacon <will@kernel.org>,
freedreno@lists.freedesktop.org,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Sibi Sankar <sibis@codeaurora.org>,
Vivek Gautam <vivek.gautam@codeaurora.org>,
Stephen Boyd <swboyd@chromium.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
Rob Clark <robdclark@chromium.org>,
Jordan Crouse <jcrouse@codeaurora.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Krishna Reddy <vdumpa@nvidia.com>,
Jon Hunter <jonathanh@nvidia.com>,
linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU
DRIVERS), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH 19/20] iommu/arm-smmu: add a way for implementations to influence SCTLR
Date: Mon, 17 Aug 2020 15:01:44 -0700 [thread overview]
Message-ID: <20200817220238.603465-20-robdclark@gmail.com> (raw)
In-Reply-To: <20200817220238.603465-1-robdclark@gmail.com>
From: Rob Clark <robdclark@chromium.org>
For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
pending translations are not terminated on iova fault. Otherwise
a terminated CP read could hang the GPU by returning invalid
command-stream data.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++
drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++
drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++
3 files changed, 12 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 5640d9960610..2aa6249050ff 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -127,6 +127,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
(smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
+ /*
+ * On the GPU device we want to process subsequent transactions after a
+ * fault to keep the GPU from hanging
+ */
+ smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF;
+
/*
* Initialize private interface with GPU:
*/
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index e63a480d7f71..bbec5793faf8 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
reg |= ARM_SMMU_SCTLR_E;
+ reg |= cfg->sctlr_set;
+ reg &= ~cfg->sctlr_clr;
+
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index cd75a33967bb..2df3a70a8a41 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -144,6 +144,7 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_CB_SCTLR 0x0
#define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12)
#define ARM_SMMU_SCTLR_CFCFG BIT(7)
+#define ARM_SMMU_SCTLR_HUPCF BIT(8)
#define ARM_SMMU_SCTLR_CFIE BIT(6)
#define ARM_SMMU_SCTLR_CFRE BIT(5)
#define ARM_SMMU_SCTLR_E BIT(4)
@@ -341,6 +342,8 @@ struct arm_smmu_cfg {
u16 asid;
u16 vmid;
};
+ u32 sctlr_set; /* extra bits to set in SCTLR */
+ u32 sctlr_clr; /* bits to mask in SCTLR */
enum arm_smmu_cbar_type cbar;
enum arm_smmu_context_fmt fmt;
};
--
2.26.2
next prev parent reply other threads:[~2020-08-17 22:03 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-17 22:01 [PATCH 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables Rob Clark
2020-08-17 22:01 ` [PATCH 01/20] drm/msm: remove dangling submitqueue references Rob Clark
2020-08-17 22:01 ` [PATCH 02/20] iommu/arm-smmu: Pass io-pgtable config to implementation specific function Rob Clark
2020-08-17 22:01 ` [PATCH 03/20] iommu/arm-smmu: Add support for split pagetables Rob Clark
2020-08-17 22:01 ` [PATCH 04/20] iommu/arm-smmu: Prepare for the adreno-smmu implementation Rob Clark
2020-08-17 22:01 ` [PATCH 05/20] iommu: add private interface for adreno-smmu Rob Clark
2020-08-17 22:01 ` [PATCH 06/20] drm/msm/gpu: add dev_to_gpu() helper Rob Clark
2020-08-17 22:01 ` [PATCH 07/20] drm/msm: set adreno_smmu as gpu's drvdata Rob Clark
2020-08-17 22:01 ` [PATCH 08/20] iommu/arm-smmu: constify some helpers Rob Clark
2020-08-17 22:01 ` [PATCH 09/20] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU Rob Clark
2020-08-17 22:01 ` [PATCH 10/20] dt-bindings: arm-smmu: Add compatible string for Adreno " Rob Clark
2020-08-19 17:02 ` Doug Anderson
2020-08-19 17:36 ` Rob Clark
2020-08-19 18:20 ` Doug Anderson
2020-08-21 14:39 ` Jordan Crouse
2020-08-17 22:01 ` [PATCH 11/20] drm/msm: Add a context pointer to the submitqueue Rob Clark
2020-08-17 22:01 ` [PATCH 12/20] drm/msm: Drop context arg to gpu->submit() Rob Clark
2020-08-17 22:01 ` [PATCH 13/20] drm/msm: Set the global virtual address range from the IOMMU domain Rob Clark
2020-08-17 22:01 ` [PATCH 14/20] drm/msm: Add support to create a local pagetable Rob Clark
2020-08-17 22:01 ` [PATCH 15/20] drm/msm: Add support for private address space instances Rob Clark
2020-08-17 22:01 ` [PATCH 16/20] drm/msm/a6xx: Add support for per-instance pagetables Rob Clark
2020-08-18 10:10 ` Akhil P Oommen
2020-08-17 22:01 ` [PATCH 17/20] arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU Rob Clark
2020-08-17 22:01 ` [PATCH 18/20] arm: dts: qcom: sc7180: " Rob Clark
2020-08-17 22:01 ` Rob Clark [this message]
2020-08-17 22:01 ` [PATCH 20/20] drm/msm: show process names in gem_describe Rob Clark
2020-09-04 9:11 ` [PATCH 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables Joerg Roedel
2020-09-04 16:47 ` Rob Clark
2020-08-24 18:37 Rob Clark
2020-08-24 18:37 ` [PATCH 19/20] iommu/arm-smmu: add a way for implementations to influence SCTLR Rob Clark
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