From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E665FC433E1 for ; Thu, 20 Aug 2020 00:11:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B228A2075E for ; Thu, 20 Aug 2020 00:11:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597882289; bh=cBWRrPXAZq+OpXD8QP6SeV0mkgjHFxpB8eaf/FyXlsA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=1XAe7DFw4QkcEdmPbu9o5aPYSnYIdd2uw4oexnIAYypq2bYLmrnCWx6OkDOHQLtEB +Zo9wGa8hcmrCw2iylXnfyL7cfqocoSjLxwDs6BcTVLe9aJu3upjanVprtt66LIJF5 vQimpWUlaMag+wolj4dy7Pfxt2t8PcRlrQUQxsPs= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728230AbgHTAL2 (ORCPT ); Wed, 19 Aug 2020 20:11:28 -0400 Received: from mail.kernel.org ([198.145.29.99]:58576 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727822AbgHTACH (ORCPT ); Wed, 19 Aug 2020 20:02:07 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 257AE214F1; Thu, 20 Aug 2020 00:02:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597881727; bh=cBWRrPXAZq+OpXD8QP6SeV0mkgjHFxpB8eaf/FyXlsA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CizWH0iF+sQxj7FteMdGjiKNEsKJMUELydrXVkQcHj9qQfhJPwb9buZ6NB8iLr3Yn NvpP3i9BLzZk5DErLpZBVFenZ+MjhVo9ty8Gqmdy3925cjXBSWKLOekDwDxIzdSXhh TUwBC4b4G7x42EXWprspkICUcnZtaCf1yeF3sqx4= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Greg Ungerer , Sasha Levin , linux-m68k@lists.linux-m68k.org Subject: [PATCH AUTOSEL 5.7 09/24] m68knommu: fix overwriting of bits in ColdFire V3 cache control Date: Wed, 19 Aug 2020 20:01:40 -0400 Message-Id: <20200820000155.215089-9-sashal@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200820000155.215089-1-sashal@kernel.org> References: <20200820000155.215089-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Greg Ungerer [ Upstream commit bdee0e793cea10c516ff48bf3ebb4ef1820a116b ] The Cache Control Register (CACR) of the ColdFire V3 has bits that control high level caching functions, and also enable/disable the use of the alternate stack pointer register (the EUSP bit) to provide separate supervisor and user stack pointer registers. The code as it is today will blindly clear the EUSP bit on cache actions like invalidation. So it is broken for this case - and that will result in failed booting (interrupt entry and exit processing will be completely hosed). This only affects ColdFire V3 parts that support the alternate stack register (like the 5329 for example) - generally speaking new parts do, older parts don't. It has no impact on ColdFire V3 parts with the single stack pointer, like the 5307 for example. Fix the cache bit defines used, so they maintain the EUSP bit when carrying out cache actions through the CACR register. Signed-off-by: Greg Ungerer Signed-off-by: Sasha Levin --- arch/m68k/include/asm/m53xxacr.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h index 9138a624c5c81..692f90e7fecc1 100644 --- a/arch/m68k/include/asm/m53xxacr.h +++ b/arch/m68k/include/asm/m53xxacr.h @@ -89,9 +89,9 @@ * coherency though in all cases. And for copyback caches we will need * to push cached data as well. */ -#define CACHE_INIT CACR_CINVA -#define CACHE_INVALIDATE CACR_CINVA -#define CACHE_INVALIDATED CACR_CINVA +#define CACHE_INIT (CACHE_MODE + CACR_CINVA - CACR_EC) +#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINVA) +#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINVA) #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ (0x000f0000) + \ -- 2.25.1