* [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy)
@ 2020-08-26 2:47 Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 1/9] dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information Stephen Boyd
` (8 more replies)
0 siblings, 9 replies; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Rob Clark
This patch series is based on v11 of the msm DP driver submission[1]
plus a compliance patch[2]. In the v5 patch series review I suggested
that the DP PHY and PLL be split out of the drm driver and moved to the
qmp phy driver. This patch series does that, but it is still marked as
an RFC because there are a couple more things to do, mostly updating the
DT binding and getting agreement on how to structure the code.
Eventually I believe the qmp phy driver will need to listen for type-c
notifiers or somehow know the type-c pinout being used so this driver
can program things slightly differently. Right now, I don't have any way
to test it though, so I've left it as future work. For some more
details, the DP phy and the USB3 phy share the same physical pins on the
SoC and those pins pretty much line up with a type-c pinout modulo some
CC pins for cable orientation detection logic that lives on the PMIC. So
the DP phy can use all four lanes or it can use two lanes and the USB3
phy can use two lanes. In the hardware designs that I have access to it
is always two lanes for USB3 and two lanes for DP going through what
looks like a type-c pinout so this just hard codes that configuration in
the driver.
Here's the example node that I'm using on sc7180:
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>, // usb pll (or serdes)
<0 0x088e8000 0 0x38>, // dp com
<0 0x088ea000 0 0x40>; // dp pll (or serdes)
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x128>, // tx0
<0 0x088e9400 0 0x200>, // rx0
<0 0x088e9c00 0 0x218>, // pcs
<0 0x088e9600 0 0x128>, // tx1
<0 0x088e9800 0 0x200>, // rx1
<0 0x088e9a00 0 0x18>; // pcs misc
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>, // tx0
<0 0x088ea400 0 0x200>, // rx0
<0 0x088eaa00 0 0x200>, // dp phy
<0 0x088ea600 0 0x200>, // tx1
<0 0x088ea800 0 0x200>; // rx1
#clock-cells = <1>;
#phy-cells = <0>;
};
};
I had to put the serdes register region in the wrapper node and jam the
common area (dp_com) in the middle. Sort of a mess but it was the best I
could do to make the driver changes minimially invasive. I also had to
change the node names to 'usb3-phy' and 'dp-phy' from 'phy' so that I
could differentiate the different phys in the driver. Otherwise the qmp
driver was already mostly prepared for two different phys to sit next to
each other inside the phy wrapper so it was mostly just a chore of
moving code from one place to another.
I'll also point out that I found out the DP controller driver is
resetting the aux phy settings right after it configures it. The last
patch in this series rips out the DP PHY and PLL code from the drm
driver and wires in the phy API calls instead. In that same patch I also
fixed this aux reset behavior by removing the bit that resets the aux
phy. I believe that the aux configuration is broken in the DP driver
but I fixed it now I think.
Changes from RFC (https://lore.kernel.org/r/20200611091919.108018-1-swboyd@chromium.org)
* New patch for DT binding
* Rebased onto latest DP patch series
TODO:
* Clean up phy power on sequence a bit so that it is done in one place
instead of two
* Allow link rate to change after phy is powered on?
* Make the runtime PM logic detect combo phy and power down both?
Stephen Boyd (9):
dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information
phy: qcom-qmp: Move phy mode into struct qmp_phy
phy: qcom-qmp: Remove 'initialized' in favor of 'init_count'
phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'
phy: qcom-qmp: Get dp_com I/O resource by index
phy: qcom-qmp: Add support for DP in USB3+DP combo phy
phy: qcom-qmp: Add support for sc7180 DP phy
clk: qcom: dispcc: Update DP clk ops for phy design
drm/msm/dp: Use qmp phy for DP PLL and PHY
.../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 91 +-
drivers/clk/qcom/clk-rcg2.c | 19 +-
drivers/clk/qcom/dispcc-sc7180.c | 3 -
drivers/gpu/drm/msm/Makefile | 4 +-
drivers/gpu/drm/msm/dp/dp_aux.c | 7 +-
drivers/gpu/drm/msm/dp/dp_catalog.c | 253 +---
drivers/gpu/drm/msm/dp/dp_catalog.h | 7 +-
drivers/gpu/drm/msm/dp/dp_ctrl.c | 47 +-
drivers/gpu/drm/msm/dp/dp_display.c | 17 -
drivers/gpu/drm/msm/dp/dp_display.h | 3 -
drivers/gpu/drm/msm/dp/dp_link.c | 2 +
drivers/gpu/drm/msm/dp/dp_panel.c | 1 +
drivers/gpu/drm/msm/dp/dp_parser.c | 12 +-
drivers/gpu/drm/msm/dp/dp_parser.h | 12 +-
drivers/gpu/drm/msm/dp/dp_pll.c | 99 --
drivers/gpu/drm/msm/dp/dp_pll.h | 61 -
drivers/gpu/drm/msm/dp/dp_pll_10nm.c | 930 --------------
drivers/gpu/drm/msm/dp/dp_pll_private.h | 89 --
drivers/gpu/drm/msm/dp/dp_power.c | 39 +-
drivers/gpu/drm/msm/dp/dp_power.h | 9 -
drivers/phy/qualcomm/phy-qcom-qmp.c | 1114 ++++++++++++++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 80 ++
22 files changed, 1207 insertions(+), 1692 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll.c
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll.h
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll_10nm.c
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll_private.h
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Rob Clark <robdclark@chromium.org>
[1] https://lore.kernel.org/r/20200818051137.21478-1-tanmay@codeaurora.org
[2] https://lore.kernel.org/r/20200818230900.29294-1-khsieh@codeaurora.org
base-commit: 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5
prerequisite-patch-id: aa650e8353e003be0075deea0dee92a82e321432
prerequisite-patch-id: aa08019ebd00b502b4b76337dcef12939b5ed27d
prerequisite-patch-id: 87e6b1a10063ca350cacd64408024714599a14f4
prerequisite-patch-id: ac467cb99ea60ee186ab9bbe47a3e4d9c13a1313
prerequisite-patch-id: 48e1faa902cf53f64914f5a18e7a4296fa6a7bdd
prerequisite-patch-id: 6b2fb441138a10db425c5302638ea99ca00bf81d
--
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 1/9] dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information
2020-08-26 2:47 [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
@ 2020-08-26 2:47 ` Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 2/9] phy: qcom-qmp: Move phy mode into struct qmp_phy Stephen Boyd
` (7 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Jonathan Marek,
Dmitry Baryshkov, devicetreee, Rob Herring, Rob Clark
This binding only describes the USB phy inside the USB3 + DP "combo"
phy. Add information for the DP phy and describe the sub-nodes that
represent the DP and USB3 phys that exist inside the combo wrapper.
Remove reg-names from required properties because it isn't required nor
used by the kernel driver.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: <devicetreee@vger.kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
.../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 91 +++++++++++++++++--
1 file changed, 81 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
index ef8ae9f73092..4154f5748d39 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
@@ -17,13 +17,15 @@ properties:
- qcom,sdm845-qmp-usb3-phy
reg:
items:
- - description: Address and length of PHY's common serdes block.
+ - description: Address and length of PHY's USB serdes block.
- description: Address and length of the DP_COM control block.
+ - description: Address and length of PHY's DP serdes block.
reg-names:
items:
- - const: reg-base
+ - const: usb
- const: dp_com
+ - const: dp
"#clock-cells":
enum: [ 1, 2 ]
@@ -74,16 +76,74 @@ properties:
#Required nodes:
patternProperties:
- "^phy@[0-9a-f]+$":
+ "^usb3-phy@[0-9a-f]+$":
type: object
description:
- Each device node of QMP phy is required to have as many child nodes as
- the number of lanes the PHY has.
+ The USB3 PHY.
+
+ properties:
+ reg:
+ items:
+ - description: Address and length of TX.
+ - description: Address and length of RX.
+ - description: Address and length of PCS.
+ - description: Address and length of TX2.
+ - description: Address and length of RX2.
+ - description: Address and length of pcs_misc.
+
+ clocks:
+ items:
+ - description: pipe clock
+
+ clock-names:
+ items:
+ - const: pipe0
+
+ clock-output-names:
+ items:
+ - const: usb3_phy_pipe_clk_src
+
+ '#clock-cells':
+ const: 0
+
+ '#phy-cells':
+ const: 0
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#phy-cells'
+
+ "^dp-phy@[0-9a-f]+$":
+ type: object
+ description:
+ The DP PHY.
+
+ properties:
+ reg:
+ items:
+ - description: Address and length of TX.
+ - description: Address and length of RX.
+ - description: Address and length of PCS.
+ - description: Address and length of TX2.
+ - description: Address and length of RX2.
+
+ '#clock-cells':
+ const: 1
+
+ '#phy-cells':
+ const: 0
+
+ required:
+ - reg
+ - '#clock-cells'
+ - '#phy-cells'
required:
- compatible
- reg
- - reg-names
- "#clock-cells"
- "#address-cells"
- "#size-cells"
@@ -103,12 +163,13 @@ examples:
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sdm845-qmp-usb3-phy";
reg = <0x088e9000 0x18c>,
- <0x088e8000 0x10>;
- reg-names = "reg-base", "dp_com";
+ <0x088e8000 0x10>,
+ <0x088ea000 0x40>;
+ reg-names = "usb", "dp_com", "dp";
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x088e9000 0x1000>;
+ ranges = <0x0 0x088e9000 0x2000>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
@@ -123,7 +184,7 @@ examples:
vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>;
- phy@200 {
+ usb3-phy@200 {
reg = <0x200 0x128>,
<0x400 0x200>,
<0xc00 0x218>,
@@ -136,4 +197,14 @@ examples:
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
+
+ dp-phy@88ea200 {
+ reg = <0xa200 0x200>,
+ <0xa400 0x200>,
+ <0xaa00 0x200>,
+ <0xa600 0x200>,
+ <0xa800 0x200>;
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ };
};
--
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v1 2/9] phy: qcom-qmp: Move phy mode into struct qmp_phy
2020-08-26 2:47 [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 1/9] dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information Stephen Boyd
@ 2020-08-26 2:47 ` Stephen Boyd
2020-08-26 3:37 ` Bjorn Andersson
2020-08-26 2:47 ` [PATCH v1 3/9] phy: qcom-qmp: Remove 'initialized' in favor of 'init_count' Stephen Boyd
` (6 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Jonathan Marek,
Dmitry Baryshkov, Rob Clark
The phy mode pertains to the phy itself, i.e. 'struct qmp_phy', not the
wrapper, i.e. 'struct qcom_qmp'. Move the phy mode into the phy
structure to more accurately reflect what is going on. This also cleans
up 'struct qcom_qmp' so that it can eventually be the place where qmp
wrapper wide data is located, paving the way for the USB3+DP combo phy.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 562053ce9455..7ee9e966dc6d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1812,6 +1812,7 @@ struct qmp_phy_cfg {
* @index: lane index
* @qmp: QMP phy to which this lane belongs
* @lane_rst: lane's reset controller
+ * @mode: current PHY mode
*/
struct qmp_phy {
struct phy *phy;
@@ -1825,6 +1826,7 @@ struct qmp_phy {
unsigned int index;
struct qcom_qmp *qmp;
struct reset_control *lane_rst;
+ enum phy_mode mode;
};
/**
@@ -1843,7 +1845,6 @@ struct qmp_phy {
* @phy_mutex: mutex lock for PHY common block initialization
* @init_count: phy common block initialization count
* @phy_initialized: indicate if PHY has been initialized
- * @mode: current PHY mode
* @ufs_reset: optional UFS PHY reset handle
*/
struct qcom_qmp {
@@ -1861,7 +1862,6 @@ struct qcom_qmp {
struct mutex phy_mutex;
int init_count;
bool phy_initialized;
- enum phy_mode mode;
struct reset_control *ufs_reset;
};
@@ -2801,9 +2801,8 @@ static int qcom_qmp_phy_set_mode(struct phy *phy,
enum phy_mode mode, int submode)
{
struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
- qmp->mode = mode;
+ qphy->mode = mode;
return 0;
}
@@ -2816,8 +2815,8 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
void __iomem *pcs_misc = qphy->pcs_misc;
u32 intr_mask;
- if (qmp->mode == PHY_MODE_USB_HOST_SS ||
- qmp->mode == PHY_MODE_USB_DEVICE_SS)
+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
else
intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
@@ -2863,7 +2862,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
struct qmp_phy *qphy = qmp->phys[0];
const struct qmp_phy_cfg *cfg = qmp->cfg;
- dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
/* Supported only for USB3 PHY */
if (cfg->type != PHY_TYPE_USB3)
@@ -2889,7 +2888,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
const struct qmp_phy_cfg *cfg = qmp->cfg;
int ret = 0;
- dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
/* Supported only for USB3 PHY */
if (cfg->type != PHY_TYPE_USB3)
--
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* [PATCH v1 3/9] phy: qcom-qmp: Remove 'initialized' in favor of 'init_count'
2020-08-26 2:47 [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 1/9] dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 2/9] phy: qcom-qmp: Move phy mode into struct qmp_phy Stephen Boyd
@ 2020-08-26 2:47 ` Stephen Boyd
2020-08-26 3:44 ` Bjorn Andersson
2020-08-26 2:47 ` [PATCH v1 4/9] phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy' Stephen Boyd
` (5 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Jonathan Marek,
Dmitry Baryshkov, Rob Clark
We already track if any phy inside the qmp wrapper has been initialized
by means of the struct qcom_qmp::init_count member. Let's drop the
duplicate 'initialized' member to simplify the code a bit.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 7ee9e966dc6d..4a23ba9361b3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1844,7 +1844,6 @@ struct qmp_phy {
* @phys: array of per-lane phy descriptors
* @phy_mutex: mutex lock for PHY common block initialization
* @init_count: phy common block initialization count
- * @phy_initialized: indicate if PHY has been initialized
* @ufs_reset: optional UFS PHY reset handle
*/
struct qcom_qmp {
@@ -1861,7 +1860,6 @@ struct qcom_qmp {
struct mutex phy_mutex;
int init_count;
- bool phy_initialized;
struct reset_control *ufs_reset;
};
@@ -2748,7 +2746,6 @@ static int qcom_qmp_phy_enable(struct phy *phy)
dev_err(qmp->dev, "phy initialization timed-out\n");
goto err_pcs_ready;
}
- qmp->phy_initialized = true;
return 0;
err_pcs_ready:
@@ -2792,8 +2789,6 @@ static int qcom_qmp_phy_disable(struct phy *phy)
qcom_qmp_phy_com_exit(qmp);
- qmp->phy_initialized = false;
-
return 0;
}
@@ -2868,7 +2863,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
if (cfg->type != PHY_TYPE_USB3)
return 0;
- if (!qmp->phy_initialized) {
+ if (!qmp->init_count) {
dev_vdbg(dev, "PHY not initialized, bailing out\n");
return 0;
}
@@ -2894,7 +2889,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
if (cfg->type != PHY_TYPE_USB3)
return 0;
- if (!qmp->phy_initialized) {
+ if (!qmp->init_count) {
dev_vdbg(dev, "PHY not initialized, bailing out\n");
return 0;
}
--
Sent by a computer, using git, on the internet
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v1 4/9] phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'
2020-08-26 2:47 [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
` (2 preceding siblings ...)
2020-08-26 2:47 ` [PATCH v1 3/9] phy: qcom-qmp: Remove 'initialized' in favor of 'init_count' Stephen Boyd
@ 2020-08-26 2:47 ` Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 5/9] phy: qcom-qmp: Get dp_com I/O resource by index Stephen Boyd
` (4 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Jonathan Marek,
Dmitry Baryshkov, Rob Clark
The serdes I/O region is where the PLL for the phy is controlled.
Sometimes the PLL is shared between multiple phys, for example in the
PCIe case where there are three phys inside the same wrapper. Other
times the PLL is for a single phy, i.e. some USB3 phys. To complete the
trifecta we have the USB3+DP combo phy where the USB3 and DP phys each
have their own serdes region because they have their own PLL while they
both share a common I/O region pertaining to the USB type-c pinout and
cable orientation.
Let's move the serdes iomem pointer into 'struct qmp_phy' so that we can
correlate PLL control to the phy that uses it. This allows us to support
the USB3+DP combo phy in this driver. This isn't a problem for the
3-lane/phy PCIe phy because there is a common init function that is the
only place the serdes region is programmed.
Furthermore, move the configuration data that contains most of the
register programming sequences to the qmp phy struct. This data isn't
qmp wrapper specific. It is phy specific data used to tune various
settings for things like pre-emphasis, bias, etc.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 113 ++++++++++++++--------------
1 file changed, 56 insertions(+), 57 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 4a23ba9361b3..40c051813c34 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1802,6 +1802,8 @@ struct qmp_phy_cfg {
* struct qmp_phy - per-lane phy descriptor
*
* @phy: generic phy
+ * @cfg: phy specific configuration
+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
* @tx: iomapped memory space for lane's tx
* @rx: iomapped memory space for lane's rx
* @pcs: iomapped memory space for lane's pcs
@@ -1816,6 +1818,8 @@ struct qmp_phy_cfg {
*/
struct qmp_phy {
struct phy *phy;
+ const struct qmp_phy_cfg *cfg;
+ void __iomem *serdes;
void __iomem *tx;
void __iomem *rx;
void __iomem *pcs;
@@ -1833,14 +1837,12 @@ struct qmp_phy {
* struct qcom_qmp - structure holding QMP phy block attributes
*
* @dev: device
- * @serdes: iomapped memory space for phy's serdes
* @dp_com: iomapped memory space for phy's dp_com control block
*
* @clks: array of clocks required by phy
* @resets: array of resets required by phy
* @vregs: regulator supplies bulk data
*
- * @cfg: phy specific configuration
* @phys: array of per-lane phy descriptors
* @phy_mutex: mutex lock for PHY common block initialization
* @init_count: phy common block initialization count
@@ -1848,14 +1850,12 @@ struct qmp_phy {
*/
struct qcom_qmp {
struct device *dev;
- void __iomem *serdes;
void __iomem *dp_com;
struct clk_bulk_data *clks;
struct reset_control **resets;
struct regulator_bulk_data *vregs;
- const struct qmp_phy_cfg *cfg;
struct qmp_phy **phys;
struct mutex phy_mutex;
@@ -2478,8 +2478,8 @@ static void qcom_qmp_phy_configure(void __iomem *base,
static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
{
struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qmp->cfg;
- void __iomem *serdes = qmp->serdes;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *serdes = qphy->serdes;
void __iomem *pcs = qphy->pcs;
void __iomem *dp_com = qmp->dp_com;
int ret, i;
@@ -2510,7 +2510,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
ret = reset_control_deassert(qmp->resets[i]);
if (ret) {
dev_err(qmp->dev, "%s reset deassert failed\n",
- qmp->cfg->reset_list[i]);
+ qphy->cfg->reset_list[i]);
goto err_rst;
}
}
@@ -2592,10 +2592,11 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
return ret;
}
-static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
{
- const struct qmp_phy_cfg *cfg = qmp->cfg;
- void __iomem *serdes = qmp->serdes;
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *serdes = qphy->serdes;
int i = cfg->num_resets;
mutex_lock(&qmp->phy_mutex);
@@ -2630,7 +2631,7 @@ static int qcom_qmp_phy_enable(struct phy *phy)
{
struct qmp_phy *qphy = phy_get_drvdata(phy);
struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qmp->cfg;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
void __iomem *tx = qphy->tx;
void __iomem *rx = qphy->rx;
void __iomem *pcs = qphy->pcs;
@@ -2755,7 +2756,7 @@ static int qcom_qmp_phy_enable(struct phy *phy)
if (cfg->has_lane_rst)
reset_control_assert(qphy->lane_rst);
err_lane_rst:
- qcom_qmp_phy_com_exit(qmp);
+ qcom_qmp_phy_com_exit(qphy);
return ret;
}
@@ -2763,8 +2764,7 @@ static int qcom_qmp_phy_enable(struct phy *phy)
static int qcom_qmp_phy_disable(struct phy *phy)
{
struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qmp->cfg;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
clk_disable_unprepare(qphy->pipe_clk);
@@ -2787,7 +2787,7 @@ static int qcom_qmp_phy_disable(struct phy *phy)
if (cfg->has_lane_rst)
reset_control_assert(qphy->lane_rst);
- qcom_qmp_phy_com_exit(qmp);
+ qcom_qmp_phy_com_exit(qphy);
return 0;
}
@@ -2804,8 +2804,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy,
static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
{
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qmp->cfg;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
void __iomem *pcs = qphy->pcs;
void __iomem *pcs_misc = qphy->pcs_misc;
u32 intr_mask;
@@ -2834,8 +2833,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
{
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qmp->cfg;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
void __iomem *pcs = qphy->pcs;
void __iomem *pcs_misc = qphy->pcs_misc;
@@ -2855,7 +2853,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
{
struct qcom_qmp *qmp = dev_get_drvdata(dev);
struct qmp_phy *qphy = qmp->phys[0];
- const struct qmp_phy_cfg *cfg = qmp->cfg;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
@@ -2880,7 +2878,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
{
struct qcom_qmp *qmp = dev_get_drvdata(dev);
struct qmp_phy *qphy = qmp->phys[0];
- const struct qmp_phy_cfg *cfg = qmp->cfg;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
int ret = 0;
dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
@@ -2912,10 +2910,10 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
return 0;
}
-static int qcom_qmp_phy_vreg_init(struct device *dev)
+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
{
struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int num = qmp->cfg->num_vregs;
+ int num = cfg->num_vregs;
int i;
qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
@@ -2923,24 +2921,24 @@ static int qcom_qmp_phy_vreg_init(struct device *dev)
return -ENOMEM;
for (i = 0; i < num; i++)
- qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
+ qmp->vregs[i].supply = cfg->vreg_list[i];
return devm_regulator_bulk_get(dev, num, qmp->vregs);
}
-static int qcom_qmp_phy_reset_init(struct device *dev)
+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
{
struct qcom_qmp *qmp = dev_get_drvdata(dev);
int i;
- qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
sizeof(*qmp->resets), GFP_KERNEL);
if (!qmp->resets)
return -ENOMEM;
- for (i = 0; i < qmp->cfg->num_resets; i++) {
+ for (i = 0; i < cfg->num_resets; i++) {
struct reset_control *rst;
- const char *name = qmp->cfg->reset_list[i];
+ const char *name = cfg->reset_list[i];
rst = devm_reset_control_get(dev, name);
if (IS_ERR(rst)) {
@@ -2953,10 +2951,10 @@ static int qcom_qmp_phy_reset_init(struct device *dev)
return 0;
}
-static int qcom_qmp_phy_clk_init(struct device *dev)
+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
{
struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int num = qmp->cfg->num_clks;
+ int num = cfg->num_clks;
int i;
qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
@@ -2964,7 +2962,7 @@ static int qcom_qmp_phy_clk_init(struct device *dev)
return -ENOMEM;
for (i = 0; i < num; i++)
- qmp->clks[i].id = qmp->cfg->clk_list[i];
+ qmp->clks[i].id = cfg->clk_list[i];
return devm_clk_bulk_get(dev, num, qmp->clks);
}
@@ -2998,12 +2996,6 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
struct clk_init_data init = { };
int ret;
- if ((qmp->cfg->type != PHY_TYPE_USB3) &&
- (qmp->cfg->type != PHY_TYPE_PCIE)) {
- /* not all phys register pipe clocks, so return success */
- return 0;
- }
-
ret = of_property_read_string(np, "clock-output-names", &init.name);
if (ret) {
dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
@@ -3054,7 +3046,8 @@ static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
};
static
-int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
{
struct qcom_qmp *qmp = dev_get_drvdata(dev);
struct phy *generic_phy;
@@ -3067,6 +3060,8 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
if (!qphy)
return -ENOMEM;
+ qphy->cfg = cfg;
+ qphy->serdes = serdes;
/*
* Get memory resources for each phy lane:
* Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
@@ -3091,7 +3086,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
* back to old legacy behavior of assuming they can be reached at an
* offset from the first lane.
*/
- if (qmp->cfg->is_dual_lane_phy) {
+ if (cfg->is_dual_lane_phy) {
qphy->tx2 = of_iomap(np, 3);
qphy->rx2 = of_iomap(np, 4);
if (!qphy->tx2 || !qphy->rx2) {
@@ -3124,8 +3119,8 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
if (IS_ERR(qphy->pipe_clk)) {
- if (qmp->cfg->type == PHY_TYPE_PCIE ||
- qmp->cfg->type == PHY_TYPE_USB3) {
+ if (cfg->type == PHY_TYPE_PCIE ||
+ cfg->type == PHY_TYPE_USB3) {
ret = PTR_ERR(qphy->pipe_clk);
if (ret != -EPROBE_DEFER)
dev_err(dev,
@@ -3137,7 +3132,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
}
/* Get lane reset, if any */
- if (qmp->cfg->has_lane_rst) {
+ if (cfg->has_lane_rst) {
snprintf(prop_name, sizeof(prop_name), "lane%d", id);
qphy->lane_rst = of_reset_control_get(np, prop_name);
if (IS_ERR(qphy->lane_rst)) {
@@ -3146,7 +3141,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
}
}
- if (qmp->cfg->type == PHY_TYPE_UFS || qmp->cfg->type == PHY_TYPE_PCIE)
+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
ops = &qcom_qmp_pcie_ufs_ops;
generic_phy = devm_phy_create(dev, np, ops);
@@ -3244,6 +3239,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
struct device_node *child;
struct phy_provider *phy_provider;
void __iomem *base;
+ void __iomem *serdes;
+ const struct qmp_phy_cfg *cfg;
int num, id;
int ret;
@@ -3255,8 +3252,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
dev_set_drvdata(dev, qmp);
/* Get the specific init parameters of QMP phy */
- qmp->cfg = of_device_get_match_data(dev);
- if (!qmp->cfg)
+ cfg = of_device_get_match_data(dev);
+ if (!cfg)
return -EINVAL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -3265,10 +3262,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
return PTR_ERR(base);
/* per PHY serdes; usually located at base address */
- qmp->serdes = base;
+ serdes = base;
/* per PHY dp_com; if PHY has dp_com control block */
- if (qmp->cfg->has_phy_dp_com_ctrl) {
+ if (cfg->has_phy_dp_com_ctrl) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"dp_com");
base = devm_ioremap_resource(dev, res);
@@ -3280,15 +3277,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
mutex_init(&qmp->phy_mutex);
- ret = qcom_qmp_phy_clk_init(dev);
+ ret = qcom_qmp_phy_clk_init(dev, cfg);
if (ret)
return ret;
- ret = qcom_qmp_phy_reset_init(dev);
+ ret = qcom_qmp_phy_reset_init(dev, cfg);
if (ret)
return ret;
- ret = qcom_qmp_phy_vreg_init(dev);
+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
if (ret) {
if (ret != -EPROBE_DEFER)
dev_err(dev, "failed to get regulator supplies: %d\n",
@@ -3298,7 +3295,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
num = of_get_available_child_count(dev->of_node);
/* do we have a rogue child node ? */
- if (num > qmp->cfg->nlanes)
+ if (num > cfg->nlanes)
return -EINVAL;
qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
@@ -3316,7 +3313,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
for_each_available_child_of_node(dev->of_node, child) {
/* Create per-lane phy */
- ret = qcom_qmp_phy_create(dev, child, id);
+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
if (ret) {
dev_err(dev, "failed to create lane%d phy, %d\n",
id, ret);
@@ -3327,11 +3324,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
* Register the pipe clock provided by phy.
* See function description to see details of this pipe clock.
*/
- ret = phy_pipe_clk_register(qmp, child);
- if (ret) {
- dev_err(qmp->dev,
- "failed to register pipe clock source\n");
- goto err_node_put;
+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
+ ret = phy_pipe_clk_register(qmp, child);
+ if (ret) {
+ dev_err(qmp->dev,
+ "failed to register pipe clock source\n");
+ goto err_node_put;
+ }
}
id++;
}
--
Sent by a computer, using git, on the internet
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v1 5/9] phy: qcom-qmp: Get dp_com I/O resource by index
2020-08-26 2:47 [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
` (3 preceding siblings ...)
2020-08-26 2:47 ` [PATCH v1 4/9] phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy' Stephen Boyd
@ 2020-08-26 2:47 ` Stephen Boyd
2020-08-26 4:36 ` Bjorn Andersson
2020-08-26 2:47 ` [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy Stephen Boyd
` (3 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Jonathan Marek,
Dmitry Baryshkov, Rob Clark
The dp_com resource is always at index 1 according to the dts files in
the kernel. Get this resource by index so that we don't need to make
future additions to the DT binding use 'reg-names'.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 40c051813c34..76d7a9e80f04 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -3266,8 +3266,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
/* per PHY dp_com; if PHY has dp_com control block */
if (cfg->has_phy_dp_com_ctrl) {
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "dp_com");
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
--
Sent by a computer, using git, on the internet
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy
2020-08-26 2:47 [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
` (4 preceding siblings ...)
2020-08-26 2:47 ` [PATCH v1 5/9] phy: qcom-qmp: Get dp_com I/O resource by index Stephen Boyd
@ 2020-08-26 2:47 ` Stephen Boyd
2020-09-01 13:36 ` Dmitry Baryshkov
2020-08-26 2:47 ` [PATCH v1 7/9] phy: qcom-qmp: Add support for sc7180 DP phy Stephen Boyd
` (2 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Stephen Boyd,
Jonathan Marek, Dmitry Baryshkov, Rob Clark
Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy
driver. We already have support for the USB3 part of the combo phy, so
most additions are for the DP phy.
Split up the qcom_qmp_phy{enable,disable}() functions into the phy init,
power on, power off, and exit functions that the common phy framework
expects so that the DP phy can add even more phy ops like
phy_calibrate() and phy_configure(). This allows us to initialize the DP
PHY and configure the AUX channel before powering on the PHY at the link
rate that was negotiated during link training.
The general design is as follows:
1) DP controller calls phy_init() to initialize the PHY and configure
the dp_com register region.
2) DP controller calls phy_configure() to tune the link rate and
voltage swing and pre-emphasis settings.
3) DP controller calls phy_power_on() to enable the PLL and power on
the phy.
4) DP controller calls phy_configure() again to tune the voltage swing
and pre-emphasis settings determind during link training.
5) DP controller calls phy_calibrate() some number of times to change
the aux settings if the aux channel times out during link training.
6) DP controller calls phy_power_off() if the link rate is to be
changed and goes back to step 2 to try again at a different link rate.
5) DP controller calls phy_power_off() and then phy_exit() to power
down the PHY when it is done.
The DP PHY contains a PLL that is different from the one used for the
USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk
output from the DP PLL after going through various dividers. Introduce
clk ops for these two clks that just tell the child clks what the
frequency of the pixel and link are. When the phy link rate is
configured we call clk_set_rate() to update the child clks in the
display clk controller on what rate is in use. The clk frequencies
always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or
8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or
HBR3) so we simply store the link rate and use that to calculate the clk
frequencies.
The PLL enable sequence is a little different from other QMP phy PLLs so
we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called
from phy_power_on(). This should probably be split out better so that
each phy has a way to run the final PLL/PHY enable sequence.
This code is based on a submission of this phy and PLL in the drm
subsystem.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 935 +++++++++++++++++++++++++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 80 +++
2 files changed, 926 insertions(+), 89 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 76d7a9e80f04..dd77c7dfa310 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -947,6 +947,130 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
};
+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+};
+
+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+};
+
+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+};
+
+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+};
+
static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
@@ -1798,6 +1922,11 @@ struct qmp_phy_cfg {
bool no_pcs_sw_reset;
};
+struct qmp_phy_combo_cfg {
+ const struct qmp_phy_cfg *usb_cfg;
+ const struct qmp_phy_cfg *dp_cfg;
+};
+
/**
* struct qmp_phy - per-lane phy descriptor
*
@@ -1831,6 +1960,15 @@ struct qmp_phy {
struct qcom_qmp *qmp;
struct reset_control *lane_rst;
enum phy_mode mode;
+ unsigned int dp_aux_cfg;
+ struct phy_configure_opts_dp dp_opts;
+ struct qmp_phy_dp_clks *dp_clks;
+};
+
+struct qmp_phy_dp_clks {
+ struct qmp_phy *qphy;
+ struct clk_hw dp_link_hw;
+ struct clk_hw dp_pixel_hw;
};
/**
@@ -2475,6 +2613,329 @@ static void qcom_qmp_phy_configure(void __iomem *base,
qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
}
+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
+{
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *serdes = qphy->serdes;
+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+ const struct qmp_phy_init_tbl *serdes_tbl;
+ int serdes_tbl_num;
+ int ret;
+
+ if (cfg->type == PHY_TYPE_DP) {
+ switch (dp_opts->link_rate) {
+ case 1620:
+ serdes_tbl = qmp_v3_dp_serdes_tbl_rbr;
+ serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr);
+ break;
+ case 2700:
+ serdes_tbl = qmp_v3_dp_serdes_tbl_hbr;
+ serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr);
+ break;
+ case 5400:
+ serdes_tbl = qmp_v3_dp_serdes_tbl_hbr2;
+ serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2);
+ break;
+ case 8100:
+ serdes_tbl = qmp_v3_dp_serdes_tbl_hbr3;
+ serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3);
+ break;
+ default:
+ /* Other link rates aren't supported */
+ return -EINVAL;
+ }
+ } else {
+ serdes_tbl = cfg->serdes_tbl;
+ serdes_tbl_num = cfg->serdes_tbl_num;
+ }
+
+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
+
+ if (cfg->has_phy_com_ctrl) {
+ void __iomem *status;
+ unsigned int mask, val;
+
+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
+ SERDES_START | PCS_START);
+
+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
+ mask = cfg->mask_com_pcs_ready;
+
+ ret = readl_poll_timeout(status, val, (val & mask), 10,
+ PHY_INIT_COMPLETE_TIMEOUT);
+ if (ret) {
+ dev_err(qmp->dev,
+ "phy common block init timed-out\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy)
+{
+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
+ qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+
+ /* Turn on BIAS current for PHY/PLL */
+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
+
+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+
+ /* Make sure that hardware is done with PSR power down */
+ wmb();
+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
+ DP_PHY_PD_CTL_DP_CLAMP_EN,
+ qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+
+ writel(QSERDES_V3_COM_BIAS_EN |
+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
+
+ writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
+ writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
+ writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
+ writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
+ writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
+ writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
+ writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
+ writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
+ writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
+ writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
+ qphy->dp_aux_cfg = 0;
+
+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
+ PHY_AUX_REQ_ERR_MASK,
+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
+}
+
+static const u8 vm_pre_emphasis[4][4] = {
+ { 0x00, 0x0b, 0x12, 0xff }, /* pe0, 0 db */
+ { 0x00, 0x0a, 0x12, 0xff }, /* pe1, 3.5 db */
+ { 0x00, 0x0c, 0xff, 0xff }, /* pe2, 6.0 db */
+ { 0xff, 0xff, 0xff, 0xff } /* pe3, 9.5 db */
+};
+
+/* voltage swing, 0.2v and 1.0v are not support */
+static const u8 vm_voltage_swing[4][4] = {
+ { 0x07, 0x0f, 0x14, 0xff }, /* sw0, 0.4v */
+ { 0x11, 0x1d, 0x1f, 0xff }, /* sw1, 0.6 v */
+ { 0x18, 0x1f, 0xff, 0xff }, /* sw1, 0.8 v */
+ { 0xff, 0xff, 0xff, 0xff } /* sw1, 1.2 v, optional */
+};
+
+static const u8 vm_pre_emphasis_hbr3_hbr2[4][4] = {
+ { 0x00, 0x0c, 0x15, 0x1a },
+ { 0x02, 0x0e, 0x16, 0xff },
+ { 0x02, 0x11, 0xff, 0xff },
+ { 0x04, 0xff, 0xff, 0xff }
+};
+
+static const u8 vm_voltage_swing_hbr3_hbr2[4][4] = {
+ { 0x02, 0x12, 0x16, 0x1a },
+ { 0x09, 0x19, 0x1f, 0xff },
+ { 0x10, 0x1f, 0xff, 0xff },
+ { 0x1f, 0xff, 0xff, 0xff }
+};
+
+static const u8 vm_pre_emphasis_hbr_rbr[4][4] = {
+ { 0x00, 0x0c, 0x14, 0x19 },
+ { 0x00, 0x0b, 0x12, 0xff },
+ { 0x00, 0x0b, 0xff, 0xff },
+ { 0x04, 0xff, 0xff, 0xff }
+};
+
+static const u8 vm_voltage_swing_hbr_rbr[4][4] = {
+ { 0x08, 0x0f, 0x16, 0x1f },
+ { 0x11, 0x1e, 0x1f, 0xff },
+ { 0x19, 0x1f, 0xff, 0xff },
+ { 0x1f, 0xff, 0xff, 0xff }
+};
+
+static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy)
+{
+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+ unsigned int v_level = 0, p_level = 0;
+ u32 bias_en, drvr_en;
+ u8 voltage_swing_cfg, pre_emphasis_cfg;
+ int i;
+
+ for (i = 0; i < dp_opts->lanes; i++) {
+ v_level = max(v_level, dp_opts->voltage[i]);
+ p_level = max(p_level, dp_opts->pre[i]);
+ }
+
+ if (dp_opts->lanes == 1) {
+ bias_en = 0x3e;
+ drvr_en = 0x13;
+ } else {
+ bias_en = 0x3f;
+ drvr_en = 0x10;
+ }
+
+ /* TODO: Pick based on link rate */
+ voltage_swing_cfg = vm_voltage_swing_hbr_rbr[v_level][p_level];
+ pre_emphasis_cfg = vm_pre_emphasis_hbr_rbr[v_level][p_level];
+
+ /* TODO: Move check to config check */
+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
+ return;
+
+ /* Enable MUX to use Cursor values from these registers */
+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
+
+ writel(voltage_swing_cfg, qphy->tx + QSERDES_V3_TX_TX_DRV_LVL);
+ writel(pre_emphasis_cfg, qphy->tx + QSERDES_V3_TX_TX_EMP_POST1_LVL);
+ writel(voltage_swing_cfg, qphy->tx2 + QSERDES_V3_TX_TX_DRV_LVL);
+ writel(pre_emphasis_cfg, qphy->tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL);
+
+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
+}
+
+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
+{
+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+
+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
+ if (qphy->dp_opts.set_voltages) {
+ qcom_qmp_phy_configure_dp_tx(qphy);
+ qphy->dp_opts.set_voltages = 0;
+ }
+
+ return 0;
+}
+
+static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy)
+{
+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
+ u32 val, phy_vco_div, status;
+ unsigned long pixel_freq;
+
+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
+
+ /*
+ if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
+ val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
+ if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
+ */
+ /*
+ * TODO: Assume orientation is CC1 for now and two lanes, need to
+ * use type-c connector to understand orientation and lanes
+ */
+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
+
+ writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+
+ /*
+ if (orientation == ORIENTATION_CC2)
+ writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
+ else
+ */
+ /* does this do anything? link_clock_sel_mux isn't set (bit 5) */
+ writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
+
+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
+
+ switch (dp_opts->link_rate) {
+ case 1620:
+ phy_vco_div = 0x1;
+ pixel_freq = 1620000000UL / 2;
+ break;
+ case 2700:
+ phy_vco_div = 0x1;
+ pixel_freq = 2700000000UL / 2;
+ break;
+ case 5400:
+ phy_vco_div = 0x2;
+ pixel_freq = 5400000000UL / 4;
+ break;
+ case 8100:
+ phy_vco_div = 0x0;
+ pixel_freq = 8100000000UL / 6;
+ break;
+ default:
+ /* Other link rates aren't supported */
+ return -EINVAL;
+ }
+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
+
+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
+
+ writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
+ writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+ writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+ writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+
+ writel(0x20, qphy->serdes + QSERDES_COM_RESETSM_CNTRL);
+
+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
+ status,
+ ((status & BIT(0)) > 0),
+ 500,
+ 10000))
+ return -ETIMEDOUT;
+
+ writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+
+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
+ status,
+ ((status & BIT(1)) > 0),
+ 500,
+ 10000))
+ return -ETIMEDOUT;
+
+ writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+ udelay(2000);
+ writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
+
+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
+ status,
+ ((status & BIT(1)) > 0),
+ 500,
+ 10000);
+}
+
+/*
+ * We need to calibrate the aux setting here as many times
+ * as the caller tries
+ */
+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
+{
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
+ u8 val;
+
+ qphy->dp_aux_cfg++;
+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
+ val = cfg1_settings[qphy->dp_aux_cfg];
+
+ writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
+
+ return 0;
+}
+
static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
{
struct qcom_qmp *qmp = qphy->qmp;
@@ -2529,6 +2990,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
+ /* Default type-c orientation, i.e CC1 */
+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
+
qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
USB3_MODE | DP_MODE);
@@ -2536,6 +3000,9 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
+
+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
}
if (cfg->has_phy_com_ctrl) {
@@ -2551,36 +3018,10 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
cfg->pwrdn_ctrl);
}
- /* Serdes configuration */
- qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
- cfg->serdes_tbl_num);
-
- if (cfg->has_phy_com_ctrl) {
- void __iomem *status;
- unsigned int mask, val;
-
- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
- SERDES_START | PCS_START);
-
- status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
- mask = cfg->mask_com_pcs_ready;
-
- ret = readl_poll_timeout(status, val, (val & mask), 10,
- PHY_INIT_COMPLETE_TIMEOUT);
- if (ret) {
- dev_err(qmp->dev,
- "phy common block init timed-out\n");
- goto err_com_init;
- }
- }
-
mutex_unlock(&qmp->phy_mutex);
return 0;
-err_com_init:
- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
err_rst:
while (++i < cfg->num_resets)
reset_control_assert(qmp->resets[i]);
@@ -2627,20 +3068,12 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
return 0;
}
-static int qcom_qmp_phy_enable(struct phy *phy)
+static int qcom_qmp_phy_init(struct phy *phy)
{
struct qmp_phy *qphy = phy_get_drvdata(phy);
struct qcom_qmp *qmp = qphy->qmp;
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *tx = qphy->tx;
- void __iomem *rx = qphy->rx;
- void __iomem *pcs = qphy->pcs;
- void __iomem *pcs_misc = qphy->pcs_misc;
- void __iomem *dp_com = qmp->dp_com;
- void __iomem *status;
- unsigned int mask, val, ready;
int ret;
-
dev_vdbg(qmp->dev, "Initializing QMP phy\n");
if (cfg->no_pcs_sw_reset) {
@@ -2667,13 +3100,34 @@ static int qcom_qmp_phy_enable(struct phy *phy)
ret = reset_control_assert(qmp->ufs_reset);
if (ret)
- goto err_lane_rst;
+ return ret;
}
ret = qcom_qmp_phy_com_init(qphy);
if (ret)
return ret;
+ if (cfg->type == PHY_TYPE_DP)
+ qcom_qmp_phy_dp_aux_init(qphy);
+
+ return 0;
+}
+
+static int qcom_qmp_phy_power_on(struct phy *phy)
+{
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ struct qcom_qmp *qmp = qphy->qmp;
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *tx = qphy->tx;
+ void __iomem *rx = qphy->rx;
+ void __iomem *pcs = qphy->pcs;
+ void __iomem *pcs_misc = qphy->pcs_misc;
+ void __iomem *status;
+ unsigned int mask, val, ready;
+ int ret;
+
+ qcom_qmp_phy_serdes_init(qphy);
+
if (cfg->has_lane_rst) {
ret = reset_control_deassert(qphy->lane_rst);
if (ret) {
@@ -2697,13 +3151,24 @@ static int qcom_qmp_phy_enable(struct phy *phy)
qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
cfg->tx_tbl, cfg->tx_tbl_num, 2);
+ /* Configure special DP tx tunings */
+ if (cfg->type == PHY_TYPE_DP)
+ qcom_qmp_phy_configure_dp_tx(qphy);
+
qcom_qmp_phy_configure_lane(rx, cfg->regs,
cfg->rx_tbl, cfg->rx_tbl_num, 1);
+
if (cfg->is_dual_lane_phy)
qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
cfg->rx_tbl, cfg->rx_tbl_num, 2);
- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+ /* Configure link rate, swing, etc. */
+ if (cfg->type == PHY_TYPE_DP) {
+ qcom_qmp_phy_configure_dp_phy(qphy);
+ } else {
+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
+ }
+
ret = reset_control_deassert(qmp->ufs_reset);
if (ret)
goto err_lane_rst;
@@ -2721,69 +3186,77 @@ static int qcom_qmp_phy_enable(struct phy *phy)
if (cfg->has_pwrdn_delay)
usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
- /* Pull PHY out of reset state */
- if (!cfg->no_pcs_sw_reset)
- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-
- if (cfg->has_phy_dp_com_ctrl)
- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-
- /* start SerDes and Phy-Coding-Sublayer */
- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
- if (cfg->type == PHY_TYPE_UFS) {
- status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
- mask = PCS_READY;
- ready = PCS_READY;
- } else {
- status = pcs + cfg->regs[QPHY_PCS_STATUS];
- mask = PHYSTATUS;
- ready = 0;
- }
+ if (cfg->type != PHY_TYPE_DP) {
+ /* Pull PHY out of reset state */
+ if (!cfg->no_pcs_sw_reset)
+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+ /* start SerDes and Phy-Coding-Sublayer */
+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+
+ if (cfg->type == PHY_TYPE_UFS) {
+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
+ mask = PCS_READY;
+ ready = PCS_READY;
+ } else {
+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
+ mask = PHYSTATUS;
+ ready = 0;
+ }
- ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
- PHY_INIT_COMPLETE_TIMEOUT);
- if (ret) {
- dev_err(qmp->dev, "phy initialization timed-out\n");
- goto err_pcs_ready;
+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
+ PHY_INIT_COMPLETE_TIMEOUT);
+ if (ret) {
+ dev_err(qmp->dev, "phy initialization timed-out\n");
+ goto err_pcs_ready;
+ }
}
return 0;
err_pcs_ready:
- reset_control_assert(qmp->ufs_reset);
clk_disable_unprepare(qphy->pipe_clk);
err_clk_enable:
if (cfg->has_lane_rst)
reset_control_assert(qphy->lane_rst);
err_lane_rst:
- qcom_qmp_phy_com_exit(qphy);
-
return ret;
}
-static int qcom_qmp_phy_disable(struct phy *phy)
+static int qcom_qmp_phy_power_off(struct phy *phy)
{
struct qmp_phy *qphy = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qphy->cfg;
clk_disable_unprepare(qphy->pipe_clk);
- /* PHY reset */
- if (!cfg->no_pcs_sw_reset)
- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+ if (cfg->type == PHY_TYPE_DP) {
+ /* Assert DP PHY power down */
+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
+ } else {
+ /* PHY reset */
+ if (!cfg->no_pcs_sw_reset)
+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
- /* stop SerDes and Phy-Coding-Sublayer */
- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+ /* stop SerDes and Phy-Coding-Sublayer */
+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
- /* Put PHY into POWER DOWN state: active low */
- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
- cfg->pwrdn_ctrl);
- } else {
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
- cfg->pwrdn_ctrl);
+ /* Put PHY into POWER DOWN state: active low */
+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
+ cfg->pwrdn_ctrl);
+ } else {
+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ cfg->pwrdn_ctrl);
+ }
}
+ return 0;
+}
+
+static int qcom_qmp_phy_exit(struct phy *phy)
+{
+ struct qmp_phy *qphy = phy_get_drvdata(phy);
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+
if (cfg->has_lane_rst)
reset_control_assert(qphy->lane_rst);
@@ -2792,6 +3265,31 @@ static int qcom_qmp_phy_disable(struct phy *phy)
return 0;
}
+static int qcom_qmp_phy_enable(struct phy *phy)
+{
+ int ret;
+
+ ret = qcom_qmp_phy_init(phy);
+ if (ret)
+ return ret;
+
+ ret = qcom_qmp_phy_power_on(phy);
+ if (ret)
+ qcom_qmp_phy_exit(phy);
+
+ return ret;
+}
+
+static int qcom_qmp_phy_disable(struct phy *phy)
+{
+ int ret;
+
+ ret = qcom_qmp_phy_power_off(phy);
+ if (ret)
+ return ret;
+ return qcom_qmp_phy_exit(phy);
+}
+
static int qcom_qmp_phy_set_mode(struct phy *phy,
enum phy_mode mode, int submode)
{
@@ -2857,7 +3355,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
- /* Supported only for USB3 PHY */
+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
if (cfg->type != PHY_TYPE_USB3)
return 0;
@@ -2883,7 +3381,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
- /* Supported only for USB3 PHY */
+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
if (cfg->type != PHY_TYPE_USB3)
return 0;
@@ -2967,7 +3465,7 @@ static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *c
return devm_clk_bulk_get(dev, num, qmp->clks);
}
-static void phy_pipe_clk_release_provider(void *res)
+static void phy_clk_release_provider(void *res)
{
of_clk_del_provider(res);
}
@@ -3024,9 +3522,202 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
* Roll a devm action because the clock provider is the child node, but
* the child node is not actually a device.
*/
- ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np);
+ ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
if (ret)
- phy_pipe_clk_release_provider(np);
+ phy_clk_release_provider(np);
+
+ return ret;
+}
+
+/*
+ * Display Port PLL driver block diagram for branch clocks
+ *
+ * +------------------------------+
+ * | DP_VCO_CLK |
+ * | |
+ * | +-------------------+ |
+ * | | (DP PLL/VCO) | |
+ * | +---------+---------+ |
+ * | v |
+ * | +----------+-----------+ |
+ * | | hsclk_divsel_clk_src | |
+ * | +----------+-----------+ |
+ * +------------------------------+
+ * |
+ * +---------<---------v------------>----------+
+ * | |
+ * +--------v----------------+ |
+ * | dp_phy_pll_link_clk | |
+ * | link_clk | |
+ * +--------+----------------+ |
+ * | |
+ * | |
+ * v v
+ * Input to DISPCC block |
+ * for link clk, crypto clk |
+ * and interface clock |
+ * |
+ * |
+ * +--------<------------+-----------------+---<---+
+ * | | |
+ * +----v---------+ +--------v-----+ +--------v------+
+ * | vco_divided | | vco_divided | | vco_divided |
+ * | _clk_src | | _clk_src | | _clk_src |
+ * | | | | | |
+ * |divsel_six | | divsel_two | | divsel_four |
+ * +-------+------+ +-----+--------+ +--------+------+
+ * | | |
+ * v---->----------v-------------<------v
+ * |
+ * +----------+-----------------+
+ * | dp_phy_pll_vco_div_clk |
+ * +---------+------------------+
+ * |
+ * v
+ * Input to DISPCC block
+ * for DP pixel clock
+ *
+ */
+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ switch (req->rate) {
+ case 1620000000UL / 2:
+ case 2700000000UL / 2:
+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static unsigned long
+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ const struct qmp_phy_dp_clks *dp_clks;
+ const struct qmp_phy *qphy;
+ const struct phy_configure_opts_dp *dp_opts;
+
+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
+ qphy = dp_clks->qphy;
+ dp_opts = &qphy->dp_opts;
+
+ switch (dp_opts->link_rate) {
+ case 1620:
+ return 1620000000UL / 2;
+ case 2700:
+ return 2700000000UL / 2;
+ case 5400:
+ return 5400000000UL / 4;
+ case 8100:
+ return 8100000000UL / 6;
+ default:
+ return 0;
+ }
+}
+
+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
+};
+
+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ switch (req->rate) {
+ case 162000000:
+ case 270000000:
+ case 540000000:
+ case 810000000:
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static unsigned long
+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ const struct qmp_phy_dp_clks *dp_clks;
+ const struct qmp_phy *qphy;
+ const struct phy_configure_opts_dp *dp_opts;
+
+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
+ qphy = dp_clks->qphy;
+ dp_opts = &qphy->dp_opts;
+
+ switch (dp_opts->link_rate) {
+ case 1620:
+ case 2700:
+ case 5400:
+ case 8100:
+ return dp_opts->link_rate * 100000;
+ default:
+ return 0;
+ }
+}
+
+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
+};
+
+static struct clk_hw *
+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct qmp_phy_dp_clks *dp_clks = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= 2) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (idx == 0)
+ return &dp_clks->dp_link_hw;
+
+ return &dp_clks->dp_pixel_hw;
+}
+
+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
+ struct device_node *np)
+{
+ struct clk_init_data init = { };
+ struct qmp_phy_dp_clks *dp_clks;
+ int ret;
+
+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
+ if (!dp_clks)
+ return -ENOMEM;
+
+ dp_clks->qphy = qphy;
+ qphy->dp_clks = dp_clks;
+
+ init.ops = &qcom_qmp_dp_link_clk_ops;
+ init.name = "qmp_dp_phy_pll_link_clk";
+ dp_clks->dp_link_hw.init = &init;
+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
+ if (ret)
+ return ret;
+
+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
+ init.name = "qmp_dp_phy_pll_vco_div_clk";
+ dp_clks->dp_pixel_hw.init = &init;
+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
+ if (ret)
+ return ret;
+
+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
+ if (ret)
+ return ret;
+
+ /*
+ * Roll a devm action because the clock provider is the child node, but
+ * the child node is not actually a device.
+ */
+ ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
+ if (ret)
+ phy_clk_release_provider(np);
return ret;
}
@@ -3038,6 +3729,17 @@ static const struct phy_ops qcom_qmp_phy_gen_ops = {
.owner = THIS_MODULE,
};
+static const struct phy_ops qcom_qmp_phy_dp_ops = {
+ .init = qcom_qmp_phy_init,
+ .configure = qcom_qmp_dp_phy_configure,
+ .power_on = qcom_qmp_phy_power_on,
+ .calibrate = qcom_qmp_dp_phy_calibrate,
+ .power_off = qcom_qmp_phy_power_off,
+ .exit = qcom_qmp_phy_exit,
+ .set_mode = qcom_qmp_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
.power_on = qcom_qmp_phy_enable,
.power_off = qcom_qmp_phy_disable,
@@ -3052,7 +3754,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
struct qcom_qmp *qmp = dev_get_drvdata(dev);
struct phy *generic_phy;
struct qmp_phy *qphy;
- const struct phy_ops *ops = &qcom_qmp_phy_gen_ops;
+ const struct phy_ops *ops;
char prop_name[MAX_PROP_NAME];
int ret;
@@ -3143,6 +3845,10 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
ops = &qcom_qmp_pcie_ufs_ops;
+ else if (cfg->type == PHY_TYPE_DP)
+ ops = &qcom_qmp_phy_dp_ops;
+ else
+ ops = &qcom_qmp_phy_gen_ops;
generic_phy = devm_phy_create(dev, np, ops);
if (IS_ERR(generic_phy)) {
@@ -3226,6 +3932,10 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
};
MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
+ { }
+};
+
static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
qcom_qmp_phy_runtime_resume, NULL)
@@ -3240,8 +3950,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
struct phy_provider *phy_provider;
void __iomem *base;
void __iomem *serdes;
+ void __iomem *usb_serdes;
+ void __iomem *dp_serdes;
+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
const struct qmp_phy_cfg *cfg;
- int num, id;
+ const struct qmp_phy_cfg *usb_cfg;
+ const struct qmp_phy_cfg *dp_cfg;
+ int num, id, expected_phys;
int ret;
qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
@@ -3253,8 +3968,20 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
/* Get the specific init parameters of QMP phy */
cfg = of_device_get_match_data(dev);
- if (!cfg)
- return -EINVAL;
+ if (!cfg) {
+ const struct of_device_id *match;
+
+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
+ if (!match)
+ return -EINVAL;
+
+ combo_cfg = match->data;
+ if (!combo_cfg)
+ return -EINVAL;
+
+ usb_cfg = combo_cfg->usb_cfg;
+ cfg = usb_cfg; /* Setup clks and regulators */
+ }
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
@@ -3263,9 +3990,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
/* per PHY serdes; usually located at base address */
serdes = base;
+ usb_serdes = base;
/* per PHY dp_com; if PHY has dp_com control block */
- if (cfg->has_phy_dp_com_ctrl) {
+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base))
@@ -3274,6 +4002,20 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
qmp->dp_com = base;
}
+ if (combo_cfg) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ /* Only two serdes for combo PHY */
+ dp_serdes = base;
+ dp_cfg = combo_cfg->dp_cfg;
+ expected_phys = 2;
+ } else {
+ expected_phys = cfg->nlanes;
+ }
+
mutex_init(&qmp->phy_mutex);
ret = qcom_qmp_phy_clk_init(dev, cfg);
@@ -3294,14 +4036,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
num = of_get_available_child_count(dev->of_node);
/* do we have a rogue child node ? */
- if (num > cfg->nlanes)
+ if (num > expected_phys)
return -EINVAL;
qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
if (!qmp->phys)
return -ENOMEM;
- id = 0;
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
/*
@@ -3310,7 +4051,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
*/
pm_runtime_forbid(dev);
+ id = 0;
for_each_available_child_of_node(dev->of_node, child) {
+ if (of_node_name_eq(child, "dp-phy")) {
+ cfg = dp_cfg;
+ serdes = dp_serdes;
+ } else if (of_node_name_eq(child, "usb3-phy")) {
+ cfg = usb_cfg;
+ serdes = usb_serdes;
+ }
+
/* Create per-lane phy */
ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
if (ret) {
@@ -3330,6 +4080,13 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
"failed to register pipe clock source\n");
goto err_node_put;
}
+ } else if (cfg->type == PHY_TYPE_DP) {
+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
+ if (ret) {
+ dev_err(qmp->dev,
+ "failed to register DP clock source\n");
+ goto err_node_put;
+ }
}
id++;
}
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 4277f592684b..5de1f25fc166 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -135,6 +135,9 @@
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
/* Only for QMP V3 PHY - QSERDES COM registers */
+#define QSERDES_V3_COM_ATB_SEL1 0x000
+#define QSERDES_V3_COM_ATB_SEL2 0x004
+#define QSERDES_V3_COM_FREQ_UPDATE 0x008
#define QSERDES_V3_COM_BG_TIMER 0x00c
#define QSERDES_V3_COM_SSC_EN_CENTER 0x010
#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
@@ -144,6 +147,13 @@
#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
+# define QSERDES_V3_COM_BIAS_EN 0x0001
+# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
+# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
+# define QSERDES_V3_COM_CLKBUF_L_EN 0x0008
+# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
+# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
+# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
#define QSERDES_V3_COM_CLK_ENABLE1 0x038
#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
@@ -205,12 +215,36 @@
#define QSERDES_V3_COM_CMN_MODE 0x184
/* Only for QMP V3 PHY - TX registers */
+#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
+#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
+#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
+# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
+# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
+
+#define QSERDES_V3_TX_TX_DRV_LVL 0x01c
+# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
+# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
+
+#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
+#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
+
+#define QSERDES_V3_TX_TX_BAND 0x02c
+#define QSERDES_V3_TX_SLEW_CNTL 0x030
+#define QSERDES_V3_TX_INTERFACE_SELECT 0x034
+#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
+#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040
#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048
#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058
+#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c
#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060
+#define QSERDES_V3_TX_TX_POL_INV 0x064
+#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068
#define QSERDES_V3_TX_LANE_MODE_1 0x08c
#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
+#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0
+#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4
+#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0
/* Only for QMP V3 PHY - RX registers */
#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008
@@ -313,6 +347,52 @@
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
+/* Only for QMP V3 PHY - DP PHY registers */
+#define QSERDES_V3_DP_PHY_REVISION_ID0 0x000
+#define QSERDES_V3_DP_PHY_REVISION_ID1 0x004
+#define QSERDES_V3_DP_PHY_REVISION_ID2 0x008
+#define QSERDES_V3_DP_PHY_REVISION_ID3 0x00c
+#define QSERDES_V3_DP_PHY_CFG 0x010
+#define QSERDES_V3_DP_PHY_PD_CTL 0x018
+# define DP_PHY_PD_CTL_PWRDN 0x001
+# define DP_PHY_PD_CTL_PSR_PWRDN 0x002
+# define DP_PHY_PD_CTL_AUX_PWRDN 0x004
+# define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008
+# define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010
+# define DP_PHY_PD_CTL_PLL_PWRDN 0x020
+# define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040
+#define QSERDES_V3_DP_PHY_MODE 0x01c
+#define QSERDES_V3_DP_PHY_AUX_CFG0 0x020
+#define QSERDES_V3_DP_PHY_AUX_CFG1 0x024
+#define QSERDES_V3_DP_PHY_AUX_CFG2 0x028
+#define QSERDES_V3_DP_PHY_AUX_CFG3 0x02c
+#define QSERDES_V3_DP_PHY_AUX_CFG4 0x030
+#define QSERDES_V3_DP_PHY_AUX_CFG5 0x034
+#define QSERDES_V3_DP_PHY_AUX_CFG6 0x038
+#define QSERDES_V3_DP_PHY_AUX_CFG7 0x03c
+#define QSERDES_V3_DP_PHY_AUX_CFG8 0x040
+#define QSERDES_V3_DP_PHY_AUX_CFG9 0x044
+
+#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048
+# define PHY_AUX_STOP_ERR_MASK 0x01
+# define PHY_AUX_DEC_ERR_MASK 0x02
+# define PHY_AUX_SYNC_ERR_MASK 0x04
+# define PHY_AUX_ALIGN_ERR_MASK 0x08
+# define PHY_AUX_REQ_ERR_MASK 0x10
+
+#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
+#define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050
+
+#define QSERDES_V3_DP_PHY_VCO_DIV 0x064
+#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c
+#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088
+
+#define QSERDES_V3_DP_PHY_SPARE0 0x0ac
+#define DP_PHY_SPARE0_MASK 0x0f
+#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004)
+
+#define QSERDES_V3_DP_PHY_STATUS 0x0c0
+
/* Only for QMP V4 PHY - QSERDES COM registers */
#define QSERDES_V4_COM_SSC_EN_CENTER 0x010
#define QSERDES_V4_COM_SSC_PER1 0x01c
--
Sent by a computer, using git, on the internet
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v1 7/9] phy: qcom-qmp: Add support for sc7180 DP phy
2020-08-26 2:47 [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
` (5 preceding siblings ...)
2020-08-26 2:47 ` [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy Stephen Boyd
@ 2020-08-26 2:47 ` Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 8/9] clk: qcom: dispcc: Update DP clk ops for phy design Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 9/9] drm/msm/dp: Use qmp phy for DP PLL and PHY Stephen Boyd
8 siblings, 0 replies; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Jonathan Marek,
Dmitry Baryshkov, Rob Clark
Add the necessary compatible strings and phy data for the sc7180 USB3+DP
combo phy.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 47 +++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index dd77c7dfa310..84fba3437a20 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1071,6 +1071,24 @@ static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
};
+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
+};
+
static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
@@ -2337,6 +2355,28 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
.is_dual_lane_phy = true,
};
+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
+ .type = PHY_TYPE_DP,
+ .nlanes = 1,
+
+ .tx_tbl = qmp_v3_dp_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
+ .clk_list = qmp_v3_phy_clk_l,
+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+ .reset_list = sc7180_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+
+ .has_phy_dp_com_ctrl = true,
+ .is_dual_lane_phy = true,
+};
+
+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
+ .usb_cfg = &sc7180_usb3phy_cfg,
+ .dp_cfg = &sc7180_dpphy_cfg,
+};
+
static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
.type = PHY_TYPE_USB3,
.nlanes = 1,
@@ -3891,6 +3931,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
}, {
.compatible = "qcom,sc7180-qmp-usb3-phy",
.data = &sc7180_usb3phy_cfg,
+ }, {
+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
+ /* It's a combo phy */
}, {
.compatible = "qcom,sdm845-qhp-pcie-phy",
.data = &sdm845_qhp_pciephy_cfg,
@@ -3933,6 +3976,10 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
+ {
+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
+ .data = &sc7180_usb3dpphy_cfg,
+ },
{ }
};
--
Sent by a computer, using git, on the internet
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v1 8/9] clk: qcom: dispcc: Update DP clk ops for phy design
2020-08-26 2:47 [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
` (6 preceding siblings ...)
2020-08-26 2:47 ` [PATCH v1 7/9] phy: qcom-qmp: Add support for sc7180 DP phy Stephen Boyd
@ 2020-08-26 2:47 ` Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 9/9] drm/msm/dp: Use qmp phy for DP PLL and PHY Stephen Boyd
8 siblings, 0 replies; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Stephen Boyd,
Jonathan Marek, Dmitry Baryshkov, Rob Clark
The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk.
This function should return the rate that can be achieved by the pixel
clk in 'struct clk_rate_request::rate' and match the logic similar to
what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead
the code merely bubbles the rate request up to the parent of the pixel
clk and doesn't try to do a rational approximation of the rate that
would be achieved by picking some m/n value for the RCG.
Let's change this logic so that we can assume the parent clk frequency
is fixed (it is because it's the VCO of the DP PLL that is configured
based on the link rate) and so that we can calculate what the m/n value
will be and adjust the req->rate appropriately.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/clk/qcom/clk-rcg2.c | 19 +++++++++++++------
drivers/clk/qcom/dispcc-sc7180.c | 3 ---
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 357159fe85b5..59a5a0f261f3 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1182,14 +1182,21 @@ static int clk_rcg2_dp_set_rate_and_parent(struct clk_hw *hw,
static int clk_rcg2_dp_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
- struct clk_rate_request parent_req = *req;
- int ret;
+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+ unsigned long num, den;
+ u64 tmp;
- ret = __clk_determine_rate(clk_hw_get_parent(hw), &parent_req);
- if (ret)
- return ret;
+ /* Parent rate is a fixed phy link rate */
+ rational_best_approximation(req->best_parent_rate, req->rate,
+ GENMASK(rcg->mnd_width - 1, 0),
+ GENMASK(rcg->mnd_width - 1, 0), &den, &num);
+
+ if (!num || !den)
+ return -EINVAL;
- req->best_parent_rate = parent_req.rate;
+ tmp = req->best_parent_rate * num;
+ do_div(tmp, den);
+ req->rate = tmp;
return 0;
}
diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c
index 0a5d395bce93..f487515701e3 100644
--- a/drivers/clk/qcom/dispcc-sc7180.c
+++ b/drivers/clk/qcom/dispcc-sc7180.c
@@ -202,7 +202,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
- .flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
@@ -216,7 +215,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
- .flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
};
@@ -230,7 +228,6 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
- .flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
};
--
Sent by a computer, using git, on the internet
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v1 9/9] drm/msm/dp: Use qmp phy for DP PLL and PHY
2020-08-26 2:47 [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
` (7 preceding siblings ...)
2020-08-26 2:47 ` [PATCH v1 8/9] clk: qcom: dispcc: Update DP clk ops for phy design Stephen Boyd
@ 2020-08-26 2:47 ` Stephen Boyd
8 siblings, 0 replies; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Jonathan Marek,
Dmitry Baryshkov, Rob Clark
Make the necessary changes to the DP driver to use the qmp phy from the
common phy framework instead of rolling our own in the drm subsystem.
This also removes the PLL code and adds proper includes so things build.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/gpu/drm/msm/Makefile | 4 +-
drivers/gpu/drm/msm/dp/dp_aux.c | 7 +-
drivers/gpu/drm/msm/dp/dp_catalog.c | 253 +------
drivers/gpu/drm/msm/dp/dp_catalog.h | 7 +-
drivers/gpu/drm/msm/dp/dp_ctrl.c | 47 +-
drivers/gpu/drm/msm/dp/dp_display.c | 17 -
drivers/gpu/drm/msm/dp/dp_display.h | 3 -
drivers/gpu/drm/msm/dp/dp_link.c | 2 +
drivers/gpu/drm/msm/dp/dp_panel.c | 1 +
drivers/gpu/drm/msm/dp/dp_parser.c | 12 +-
drivers/gpu/drm/msm/dp/dp_parser.h | 12 +-
drivers/gpu/drm/msm/dp/dp_pll.c | 99 ---
drivers/gpu/drm/msm/dp/dp_pll.h | 61 --
drivers/gpu/drm/msm/dp/dp_pll_10nm.c | 930 ------------------------
drivers/gpu/drm/msm/dp/dp_pll_private.h | 89 ---
drivers/gpu/drm/msm/dp/dp_power.c | 39 +-
drivers/gpu/drm/msm/dp/dp_power.h | 9 -
17 files changed, 78 insertions(+), 1514 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll.c
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll.h
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll_10nm.c
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll_private.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 6d31188cc776..af868e791210 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -109,9 +109,7 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_link.o \
dp/dp_panel.o \
dp/dp_parser.o \
- dp/dp_power.o \
- dp/dp_pll.o \
- dp/dp_pll_10nm.o
+ dp/dp_power.o
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o
diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c
index 5aaa4b50c303..1d03f13a0cb0 100644
--- a/drivers/gpu/drm/msm/dp/dp_aux.c
+++ b/drivers/gpu/drm/msm/dp/dp_aux.c
@@ -4,6 +4,7 @@
*/
#include <linux/delay.h>
+#include <drm/drm_print.h>
#include "dp_reg.h"
#include "dp_aux.h"
@@ -357,8 +358,7 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux,
if (aux->native) {
aux->retry_cnt++;
if (!(aux->retry_cnt % retry_count))
- dp_catalog_aux_update_cfg(aux->catalog,
- PHY_AUX_CFG1);
+ dp_catalog_aux_update_cfg(aux->catalog);
dp_catalog_aux_reset(aux->catalog);
}
usleep_range(400, 500); /* at least 400us to next try */
@@ -415,7 +415,7 @@ void dp_aux_reconfig(struct drm_dp_aux *dp_aux)
aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
- dp_catalog_aux_update_cfg(aux->catalog, PHY_AUX_CFG1);
+ dp_catalog_aux_update_cfg(aux->catalog);
dp_catalog_aux_reset(aux->catalog);
}
@@ -430,7 +430,6 @@ void dp_aux_init(struct drm_dp_aux *dp_aux)
aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
- dp_catalog_aux_setup(aux->catalog);
dp_catalog_aux_enable(aux->catalog, true);
aux->retry_cnt = 0;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
index f92a8e37a312..66074c44766e 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -8,8 +8,11 @@
#include <linux/rational.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-dp.h>
#include <linux/rational.h>
#include <drm/drm_dp_helper.h>
+#include <drm/drm_print.h>
#include "dp_catalog.h"
#include "dp_reg.h"
@@ -128,83 +131,6 @@ static inline void dp_write_ahb(struct dp_catalog_private *catalog,
writel(data, catalog->io->dp_controller.base + offset);
}
-static inline void dp_write_phy(struct dp_catalog_private *catalog,
- u32 offset, u32 data)
-{
- offset += DP_PHY_REG_OFFSET;
- /*
- * To make sure phy reg writes happens before any other operation,
- * this function uses writel() instread of writel_relaxed()
- */
- writel(data, catalog->io->phy_reg.base + offset);
-}
-
-static inline u32 dp_read_phy(struct dp_catalog_private *catalog,
- u32 offset)
-{
- offset += DP_PHY_REG_OFFSET;
- /*
- * To make sure phy reg writes happens before any other operation,
- * this function uses writel() instread of writel_relaxed()
- */
- return readl_relaxed(catalog->io->phy_reg.base + offset);
-}
-
-static inline void dp_write_pll(struct dp_catalog_private *catalog,
- u32 offset, u32 data)
-{
- offset += DP_PHY_PLL_OFFSET;
- writel_relaxed(data, catalog->io->phy_reg.base + offset);
-}
-
-static inline void dp_write_ln_tx0(struct dp_catalog_private *catalog,
- u32 offset, u32 data)
-{
- offset += DP_PHY_LN_TX0_OFFSET;
- writel_relaxed(data, catalog->io->phy_reg.base + offset);
-}
-
-static inline void dp_write_ln_tx1(struct dp_catalog_private *catalog,
- u32 offset, u32 data)
-{
- offset += DP_PHY_LN_TX1_OFFSET;
- writel_relaxed(data, catalog->io->phy_reg.base + offset);
-}
-
-static inline u32 dp_read_ln_tx0(struct dp_catalog_private *catalog,
- u32 offset)
-{
- offset += DP_PHY_LN_TX0_OFFSET;
- return readl_relaxed(catalog->io->phy_reg.base + offset);
-}
-
-static inline u32 dp_read_ln_tx1(struct dp_catalog_private *catalog,
- u32 offset)
-{
- offset += DP_PHY_LN_TX1_OFFSET;
- return readl_relaxed(catalog->io->phy_reg.base + offset);
-}
-
-static inline void dp_write_usb_cm(struct dp_catalog_private *catalog,
- u32 offset, u32 data)
-{
- /*
- * To make sure usb reg writes happens before any other operation,
- * this function uses writel() instread of writel_relaxed()
- */
- writel(data, catalog->io->usb3_dp_com.base + offset);
-}
-
-static inline u32 dp_read_usb_cm(struct dp_catalog_private *catalog,
- u32 offset)
-{
- /*
- * To make sure usb reg writes happens before any other operation,
- * this function uses writel() instread of writel_relaxed()
- */
- return readl_relaxed(catalog->io->usb3_dp_com.base + offset);
-}
-
static inline void dp_write_p0(struct dp_catalog_private *catalog,
u32 offset, u32 data)
{
@@ -322,27 +248,14 @@ void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable)
dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl);
}
-void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog,
- enum dp_phy_aux_config_type type)
+void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- u32 new_index = 0, current_index = 0;
+ struct dp_io *dp_io = catalog->io;
+ struct phy *phy = dp_io->phy;
- if (type >= PHY_AUX_CFG_MAX) {
- DRM_ERROR("invalid input\n");
- return;
- }
-
- current_index = catalog->aux_lut_cfg_index[type];
- new_index = (current_index + 1) % DP_AUX_CFG_MAX_VALUE_CNT;
- DRM_DEBUG_DP("Updating PHY_AUX_CFG%d from 0x%08x to 0x%08x\n",
- type, aux_lut_value[type][current_index],
- aux_lut_value[type][new_index]);
-
- dp_write_phy(catalog, aux_lut_offset[type],
- aux_lut_value[type][new_index]);
- catalog->aux_lut_cfg_index[type] = new_index;
+ phy_calibrate(phy);
}
static void dump_regs(void __iomem *base, int len)
@@ -388,64 +301,6 @@ void dp_catalog_dump_regs(struct dp_catalog *dp_catalog)
offset = MSM_DP_CONTROLLER_P0_OFFSET;
len = MSM_DP_CONTROLLER_P0_SIZE;
dump_regs(catalog->io->dp_controller.base + offset, len);
-
- pr_info("USB3 DP COM regs\n");
- dump_regs(catalog->io->usb3_dp_com.base, catalog->io->usb3_dp_com.len);
-
- pr_info("LN TX0 regs\n");
- dump_regs(catalog->io->phy_reg.base + DP_PHY_LN_TX0_OFFSET,
- DP_PHY_LN_TX0_SIZE);
-
- pr_info("LN TX1 regs\n");
- dump_regs(catalog->io->phy_reg.base + DP_PHY_LN_TX1_OFFSET,
- DP_PHY_LN_TX1_SIZE);
-
- pr_info("DP PHY regs\n");
- dump_regs(catalog->io->phy_reg.base + DP_PHY_REG_OFFSET,
- DP_PHY_REG_SIZE);
-}
-
-void dp_catalog_aux_setup(struct dp_catalog *dp_catalog)
-{
- struct dp_catalog_private *catalog = container_of(dp_catalog,
- struct dp_catalog_private, dp_catalog);
- int i = 0;
-
- dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PWRDN |
- DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
- DP_PHY_PD_CTL_DP_CLAMP_EN);
-
- /* Turn on BIAS current for PHY/PLL */
- dp_write_pll(catalog,
- QSERDES_COM_BIAS_EN_CLKBUFLR_EN, QSERDES_COM_BIAS_EN |
- QSERDES_COM_BIAS_EN_MUX | QSERDES_COM_CLKBUF_L_EN |
- QSERDES_COM_EN_SYSCLK_TX_SEL);
-
- dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PSR_PWRDN);
-
- dp_write_phy(catalog, REG_DP_PHY_PD_CTL, DP_PHY_PD_CTL_PWRDN |
- DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN
- | DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN
- | DP_PHY_PD_CTL_DP_CLAMP_EN);
-
- dp_write_pll(catalog,
- QSERDES_COM_BIAS_EN_CLKBUFLR_EN, QSERDES_COM_BIAS_EN |
- QSERDES_COM_BIAS_EN_MUX | QSERDES_COM_CLKBUF_R_EN |
- QSERDES_COM_CLKBUF_L_EN | QSERDES_COM_EN_SYSCLK_TX_SEL |
- QSERDES_COM_CLKBUF_RX_DRIVE_L);
-
- /* DP AUX CFG register programming */
- for (i = 0; i < PHY_AUX_CFG_MAX; i++) {
- DRM_DEBUG_DP("PHY_AUX_CFG%ds: offset=0x%08x, value=0x%08x\n",
- i, aux_lut_offset[i], aux_lut_value[i][0]);
- dp_write_phy(catalog, aux_lut_offset[i],
- aux_lut_value[i][0]);
- }
-
- dp_write_phy(catalog, REG_DP_PHY_AUX_INTERRUPT_MASK,
- PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
- PHY_AUX_REQ_ERR_MASK);
}
int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
@@ -569,7 +424,7 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
bool fixed_nvid)
{
u32 pixel_m, pixel_n;
- u32 mvid, nvid, div, pixel_div = 0, dispcc_input_rate;
+ u32 mvid, nvid, pixel_div = 0, dispcc_input_rate;
u32 const nvid_fixed = DP_LINK_CONSTANT_N_VALUE;
u32 const link_rate_hbr2 = 540000;
u32 const link_rate_hbr3 = 810000;
@@ -578,14 +433,11 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- div = dp_read_phy(catalog, REG_DP_PHY_VCO_DIV);
- div &= 0x03;
-
- if (div == 0)
+ if (rate == link_rate_hbr3)
pixel_div = 6;
- else if (div == 1)
+ else if (rate == 1620000 || rate == 270000)
pixel_div = 2;
- else if (div == 2)
+ else if (rate == link_rate_hbr2)
pixel_div = 4;
else
DRM_ERROR("Invalid pixel mux divider\n");
@@ -651,36 +503,6 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog,
return 0;
}
-void dp_catalog_ctrl_usb_reset(struct dp_catalog *dp_catalog, bool flip)
-{
- struct dp_catalog_private *catalog = container_of(dp_catalog,
- struct dp_catalog_private, dp_catalog);
- u32 typec_ctrl;
-
- dp_write_usb_cm(catalog, REG_USB3_DP_COM_RESET_OVRD_CTRL,
- USB3_DP_COM_OVRD_CTRL_SW_DPPHY_RESET_MUX |
- USB3_DP_COM_OVRD_CTRL_SW_USB3PHY_RESET_MUX);
- dp_write_usb_cm(catalog, REG_USB3_DP_COM_PHY_MODE_CTRL,
- USB3_DP_COM_PHY_MODE_DP);
- dp_write_usb_cm(catalog, REG_USB3_DP_COM_SW_RESET,
- USB3_DP_COM_SW_RESET_SET);
-
- /* Default configuration i.e CC1 */
- typec_ctrl = USB3_DP_COM_TYPEC_CTRL_PORTSEL_MUX;
- if (flip)
- typec_ctrl |= USB3_DP_COM_TYPEC_CTRL_PORTSEL;
-
- dp_write_usb_cm(catalog, REG_USB3_DP_COM_TYPEC_CTRL, typec_ctrl);
-
- dp_write_usb_cm(catalog, REG_USB3_DP_COM_SWI_CTRL, 0x00);
- dp_write_usb_cm(catalog, REG_USB3_DP_COM_SW_RESET, 0x00);
-
- dp_write_usb_cm(catalog, REG_USB3_DP_COM_POWER_DOWN_CTRL,
- USB3_DP_COM_POWER_DOWN_CTRL_SW_PWRDN);
- dp_write_usb_cm(catalog, REG_USB3_DP_COM_RESET_OVRD_CTRL, 0x00);
-
-}
-
void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog)
{
u32 sw_reset;
@@ -803,59 +625,26 @@ void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog)
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- dp_write_ahb(catalog, REG_DP_PHY_CTRL,
- DP_PHY_CTRL_SW_RESET_PLL | DP_PHY_CTRL_SW_RESET);
+ dp_write_ahb(catalog, REG_DP_PHY_CTRL, DP_PHY_CTRL_SW_RESET_PLL);
usleep_range(1000, 1100); /* h/w recommended delay */
dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0);
}
-void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog *dp_catalog,
- bool flipped, u8 ln_cnt)
-{
- u32 info;
- struct dp_catalog_private *catalog = container_of(dp_catalog,
- struct dp_catalog_private, dp_catalog);
- u8 orientation = BIT(!!flipped);
-
- info = ln_cnt & DP_PHY_SPARE0_MASK;
- info |= (orientation & DP_PHY_SPARE0_MASK)
- << DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT;
- DRM_DEBUG_DP("Shared Info = 0x%x\n", info);
-
- dp_write_phy(catalog, REG_DP_PHY_SPARE0, info);
-}
-
int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog,
u8 v_level, u8 p_level)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- u8 voltage_swing_cfg, pre_emphasis_cfg;
-
- DRM_DEBUG_DP("hw: v=%d p=%d\n", v_level, p_level);
-
- voltage_swing_cfg = vm_voltage_swing_hbr_rbr[v_level][p_level];
- pre_emphasis_cfg = vm_pre_emphasis_hbr_rbr[v_level][p_level];
-
- if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) {
- DRM_ERROR("invalid vx (0x%x=0x%x), px (0x%x=0x%x\n",
- v_level, voltage_swing_cfg, p_level, pre_emphasis_cfg);
- return -EINVAL;
- }
+ struct dp_io *dp_io = catalog->io;
+ struct phy *phy = dp_io->phy;
+ struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
- /* Enable MUX to use Cursor values from these registers */
- voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
- pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-
- /* Configure host and panel only if both values are allowed */
- dp_write_ln_tx0(catalog, REG_DP_PHY_TXn_TX_DRV_LVL, voltage_swing_cfg);
- dp_write_ln_tx1(catalog, REG_DP_PHY_TXn_TX_DRV_LVL, voltage_swing_cfg);
- dp_write_ln_tx0(catalog, REG_DP_PHY_TXn_TX_EMP_POST1_LVL,
- pre_emphasis_cfg);
- dp_write_ln_tx1(catalog, REG_DP_PHY_TXn_TX_EMP_POST1_LVL,
- pre_emphasis_cfg);
- DRM_DEBUG_DP("hw: vx_value=0x%x px_value=0x%x\n",
- voltage_swing_cfg, pre_emphasis_cfg);
+ /* TODO: Update for all lanes instead of just first one */
+ opts_dp->voltage[0] = v_level;
+ opts_dp->pre[0] = p_level;
+ opts_dp->set_voltages = 1;
+ phy_configure(phy, &dp_io->phy_opts);
+ opts_dp->set_voltages = 0;
return 0;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
index bcd381bfc9cd..201b49d1d84c 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -6,6 +6,8 @@
#ifndef _DP_CATALOG_H_
#define _DP_CATALOG_H_
+#include <drm/drm_modes.h>
+
#include "dp_parser.h"
/* interrupts */
@@ -57,8 +59,7 @@ int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog);
int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read);
void dp_catalog_aux_reset(struct dp_catalog *dp_catalog);
void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable);
-void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog,
- enum dp_phy_aux_config_type type);
+void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog);
void dp_catalog_aux_setup(struct dp_catalog *dp_catalog);
int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
@@ -80,8 +81,6 @@ void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog);
u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog);
-void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog *dp_catalog, bool flipped,
- u8 lane_cnt);
int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level,
u8 p_level);
int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog);
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 70b0e06953f6..b590aff6eecc 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -8,8 +8,11 @@
#include <linux/types.h>
#include <linux/completion.h>
#include <linux/delay.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-dp.h>
#include <drm/drm_fixed.h>
#include <drm/drm_dp_helper.h>
+#include <drm/drm_print.h>
#include "dp_reg.h"
#include "dp_ctrl.h"
@@ -1302,7 +1305,7 @@ static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
}
static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
- enum dp_pm_type module, char *name, u32 rate)
+ enum dp_pm_type module, char *name, unsigned long rate)
{
u32 num = ctrl->parser->mp[module].num_clk;
struct dss_clk *cfg = ctrl->parser->mp[module].clk_config;
@@ -1312,23 +1315,29 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
cfg++;
}
- DRM_DEBUG_DP("setting rate=%d on clk=%s\n", rate, name);
+ DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name);
if (num)
cfg->rate = rate;
else
- DRM_ERROR("%s clock doesn't exit to set rate %d\n",
+ DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
name, rate);
}
static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
{
int ret = 0;
+ struct dp_io *dp_io = &ctrl->parser->io;
+ struct phy *phy = dp_io->phy;
+ struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
- dp_power_set_link_clk_parent(ctrl->power);
-
+ opts_dp->lanes = ctrl->link->link_params.num_lanes;
+ opts_dp->link_rate = ctrl->link->link_params.rate / 100;
dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
- ctrl->link->link_params.rate);
+ ctrl->link->link_params.rate * 1000);
+
+ phy_configure(phy, &dp_io->phy_opts);
+ phy_power_on(phy);
ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
if (ret)
@@ -1345,7 +1354,7 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
int ret = 0;
dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
- ctrl->dp_ctrl.pixel_rate);
+ ctrl->dp_ctrl.pixel_rate * 1000);
ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
if (ret)
@@ -1360,6 +1369,8 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip)
{
struct dp_ctrl_private *ctrl;
+ struct dp_io *dp_io;
+ struct phy *phy;
if (!dp_ctrl) {
DRM_ERROR("Invalid input data\n");
@@ -1367,10 +1378,12 @@ int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip)
}
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+ dp_io = &ctrl->parser->io;
+ phy = dp_io->phy;
ctrl->dp_ctrl.orientation = flip;
- dp_catalog_ctrl_usb_reset(ctrl->catalog, flip);
+ phy_init(phy);
dp_catalog_ctrl_phy_reset(ctrl->catalog);
dp_catalog_ctrl_enable_irq(ctrl->catalog, true);
@@ -1420,10 +1433,13 @@ static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
{
int ret = 0;
+ struct dp_io *dp_io = &ctrl->parser->io;
+ struct phy *phy = dp_io->phy;
+ struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
- dp_catalog_ctrl_phy_lane_cfg(ctrl->catalog,
- ctrl->dp_ctrl.orientation, ctrl->link->link_params.num_lanes);
+ opts_dp->lanes = ctrl->link->link_params.num_lanes;
+ phy_configure(phy, &dp_io->phy_opts);
/*
* Disable and re-enable the mainlink clock since the
* link clock might have been adjusted as part of the
@@ -1434,6 +1450,7 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
return ret;
}
+ phy_power_off(phy);
/* hw recommended delay before re-enabling clocks */
msleep(20);
@@ -1622,10 +1639,6 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
ctrl->link->link_params.rate,
ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
- dp_catalog_ctrl_phy_lane_cfg(ctrl->catalog,
- ctrl->dp_ctrl.orientation,
- ctrl->link->link_params.num_lanes);
-
rc = dp_ctrl_enable_mainlink_clocks(ctrl);
if (rc)
return rc;
@@ -1763,12 +1776,16 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
{
struct dp_ctrl_private *ctrl;
+ struct dp_io *dp_io;
+ struct phy *phy;
int ret = 0;
if (!dp_ctrl)
return -EINVAL;
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+ dp_io = &ctrl->parser->io;
+ phy = dp_io->phy;
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
@@ -1783,6 +1800,8 @@ int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
}
+ phy_power_off(phy);
+
DRM_DEBUG_DP("DP off done\n");
return ret;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 97f076324242..83e7a49e022b 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -24,7 +24,6 @@
#include "dp_ctrl.h"
#include "dp_display.h"
#include "dp_drm.h"
-#include "dp_pll.h"
static struct msm_dp *g_dp_display;
#define HPD_STRING_SIZE 30
@@ -83,7 +82,6 @@ struct dp_display_private {
struct dp_usbpd *usbpd;
struct dp_parser *parser;
- struct msm_dp_pll *pll;
struct dp_power *power;
struct dp_catalog *catalog;
struct drm_dp_aux *aux;
@@ -585,7 +583,6 @@ static void dp_display_deinit_sub_modules(struct dp_display_private *dp)
dp_ctrl_put(dp->ctrl);
dp_panel_put(dp->panel);
dp_aux_put(dp->aux);
- dp_pll_put(dp->pll);
}
static int dp_init_sub_modules(struct dp_display_private *dp)
@@ -596,9 +593,6 @@ static int dp_init_sub_modules(struct dp_display_private *dp)
struct dp_panel_in panel_in = {
.dev = dev,
};
- struct dp_pll_in pll_in = {
- .pdev = dp->pdev,
- };
/* Callback APIs used for cable status change event */
cb->configure = dp_display_usbpd_configure_cb;
@@ -629,17 +623,6 @@ static int dp_init_sub_modules(struct dp_display_private *dp)
goto error;
}
- pll_in.parser = dp->parser;
- dp->pll = dp_pll_get(&pll_in);
- if (IS_ERR_OR_NULL(dp->pll)) {
- rc = -EINVAL;
- DRM_ERROR("failed to initialize pll, rc = %d\n", rc);
- dp->pll = NULL;
- goto error;
- }
-
- dp->parser->pll = dp->pll;
-
dp->power = dp_power_get(dp->parser);
if (IS_ERR(dp->power)) {
rc = PTR_ERR(dp->power);
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h
index 2f2d1279dfc6..11a02a2b9eb0 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -24,7 +24,4 @@ int dp_display_request_irq(struct msm_dp *dp_display);
bool dp_display_check_video_test(struct msm_dp *dp_display);
int dp_display_get_test_bpp(struct msm_dp *dp_display);
-void __init msm_dp_pll_driver_register(void);
-void __exit msm_dp_pll_driver_unregister(void);
-
#endif /* _DP_DISPLAY_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c
index 5110fc8ccfae..0c3b36135c30 100644
--- a/drivers/gpu/drm/msm/dp/dp_link.c
+++ b/drivers/gpu/drm/msm/dp/dp_link.c
@@ -5,6 +5,8 @@
#define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
+#include <drm/drm_print.h>
+
#include "dp_link.h"
#include "dp_panel.h"
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
index 7cdf37c525d8..4fc49005314d 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -7,6 +7,7 @@
#include <drm/drm_connector.h>
#include <drm/drm_edid.h>
+#include <drm/drm_print.h>
struct dp_panel_private {
struct device *dev;
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c
index 255a800535d5..0519dd3ac3c3 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -4,6 +4,9 @@
*/
#include <linux/of_gpio.h>
+#include <linux/phy/phy.h>
+
+#include <drm/drm_print.h>
#include "dp_parser.h"
#include "dp_reg.h"
@@ -53,8 +56,6 @@ static void dp_parser_unmap_io_resources(struct dp_parser *parser)
struct dp_io *io = &parser->io;
msm_dss_iounmap(&io->dp_controller);
- msm_dss_iounmap(&io->phy_reg);
- msm_dss_iounmap(&io->usb3_dp_com);
}
static int dp_parser_ctrl_res(struct dp_parser *parser)
@@ -69,6 +70,12 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
goto err;
}
+ io->phy = devm_phy_get(&pdev->dev, "dp");
+ if (IS_ERR(io->phy)) {
+ rc = PTR_ERR(io->phy);
+ goto err;
+ }
+
return 0;
err:
dp_parser_unmap_io_resources(parser);
@@ -90,7 +97,6 @@ static int dp_parser_misc(struct dp_parser *parser)
}
parser->max_dp_lanes = len;
-
return 0;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h
index 841e776124c4..34b49628bbaf 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.h
+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
@@ -7,10 +7,11 @@
#define _DP_PARSER_H_
#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-dp.h>
#include "dpu_io_util.h"
#include "msm_drv.h"
-#include "dp_pll.h"
#define DP_LABEL "MDSS DP DISPLAY"
#define DP_MAX_PIXEL_CLK_KHZ 675000
@@ -62,15 +63,11 @@ struct dp_display_data {
*
* @dp_controller: Display Port controller mapped memory address
* @phy_io: phy's mapped memory address
- * @ln_tx0_io: USB-DP lane TX0's mapped memory address
- * @ln_tx1_io: USB-DP lane TX1's mapped memory address
- * @dp_pll_io: DP PLL mapped memory address
- * @usb3_dp_com: USB3 DP PHY combo mapped memory address
*/
struct dp_io {
struct dss_io_data dp_controller;
- struct dss_io_data phy_reg;
- struct dss_io_data usb3_dp_com;
+ struct phy *phy;
+ union phy_configure_opts phy_opts;
};
/**
@@ -117,7 +114,6 @@ struct dp_parser {
struct dp_pinctrl pinctrl;
struct dp_io io;
struct dp_display_data disp_data;
- struct msm_dp_pll *pll;
const struct dp_regulator_cfg *regulator_cfg;
u32 max_dp_lanes;
diff --git a/drivers/gpu/drm/msm/dp/dp_pll.c b/drivers/gpu/drm/msm/dp/dp_pll.c
deleted file mode 100644
index 53f82cd97027..000000000000
--- a/drivers/gpu/drm/msm/dp/dp_pll.c
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
- */
-
-#include <linux/device.h>
-
-#include "dp_parser.h"
-#include "dp_pll.h"
-#include "dp_pll_private.h"
-
-static int dp_pll_get_phy_io(struct dp_parser *parser)
-{
- struct dp_io *io = &parser->io;
-
- io->usb3_dp_com.base = ioremap(REG_USB3_DP_COM_REGION_BASE,
- REG_USB3_DP_COM_REGION_SIZE);
- if (!io->usb3_dp_com.base) {
- DRM_ERROR("unable to map USB3 DP COM IO\n");
- return -EIO;
- }
-
- /* ToDo(user): DP PLL and DP PHY will not be part of
- * DP driver eventually so for now Hardcode Base and offsets
- * of PHY registers so we can remove them from dts and bindings
- */
- io->phy_reg.base = ioremap(REG_DP_PHY_REGION_BASE,
- REG_DP_PHY_REGION_SIZE);
- if (!io->phy_reg.base) {
- DRM_ERROR("DP PHY io region mapping failed\n");
- return -EIO;
- }
- io->phy_reg.len = REG_DP_PHY_REGION_SIZE;
-
- return 0;
-}
-
-static int msm_dp_pll_init(struct msm_dp_pll *pll,
- enum msm_dp_pll_type type, int id)
-{
- struct device *dev = &pll->pdev->dev;
- int ret = 0;
-
- switch (type) {
- case MSM_DP_PLL_10NM:
- ret = msm_dp_pll_10nm_init(pll, id);
- break;
- default:
- DRM_DEV_ERROR(dev, "%s: Wrong PLL type %d\n", __func__, type);
- return -ENXIO;
- }
-
- if (ret) {
- DRM_DEV_ERROR(dev, "%s: failed to init DP PLL\n", __func__);
- return ret;
- }
-
- pll->type = type;
-
- DRM_DEBUG_DP("DP:%d PLL registered", id);
-
- return ret;
-}
-
-struct msm_dp_pll *dp_pll_get(struct dp_pll_in *pll_in)
-{
- struct msm_dp_pll *dp_pll;
- struct dp_parser *parser = pll_in->parser;
- struct dp_io_pll *pll_io;
- int ret;
-
- dp_pll = devm_kzalloc(&pll_in->pdev->dev, sizeof(*dp_pll), GFP_KERNEL);
- if (!dp_pll)
- return ERR_PTR(-ENOMEM);
-
- pll_io = &dp_pll->pll_io;
- dp_pll->pdev = pll_in->pdev;
-
- dp_pll_get_phy_io(parser);
-
- pll_io->pll_base = parser->io.phy_reg.base + DP_PHY_PLL_OFFSET;
- pll_io->phy_base = parser->io.phy_reg.base + DP_PHY_REG_OFFSET;
- pll_io->ln_tx0_base = parser->io.phy_reg.base + DP_PHY_LN_TX0_OFFSET;
- pll_io->ln_tx1_base = parser->io.phy_reg.base + DP_PHY_LN_TX1_OFFSET;
-
- ret = msm_dp_pll_init(dp_pll, MSM_DP_PLL_10NM, 0);
- if (ret) {
- kfree(dp_pll);
- return ERR_PTR(ret);
- }
-
- return dp_pll;
-}
-
-void dp_pll_put(struct msm_dp_pll *dp_pll)
-{
- if (dp_pll->type == MSM_DP_PLL_10NM)
- msm_dp_pll_10nm_deinit(dp_pll);
-}
diff --git a/drivers/gpu/drm/msm/dp/dp_pll.h b/drivers/gpu/drm/msm/dp/dp_pll.h
deleted file mode 100644
index 5a10c8f3cfea..000000000000
--- a/drivers/gpu/drm/msm/dp/dp_pll.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DP_PLL_H
-#define __DP_PLL_H
-
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/platform_device.h>
-
-#include "dpu_io_util.h"
-#include "msm_drv.h"
-#include "dp_parser.h"
-
-#define PLL_REG_W(base, offset, data) \
- writel((data), (base) + (offset))
-#define PLL_REG_R(base, offset) readl((base) + (offset))
-
-enum msm_dp_pll_type {
- MSM_DP_PLL_10NM,
- MSM_DP_PLL_MAX
-};
-
-struct dp_pll_in {
- struct platform_device *pdev;
- struct dp_parser *parser;
-};
-
-struct dp_io_pll {
- void __iomem *pll_base;
- void __iomem *phy_base;
- void __iomem *ln_tx0_base;
- void __iomem *ln_tx1_base;
-};
-
-struct msm_dp_pll {
- enum msm_dp_pll_type type;
- bool pll_on;
-
- struct dp_io_pll pll_io;
-
- /* clock-provider: */
- struct clk_hw_onecell_data *hw_data;
-
- struct platform_device *pdev;
- void *priv;
-
- /* Pll specific resources like GPIO, power supply, clocks, etc*/
- struct dss_module_power mp;
- int (*get_provider)(struct msm_dp_pll *pll,
- struct clk **link_clk_provider,
- struct clk **pixel_clk_provider);
-};
-
-struct msm_dp_pll *dp_pll_get(struct dp_pll_in *pll_in);
-
-void dp_pll_put(struct msm_dp_pll *dp_pll);
-
-#endif /* __DP_PLL_H */
diff --git a/drivers/gpu/drm/msm/dp/dp_pll_10nm.c b/drivers/gpu/drm/msm/dp/dp_pll_10nm.c
deleted file mode 100644
index a2bf2fc24d6a..000000000000
--- a/drivers/gpu/drm/msm/dp/dp_pll_10nm.c
+++ /dev/null
@@ -1,930 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
- */
-
-/*
- * Display Port PLL driver block diagram for branch clocks
- *
- * +------------------------------+
- * | DP_VCO_CLK |
- * | |
- * | +-------------------+ |
- * | | (DP PLL/VCO) | |
- * | +---------+---------+ |
- * | v |
- * | +----------+-----------+ |
- * | | hsclk_divsel_clk_src | |
- * | +----------+-----------+ |
- * +------------------------------+
- * |
- * +---------<---------v------------>----------+
- * | |
- * +--------v---------+ |
- * | dp_phy_pll | |
- * | link_clk | |
- * +--------+---------+ |
- * | |
- * | |
- * v v
- * Input to DISPCC block |
- * for link clk, crypto clk |
- * and interface clock |
- * |
- * |
- * +--------<------------+-----------------+---<---+
- * | | |
- * +----v---------+ +--------v-----+ +--------v------+
- * | vco_divided | | vco_divided | | vco_divided |
- * | _clk_src | | _clk_src | | _clk_src |
- * | | | | | |
- * |divsel_six | | divsel_two | | divsel_four |
- * +-------+------+ +-----+--------+ +--------+------+
- * | | |
- * v---->----------v-------------<------v
- * |
- * +----------+---------+
- * | dp_phy_pll_vco |
- * | div_clk |
- * +---------+----------+
- * |
- * v
- * Input to DISPCC block
- * for DP pixel clock
- *
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/regmap.h>
-#include <linux/iopoll.h>
-
-#include "dp_hpd.h"
-#include "dp_pll.h"
-#include "dp_pll_private.h"
-
-#define NUM_PROVIDED_CLKS 2
-
-#define DP_LINK_CLK_SRC 0
-#define DP_PIXEL_CLK_SRC 1
-
-
-static int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate);
-
-static unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw,
- unsigned long parent_rate);
-
-static long dp_vco_round_rate_10nm(struct clk_hw *hw,
- unsigned long rate, unsigned long *parent_rate);
-
-static int dp_vco_prepare_10nm(struct clk_hw *hw);
-static void dp_vco_unprepare_10nm(struct clk_hw *hw);
-
-static struct dp_pll_db *dp_pdb;
-
-static const struct clk_ops dp_10nm_vco_clk_ops = {
- .recalc_rate = dp_vco_recalc_rate_10nm,
- .set_rate = dp_vco_set_rate_10nm,
- .round_rate = dp_vco_round_rate_10nm,
- .prepare = dp_vco_prepare_10nm,
- .unprepare = dp_vco_unprepare_10nm,
-};
-
-struct dp_pll_10nm_pclksel {
- struct clk_hw hw;
-
- /* divider params */
- u8 shift;
- u8 width;
- u8 flags; /* same flags as used by clk_divider struct */
-
- struct dp_pll_db *pll;
-};
-
-#define to_pll_10nm_pclksel(_hw) \
- container_of(_hw, struct dp_pll_10nm_pclksel, hw)
-
-static const struct clk_parent_data disp_cc_parent_data_0[] = {
- { .fw_name = "bi_tcxo" },
- { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
-};
-
-static struct dp_pll_vco_clk dp_vco_clk = {
- .min_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000,
- .max_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000,
-};
-
-static int dp_pll_mux_set_parent_10nm(struct clk_hw *hw, u8 val)
-{
- struct dp_pll_10nm_pclksel *pclksel = to_pll_10nm_pclksel(hw);
- struct dp_pll_db *dp_res = pclksel->pll;
- struct dp_io_pll *pll_io = &dp_res->base->pll_io;
- u32 auxclk_div;
-
- auxclk_div = PLL_REG_R(pll_io->phy_base, REG_DP_PHY_VCO_DIV);
- auxclk_div &= ~0x03;
-
- if (val == 0)
- auxclk_div |= 1;
- else if (val == 1)
- auxclk_div |= 2;
- else if (val == 2)
- auxclk_div |= 0;
-
- PLL_REG_W(pll_io->phy_base,
- REG_DP_PHY_VCO_DIV, auxclk_div);
- DRM_DEBUG_DP("%s: mux=%d auxclk_div=%x\n", __func__, val, auxclk_div);
-
- return 0;
-}
-
-static u8 dp_pll_mux_get_parent_10nm(struct clk_hw *hw)
-{
- u32 auxclk_div = 0;
- struct dp_pll_10nm_pclksel *pclksel = to_pll_10nm_pclksel(hw);
- struct dp_pll_db *dp_res = pclksel->pll;
- struct dp_io_pll *pll_io = &dp_res->base->pll_io;
- u8 val = 0;
-
- auxclk_div = PLL_REG_R(pll_io->phy_base, REG_DP_PHY_VCO_DIV);
- auxclk_div &= 0x03;
-
- if (auxclk_div == 1) /* Default divider */
- val = 0;
- else if (auxclk_div == 2)
- val = 1;
- else if (auxclk_div == 0)
- val = 2;
-
- DRM_DEBUG_DP("%s: auxclk_div=%d, val=%d\n", __func__, auxclk_div, val);
-
- return val;
-}
-
-static int dp_pll_clk_mux_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- unsigned long rate = 0;
-
- rate = clk_get_rate(hw->clk);
-
- if (rate <= 0) {
- DRM_ERROR("Rate is not set properly\n");
- return -EINVAL;
- }
-
- req->rate = rate;
-
- DRM_DEBUG_DP("%s: rate=%ld\n", __func__, req->rate);
- return 0;
-}
-
-static unsigned long dp_pll_mux_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct clk_hw *div_clk_hw = NULL, *vco_clk_hw = NULL;
- struct dp_pll_vco_clk *vco;
-
- div_clk_hw = clk_hw_get_parent(hw);
- if (!div_clk_hw)
- return 0;
-
- vco_clk_hw = clk_hw_get_parent(div_clk_hw);
- if (!vco_clk_hw)
- return 0;
-
- vco = to_dp_vco_hw(vco_clk_hw);
- if (!vco)
- return 0;
-
- if (vco->rate == DP_VCO_HSCLK_RATE_8100MHZDIV1000)
- return (vco->rate / 6);
- else if (vco->rate == DP_VCO_HSCLK_RATE_5400MHZDIV1000)
- return (vco->rate / 4);
- else
- return (vco->rate / 2);
-}
-
-static int dp_pll_10nm_get_provider(struct msm_dp_pll *pll,
- struct clk **link_clk_provider,
- struct clk **pixel_clk_provider)
-{
- struct clk_hw_onecell_data *hw_data = pll->hw_data;
-
- if (link_clk_provider)
- *link_clk_provider = hw_data->hws[DP_LINK_CLK_SRC]->clk;
- if (pixel_clk_provider)
- *pixel_clk_provider = hw_data->hws[DP_PIXEL_CLK_SRC]->clk;
-
- return 0;
-}
-
-static const struct clk_ops dp_10nm_pclksel_clk_ops = {
- .get_parent = dp_pll_mux_get_parent_10nm,
- .set_parent = dp_pll_mux_set_parent_10nm,
- .recalc_rate = dp_pll_mux_recalc_rate,
- .determine_rate = dp_pll_clk_mux_determine_rate,
-};
-
-static struct clk_hw *dp_pll_10nm_pixel_clk_sel(struct dp_pll_db *pll_10nm)
-{
- struct device *dev = &pll_10nm->pdev->dev;
- struct dp_pll_10nm_pclksel *pll_pclksel;
- struct clk_init_data pclksel_init = {
- .parent_data = disp_cc_parent_data_0,
- .num_parents = 3,
- .name = "dp_phy_pll_vco_div_clk",
- .ops = &dp_10nm_pclksel_clk_ops,
- };
- int ret;
-
- pll_pclksel = devm_kzalloc(dev, sizeof(*pll_pclksel), GFP_KERNEL);
- if (!pll_pclksel)
- return ERR_PTR(-ENOMEM);
-
- pll_pclksel->pll = pll_10nm;
- pll_pclksel->shift = 0;
- pll_pclksel->width = 4;
- pll_pclksel->hw.init = &pclksel_init;
-
- ret = clk_hw_register(dev, &pll_pclksel->hw);
- if (ret)
- return ERR_PTR(ret);
-
- return &pll_pclksel->hw;
-}
-
-static void dp_pll_10nm_unregister(struct dp_pll_db *pll_10nm)
-{
- int i = 0;
- struct clk_hw **hws;
-
- hws = pll_10nm->hws;
-
- for (i = 0; i < pll_10nm->num_hws; i++) {
- if (pll_10nm->fixed_factor_clk[i] == true)
- clk_hw_unregister_fixed_factor(hws[i]);
- else
- clk_hw_unregister(hws[i]);
- }
-}
-
-static int dp_pll_10nm_register(struct dp_pll_db *pll_10nm)
-{
- struct clk_hw_onecell_data *hw_data;
- int ret = 0;
- struct clk_hw *hw;
-
- struct msm_dp_pll *pll = pll_10nm->base;
- struct device *dev = &pll_10nm->pdev->dev;
- struct clk_hw **hws = pll_10nm->hws;
- int num = 0;
-
- struct clk_init_data vco_init = {
- .parent_data = &(const struct clk_parent_data){
- .fw_name = "bi_tcxo",
- },
- .num_parents = 1,
- .name = "dp_vco_clk",
- .ops = &dp_10nm_vco_clk_ops,
- };
-
- if (!dev) {
- DRM_ERROR("DP dev node not available\n");
- return 0;
- }
-
- DRM_DEBUG_DP("DP->id = %d", pll_10nm->id);
-
- hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
- NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
- GFP_KERNEL);
- if (!hw_data)
- return -ENOMEM;
-
- dp_vco_clk.hw.init = &vco_init;
- ret = clk_hw_register(dev, &dp_vco_clk.hw);
- if (ret)
- return ret;
- hws[num++] = &dp_vco_clk.hw;
-
- hw = clk_hw_register_fixed_factor(dev, "dp_phy_pll_link_clk",
- "dp_vco_clk", CLK_SET_RATE_PARENT, 1, 10);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
-
- pll_10nm->fixed_factor_clk[num] = true;
- hws[num++] = hw;
- hw_data->hws[DP_LINK_CLK_SRC] = hw;
-
- hw = clk_hw_register_fixed_factor(dev, "dp_vco_divsel_two_clk_src",
- "dp_vco_clk", 0, 1, 2);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
-
- pll_10nm->fixed_factor_clk[num] = true;
- hws[num++] = hw;
-
- hw = clk_hw_register_fixed_factor(dev, "dp_vco_divsel_four_clk_src",
- "dp_vco_clk", 0, 1, 4);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
-
- pll_10nm->fixed_factor_clk[num] = true;
- hws[num++] = hw;
-
- hw = clk_hw_register_fixed_factor(dev, "dp_vco_divsel_six_clk_src",
- "dp_vco_clk", 0, 1, 6);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
-
- pll_10nm->fixed_factor_clk[num] = true;
- hws[num++] = hw;
-
- hw = dp_pll_10nm_pixel_clk_sel(pll_10nm);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
-
- hws[num++] = hw;
- hw_data->hws[DP_PIXEL_CLK_SRC] = hw;
-
- pll_10nm->num_hws = num;
-
- hw_data->num = NUM_PROVIDED_CLKS;
- pll->hw_data = hw_data;
-
- ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
- pll->hw_data);
- if (ret) {
- DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n",
- ret);
- return ret;
- }
-
- return ret;
-}
-
-void msm_dp_pll_10nm_deinit(struct msm_dp_pll *pll)
-{
- dp_pll_10nm_unregister(pll->priv);
-}
-
-int msm_dp_pll_10nm_init(struct msm_dp_pll *pll, int id)
-{
- struct dp_pll_db *dp_10nm_pll;
- struct platform_device *pdev = pll->pdev;
- int ret;
-
- dp_10nm_pll = devm_kzalloc(&pdev->dev,
- sizeof(*dp_10nm_pll), GFP_KERNEL);
- if (!dp_10nm_pll)
- return -ENOMEM;
-
- DRM_DEBUG_DP("DP PLL%d", id);
-
- dp_10nm_pll->base = pll;
- dp_10nm_pll->pdev = pll->pdev;
- dp_10nm_pll->id = id;
- dp_pdb = dp_10nm_pll;
- pll->priv = (void *)dp_10nm_pll;
- dp_vco_clk.priv = pll;
- dp_10nm_pll->index = 0;
-
- ret = dp_pll_10nm_register(dp_10nm_pll);
- if (ret) {
- DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
- return ret;
- }
-
- pll->get_provider = dp_pll_10nm_get_provider;
-
- return ret;
-}
-
-static int dp_vco_pll_init_db_10nm(struct msm_dp_pll *pll,
- unsigned long rate)
-{
- u32 spare_value = 0;
- struct dp_io_pll *pll_io;
- struct dp_pll_db *dp_res = to_dp_pll_db(pll);
-
- pll_io = &pll->pll_io;
- spare_value = PLL_REG_R(pll_io->phy_base, REG_DP_PHY_SPARE0);
- dp_res->lane_cnt = spare_value & 0x0F;
- dp_res->orientation = (spare_value & 0xF0) >> 4;
-
- DRM_DEBUG_DP("%s: spare_value=0x%x, ln_cnt=0x%x, orientation=0x%x\n",
- __func__, spare_value, dp_res->lane_cnt,
- dp_res->orientation);
-
- switch (rate) {
- case DP_VCO_HSCLK_RATE_1620MHZDIV1000:
- DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__,
- DP_VCO_RATE_9720MHZDIV1000);
- dp_res->hsclk_sel = 0x0c;
- dp_res->dec_start_mode0 = 0x69;
- dp_res->div_frac_start1_mode0 = 0x00;
- dp_res->div_frac_start2_mode0 = 0x80;
- dp_res->div_frac_start3_mode0 = 0x07;
- dp_res->integloop_gain0_mode0 = 0x3f;
- dp_res->integloop_gain1_mode0 = 0x00;
- dp_res->vco_tune_map = 0x00;
- dp_res->lock_cmp1_mode0 = 0x6f;
- dp_res->lock_cmp2_mode0 = 0x08;
- dp_res->lock_cmp3_mode0 = 0x00;
- dp_res->phy_vco_div = 0x1;
- dp_res->lock_cmp_en = 0x00;
- break;
- case DP_VCO_HSCLK_RATE_2700MHZDIV1000:
- DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__,
- DP_VCO_RATE_10800MHZDIV1000);
- dp_res->hsclk_sel = 0x04;
- dp_res->dec_start_mode0 = 0x69;
- dp_res->div_frac_start1_mode0 = 0x00;
- dp_res->div_frac_start2_mode0 = 0x80;
- dp_res->div_frac_start3_mode0 = 0x07;
- dp_res->integloop_gain0_mode0 = 0x3f;
- dp_res->integloop_gain1_mode0 = 0x00;
- dp_res->vco_tune_map = 0x00;
- dp_res->lock_cmp1_mode0 = 0x0f;
- dp_res->lock_cmp2_mode0 = 0x0e;
- dp_res->lock_cmp3_mode0 = 0x00;
- dp_res->phy_vco_div = 0x1;
- dp_res->lock_cmp_en = 0x00;
- break;
- case DP_VCO_HSCLK_RATE_5400MHZDIV1000:
- DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__,
- DP_VCO_RATE_10800MHZDIV1000);
- dp_res->hsclk_sel = 0x00;
- dp_res->dec_start_mode0 = 0x8c;
- dp_res->div_frac_start1_mode0 = 0x00;
- dp_res->div_frac_start2_mode0 = 0x00;
- dp_res->div_frac_start3_mode0 = 0x0a;
- dp_res->integloop_gain0_mode0 = 0x3f;
- dp_res->integloop_gain1_mode0 = 0x00;
- dp_res->vco_tune_map = 0x00;
- dp_res->lock_cmp1_mode0 = 0x1f;
- dp_res->lock_cmp2_mode0 = 0x1c;
- dp_res->lock_cmp3_mode0 = 0x00;
- dp_res->phy_vco_div = 0x2;
- dp_res->lock_cmp_en = 0x00;
- break;
- case DP_VCO_HSCLK_RATE_8100MHZDIV1000:
- DRM_DEBUG_DP("%s: VCO rate: %ld\n", __func__,
- DP_VCO_RATE_8100MHZDIV1000);
- dp_res->hsclk_sel = 0x03;
- dp_res->dec_start_mode0 = 0x69;
- dp_res->div_frac_start1_mode0 = 0x00;
- dp_res->div_frac_start2_mode0 = 0x80;
- dp_res->div_frac_start3_mode0 = 0x07;
- dp_res->integloop_gain0_mode0 = 0x3f;
- dp_res->integloop_gain1_mode0 = 0x00;
- dp_res->vco_tune_map = 0x00;
- dp_res->lock_cmp1_mode0 = 0x2f;
- dp_res->lock_cmp2_mode0 = 0x2a;
- dp_res->lock_cmp3_mode0 = 0x00;
- dp_res->phy_vco_div = 0x0;
- dp_res->lock_cmp_en = 0x08;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static int dp_config_vco_rate_10nm(struct dp_pll_vco_clk *vco,
- unsigned long rate)
-{
- u32 res = 0;
- struct msm_dp_pll *pll = vco->priv;
- struct dp_io_pll *pll_io = &pll->pll_io;
- struct dp_pll_db *dp_res = to_dp_pll_db(pll);
-
- res = dp_vco_pll_init_db_10nm(pll, rate);
- if (res) {
- DRM_ERROR("VCO Init DB failed\n");
- return res;
- }
-
- if (dp_res->lane_cnt != 4) {
- if (dp_res->orientation == ORIENTATION_CC2)
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_PD_CTL, 0x6d);
- else
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_PD_CTL, 0x75);
- } else {
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_PD_CTL, 0x7d);
- }
-
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_SVS_MODE_CLK_SEL, 0x01);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_SYSCLK_EN_SEL, 0x37);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_SYS_CLK_CTRL, 0x02);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_CLK_ENABLE1, 0x0e);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_CLK_SEL, 0x30);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_CMN_CONFIG, 0x02);
-
- /* Different for each clock rates */
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_HSCLK_SEL, dp_res->hsclk_sel);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_DEC_START_MODE0, dp_res->dec_start_mode0);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_DIV_FRAC_START1_MODE0,
- dp_res->div_frac_start1_mode0);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_DIV_FRAC_START2_MODE0,
- dp_res->div_frac_start2_mode0);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_DIV_FRAC_START3_MODE0,
- dp_res->div_frac_start3_mode0);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_INTEGLOOP_GAIN0_MODE0,
- dp_res->integloop_gain0_mode0);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_INTEGLOOP_GAIN1_MODE0,
- dp_res->integloop_gain1_mode0);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_VCO_TUNE_MAP, dp_res->vco_tune_map);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_LOCK_CMP1_MODE0, dp_res->lock_cmp1_mode0);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_LOCK_CMP2_MODE0, dp_res->lock_cmp2_mode0);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_LOCK_CMP3_MODE0, dp_res->lock_cmp3_mode0);
-
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_BG_TIMER, 0x0a);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_CORECLK_DIV_MODE0, 0x0a);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_VCO_TUNE_CTRL, 0x00);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_CORE_CLK_EN, 0x1f);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_PLL_IVCO, 0x07);
- PLL_REG_W(pll_io->pll_base,
- QSERDES_COM_LOCK_CMP_EN, dp_res->lock_cmp_en);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_PLL_CCTRL_MODE0, 0x36);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_PLL_RCTRL_MODE0, 0x16);
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_CP_CTRL_MODE0, 0x06);
-
- if (dp_res->orientation == ORIENTATION_CC2)
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_MODE, 0x4c);
- else
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_MODE, 0x5c);
-
- /* TX Lane configuration */
- PLL_REG_W(pll_io->phy_base,
- REG_DP_PHY_TX0_TX1_LANE_CTL, 0x05);
- PLL_REG_W(pll_io->phy_base,
- REG_DP_PHY_TX2_TX3_LANE_CTL, 0x05);
-
- /* TX-0 register configuration */
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, 0x1a);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_VMODE_CTRL1, 0x40);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_PRE_STALL_LDO_BOOST_EN, 0x30);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_INTERFACE_SELECT, 0x3d);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_CLKBUF_ENABLE, 0x0f);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_RESET_TSYNC_EN, 0x03);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_TRAN_DRVR_EMP_EN, 0x03);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_TX_INTERFACE_MODE, 0x00);
- PLL_REG_W(pll_io->ln_tx0_base, REG_DP_PHY_TXn_TX_BAND, 0x4);
-
- /* TX-1 register configuration */
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, 0x1a);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_VMODE_CTRL1, 0x40);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_PRE_STALL_LDO_BOOST_EN, 0x30);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_INTERFACE_SELECT, 0x3d);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_CLKBUF_ENABLE, 0x0f);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_RESET_TSYNC_EN, 0x03);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_TRAN_DRVR_EMP_EN, 0x03);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_TX_INTERFACE_MODE, 0x00);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_TX_BAND, 0x4);
-
- /* dependent on the vco frequency */
- PLL_REG_W(pll_io->phy_base,
- REG_DP_PHY_VCO_DIV, dp_res->phy_vco_div);
-
- return res;
-}
-
-static bool dp_10nm_pll_lock_status(struct dp_pll_db *dp_res)
-{
- u32 status;
- bool pll_locked;
- struct dp_io_pll *pll_io = &dp_res->base->pll_io;
-
- /* poll for PLL lock status */
- if (readl_poll_timeout_atomic((pll_io->pll_base +
- QSERDES_COM_C_READY_STATUS),
- status,
- ((status & BIT(0)) > 0),
- DP_PHY_PLL_POLL_SLEEP_US,
- DP_PHY_PLL_POLL_TIMEOUT_US)) {
- DRM_ERROR("%s: C_READY status is not high. Status=%x\n",
- __func__, status);
- pll_locked = false;
- } else {
- pll_locked = true;
- }
-
- return pll_locked;
-}
-
-static bool dp_10nm_phy_rdy_status(struct dp_pll_db *dp_res)
-{
- u32 status;
- bool phy_ready = true;
- struct dp_io_pll *pll_io = &dp_res->base->pll_io;
-
- /* poll for PHY ready status */
- if (readl_poll_timeout_atomic((pll_io->phy_base +
- REG_DP_PHY_STATUS),
- status,
- ((status & (BIT(1))) > 0),
- DP_PHY_PLL_POLL_SLEEP_US,
- DP_PHY_PLL_POLL_TIMEOUT_US)) {
- DRM_ERROR("%s: Phy_ready is not high. Status=%x\n",
- __func__, status);
- phy_ready = false;
- }
-
- return phy_ready;
-}
-
-static int dp_pll_enable_10nm(struct clk_hw *hw)
-{
- int rc = 0;
- u32 bias_en, drvr_en;
- struct dp_io_pll *pll_io;
- struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);
- struct msm_dp_pll *pll = to_msm_dp_pll(vco);
- struct dp_pll_db *dp_res = to_dp_pll_db(pll);
-
- pll_io = &pll->pll_io;
-
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_AUX_CFG2, 0x04);
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x01);
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x05);
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x01);
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x09);
-
- PLL_REG_W(pll_io->pll_base, QSERDES_COM_RESETSM_CNTRL, 0x20);
-
- if (!dp_10nm_pll_lock_status(dp_res)) {
- rc = -EINVAL;
- goto lock_err;
- }
-
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x19);
- /* poll for PHY ready status */
- if (!dp_10nm_phy_rdy_status(dp_res)) {
- rc = -EINVAL;
- goto lock_err;
- }
-
- DRM_DEBUG_DP("%s: PLL is locked\n", __func__);
-
- if (dp_res->lane_cnt == 1) {
- bias_en = 0x3e;
- drvr_en = 0x13;
- } else {
- bias_en = 0x3f;
- drvr_en = 0x10;
- }
-
- if (dp_res->lane_cnt != 4) {
- if (dp_res->orientation == ORIENTATION_CC1) {
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en);
- } else {
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en);
- }
- } else {
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_HIGHZ_DRVR_EN, drvr_en);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN, bias_en);
- }
-
- PLL_REG_W(pll_io->ln_tx0_base, REG_DP_PHY_TXn_TX_POL_INV, 0x0a);
- PLL_REG_W(pll_io->ln_tx1_base, REG_DP_PHY_TXn_TX_POL_INV, 0x0a);
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x18);
- udelay(2000);
-
- PLL_REG_W(pll_io->phy_base, REG_DP_PHY_CFG, 0x19);
-
- /* poll for PHY ready status */
- if (!dp_10nm_phy_rdy_status(dp_res)) {
- rc = -EINVAL;
- goto lock_err;
- }
-
- PLL_REG_W(pll_io->ln_tx0_base, REG_DP_PHY_TXn_TX_DRV_LVL, 0x38);
- PLL_REG_W(pll_io->ln_tx1_base, REG_DP_PHY_TXn_TX_DRV_LVL, 0x38);
- PLL_REG_W(pll_io->ln_tx0_base, REG_DP_PHY_TXn_TX_EMP_POST1_LVL, 0x20);
- PLL_REG_W(pll_io->ln_tx1_base, REG_DP_PHY_TXn_TX_EMP_POST1_LVL, 0x20);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_TX, 0x06);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_TX, 0x06);
- PLL_REG_W(pll_io->ln_tx0_base,
- REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_RX, 0x07);
- PLL_REG_W(pll_io->ln_tx1_base,
- REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_RX, 0x07);
-
-lock_err:
- return rc;
-}
-
-static int dp_pll_disable_10nm(struct clk_hw *hw)
-{
- int rc = 0;
- struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);
- struct msm_dp_pll *pll = to_msm_dp_pll(vco);
-
- /* Assert DP PHY power down */
- PLL_REG_W(pll->pll_io.phy_base, REG_DP_PHY_PD_CTL, 0x2);
-
- return rc;
-}
-
-
-static int dp_vco_prepare_10nm(struct clk_hw *hw)
-{
- int rc = 0;
- struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);
- struct msm_dp_pll *pll = (struct msm_dp_pll *)vco->priv;
- struct dp_pll_db *dp_res = to_dp_pll_db(pll);
-
- DRM_DEBUG_DP("%s: rate = %ld\n", __func__, vco->rate);
- if ((dp_res->vco_cached_rate != 0)
- && (dp_res->vco_cached_rate == vco->rate)) {
- rc = dp_vco_set_rate_10nm(hw,
- dp_res->vco_cached_rate, dp_res->vco_cached_rate);
- if (rc) {
- DRM_ERROR("index=%d vco_set_rate failed. rc=%d\n",
- rc, dp_res->index);
- goto error;
- }
- }
-
- rc = dp_pll_enable_10nm(hw);
- if (rc) {
- DRM_ERROR("ndx=%d failed to enable dp pll\n",
- dp_res->index);
- goto error;
- }
-
- pll->pll_on = true;
-error:
- return rc;
-}
-
-static void dp_vco_unprepare_10nm(struct clk_hw *hw)
-{
- struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);
- struct msm_dp_pll *pll = to_msm_dp_pll(vco);
- struct dp_pll_db *dp_res = to_dp_pll_db(pll);
-
- if (!dp_res) {
- DRM_ERROR("Invalid input parameter\n");
- return;
- }
-
- if (!pll->pll_on) {
- DRM_ERROR("pll resource can't be enabled\n");
- return;
- }
- dp_res->vco_cached_rate = vco->rate;
- dp_pll_disable_10nm(hw);
-
- pll->pll_on = false;
-}
-
-static int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);
- int rc;
-
- DRM_DEBUG_DP("DP lane CLK rate=%ld\n", rate);
-
- rc = dp_config_vco_rate_10nm(vco, rate);
- if (rc)
- DRM_ERROR("%s: Failed to set clk rate\n", __func__);
-
- vco->rate = rate;
-
- return 0;
-}
-
-static unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- u32 div, hsclk_div, link_clk_div = 0;
- u64 vco_rate;
- struct dp_io_pll *pll_io;
- struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);
- struct msm_dp_pll *pll = to_msm_dp_pll(vco);
- struct dp_pll_db *dp_res = to_dp_pll_db(pll);
-
- pll_io = &pll->pll_io;
-
- div = PLL_REG_R(pll_io->pll_base, QSERDES_COM_HSCLK_SEL);
- div &= 0x0f;
-
- if (div == 12)
- hsclk_div = 6; /* Default */
- else if (div == 4)
- hsclk_div = 4;
- else if (div == 0)
- hsclk_div = 2;
- else if (div == 3)
- hsclk_div = 1;
- else {
- DRM_DEBUG_DP("unknown divider. forcing to default\n");
- hsclk_div = 5;
- }
-
- div = PLL_REG_R(pll_io->phy_base, REG_DP_PHY_AUX_CFG2);
- div >>= 2;
-
- if ((div & 0x3) == 0)
- link_clk_div = 5;
- else if ((div & 0x3) == 1)
- link_clk_div = 10;
- else if ((div & 0x3) == 2)
- link_clk_div = 20;
- else
- DRM_ERROR("%s: unsupported div. Phy_mode: %d\n", __func__, div);
-
- if (link_clk_div == 20) {
- vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;
- } else {
- if (hsclk_div == 6)
- vco_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000;
- else if (hsclk_div == 4)
- vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;
- else if (hsclk_div == 2)
- vco_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000;
- else
- vco_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000;
- }
-
- DRM_DEBUG_DP("returning vco rate = %lu\n", (unsigned long)vco_rate);
-
- dp_res->vco_cached_rate = vco->rate = vco_rate;
- return (unsigned long)vco_rate;
-}
-
-long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
-{
- unsigned long rrate = rate;
- struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);
-
- if (rate <= vco->min_rate)
- rrate = vco->min_rate;
- else if (rate <= DP_VCO_HSCLK_RATE_2700MHZDIV1000)
- rrate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;
- else if (rate <= DP_VCO_HSCLK_RATE_5400MHZDIV1000)
- rrate = DP_VCO_HSCLK_RATE_5400MHZDIV1000;
- else
- rrate = vco->max_rate;
-
- DRM_DEBUG_DP("%s: rrate=%ld\n", __func__, rrate);
-
- *parent_rate = rrate;
- return rrate;
-}
diff --git a/drivers/gpu/drm/msm/dp/dp_pll_private.h b/drivers/gpu/drm/msm/dp/dp_pll_private.h
deleted file mode 100644
index 434abdc396f5..000000000000
--- a/drivers/gpu/drm/msm/dp/dp_pll_private.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DP_PLL_10NM_H
-#define __DP_PLL_10NM_H
-
-#include "dp_pll.h"
-#include "dp_reg.h"
-
-#define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL
-#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL
-#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL
-#define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL
-
-#define NUM_DP_CLOCKS_MAX 6
-
-#define DP_PHY_PLL_POLL_SLEEP_US 500
-#define DP_PHY_PLL_POLL_TIMEOUT_US 10000
-
-#define DP_VCO_RATE_8100MHZDIV1000 8100000UL
-#define DP_VCO_RATE_9720MHZDIV1000 9720000UL
-#define DP_VCO_RATE_10800MHZDIV1000 10800000UL
-
-struct dp_pll_vco_clk {
- struct clk_hw hw;
- unsigned long rate; /* current vco rate */
- u64 min_rate; /* min vco rate */
- u64 max_rate; /* max vco rate */
- void *priv;
-};
-
-struct dp_pll_db {
- struct msm_dp_pll *base;
-
- int id;
- struct platform_device *pdev;
-
- /* private clocks: */
- bool fixed_factor_clk[NUM_DP_CLOCKS_MAX];
- struct clk_hw *hws[NUM_DP_CLOCKS_MAX];
- u32 num_hws;
-
- /* lane and orientation settings */
- u8 lane_cnt;
- u8 orientation;
-
- /* COM PHY settings */
- u32 hsclk_sel;
- u32 dec_start_mode0;
- u32 div_frac_start1_mode0;
- u32 div_frac_start2_mode0;
- u32 div_frac_start3_mode0;
- u32 integloop_gain0_mode0;
- u32 integloop_gain1_mode0;
- u32 vco_tune_map;
- u32 lock_cmp1_mode0;
- u32 lock_cmp2_mode0;
- u32 lock_cmp3_mode0;
- u32 lock_cmp_en;
-
- /* PHY vco divider */
- u32 phy_vco_div;
- /*
- * Certain pll's needs to update the same vco rate after resume in
- * suspend/resume scenario. Cached the vco rate for such plls.
- */
- unsigned long vco_cached_rate;
- u32 cached_cfg0;
- u32 cached_cfg1;
- u32 cached_outdiv;
-
- uint32_t index;
-};
-
-static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw *hw)
-{
- return container_of(hw, struct dp_pll_vco_clk, hw);
-}
-
-#define to_msm_dp_pll(vco) ((struct msm_dp_pll *)vco->priv)
-
-#define to_dp_pll_db(x) ((struct dp_pll_db *)x->priv)
-
-int msm_dp_pll_10nm_init(struct msm_dp_pll *dp_pll, int id);
-void msm_dp_pll_10nm_deinit(struct msm_dp_pll *dp_pll);
-
-#endif /* __DP_PLL_10NM_H */
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c
index 34fdb2e5d644..17c1fc6a2d44 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -9,6 +9,7 @@
#include <linux/clk-provider.h>
#include <linux/regulator/consumer.h>
#include "dp_power.h"
+#include "msm_drv.h"
struct dp_power_private {
struct dp_parser *parser;
@@ -102,16 +103,6 @@ static int dp_power_clk_init(struct dp_power_private *power)
ctrl = &power->parser->mp[DP_CTRL_PM];
stream = &power->parser->mp[DP_STREAM_PM];
- if (power->parser->pll && power->parser->pll->get_provider) {
- rc = power->parser->pll->get_provider(power->parser->pll,
- &power->link_provider, &power->pixel_provider);
- if (rc) {
- DRM_ERROR("%s:provider failed,don't set parent\n",
- __func__);
- return 0;
- }
- }
-
rc = msm_dss_get_clk(dev, core->clk_config, core->num_clk);
if (rc) {
DRM_ERROR("failed to get %s clk. err=%d\n",
@@ -312,34 +303,6 @@ void dp_power_client_deinit(struct dp_power *dp_power)
}
-int dp_power_set_link_clk_parent(struct dp_power *dp_power)
-{
- int rc = 0;
- struct dp_power_private *power;
- u32 num;
- struct dss_clk *cfg;
- char *name = "ctrl_link";
-
- if (!dp_power) {
- DRM_ERROR("invalid power data\n");
- rc = -EINVAL;
- goto exit;
- }
-
- power = container_of(dp_power, struct dp_power_private, dp_power);
-
- num = power->parser->mp[DP_CTRL_PM].num_clk;
- cfg = power->parser->mp[DP_CTRL_PM].clk_config;
-
- while (num && strcmp(cfg->clk_name, name)) {
- num--;
- cfg++;
- }
-
-exit:
- return rc;
-}
-
int dp_power_init(struct dp_power *dp_power, bool flip)
{
int rc = 0;
diff --git a/drivers/gpu/drm/msm/dp/dp_power.h b/drivers/gpu/drm/msm/dp/dp_power.h
index 5333a97d5c35..76743d755833 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.h
+++ b/drivers/gpu/drm/msm/dp/dp_power.h
@@ -69,15 +69,6 @@ int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type);
int dp_power_clk_enable(struct dp_power *power, enum dp_pm_type pm_type,
bool enable);
-/**
- * dp_power_set_link_clk_parent() - configures parent of link clocks
- *
- * @power: instance of power module
- * return: 0 for success, error for failures
- *
- * This API will set the link clock parent source
- */
-int dp_power_set_link_clk_parent(struct dp_power *power);
/**
* dp_power_client_init() - initialize clock and regulator modules
--
Sent by a computer, using git, on the internet
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v1 2/9] phy: qcom-qmp: Move phy mode into struct qmp_phy
2020-08-26 2:47 ` [PATCH v1 2/9] phy: qcom-qmp: Move phy mode into struct qmp_phy Stephen Boyd
@ 2020-08-26 3:37 ` Bjorn Andersson
0 siblings, 0 replies; 21+ messages in thread
From: Bjorn Andersson @ 2020-08-26 3:37 UTC (permalink / raw)
To: Stephen Boyd
Cc: Kishon Vijay Abraham I, Vinod Koul, linux-kernel, linux-arm-msm,
Jeykumar Sankaran, Chandan Uddaraju, Vara Reddy, Tanmay Shah,
Manu Gautam, Sandeep Maheswaram, Douglas Anderson, Sean Paul,
Jonathan Marek, Dmitry Baryshkov, Rob Clark
On Tue 25 Aug 21:47 CDT 2020, Stephen Boyd wrote:
> The phy mode pertains to the phy itself, i.e. 'struct qmp_phy', not the
> wrapper, i.e. 'struct qcom_qmp'. Move the phy mode into the phy
> structure to more accurately reflect what is going on. This also cleans
> up 'struct qcom_qmp' so that it can eventually be the place where qmp
> wrapper wide data is located, paving the way for the USB3+DP combo phy.
>
> Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
> Cc: Chandan Uddaraju <chandanu@codeaurora.org>
> Cc: Vara Reddy <varar@codeaurora.org>
> Cc: Tanmay Shah <tanmay@codeaurora.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Cc: Manu Gautam <mgautam@codeaurora.org>
> Cc: Sandeep Maheswaram <sanm@codeaurora.org>
> Cc: Douglas Anderson <dianders@chromium.org>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Jonathan Marek <jonathan@marek.ca>
> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Cc: Rob Clark <robdclark@chromium.org>
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 15 +++++++--------
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 562053ce9455..7ee9e966dc6d 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -1812,6 +1812,7 @@ struct qmp_phy_cfg {
> * @index: lane index
> * @qmp: QMP phy to which this lane belongs
> * @lane_rst: lane's reset controller
> + * @mode: current PHY mode
> */
> struct qmp_phy {
> struct phy *phy;
> @@ -1825,6 +1826,7 @@ struct qmp_phy {
> unsigned int index;
> struct qcom_qmp *qmp;
> struct reset_control *lane_rst;
> + enum phy_mode mode;
> };
>
> /**
> @@ -1843,7 +1845,6 @@ struct qmp_phy {
> * @phy_mutex: mutex lock for PHY common block initialization
> * @init_count: phy common block initialization count
> * @phy_initialized: indicate if PHY has been initialized
> - * @mode: current PHY mode
> * @ufs_reset: optional UFS PHY reset handle
> */
> struct qcom_qmp {
> @@ -1861,7 +1862,6 @@ struct qcom_qmp {
> struct mutex phy_mutex;
> int init_count;
> bool phy_initialized;
> - enum phy_mode mode;
>
> struct reset_control *ufs_reset;
> };
> @@ -2801,9 +2801,8 @@ static int qcom_qmp_phy_set_mode(struct phy *phy,
> enum phy_mode mode, int submode)
> {
> struct qmp_phy *qphy = phy_get_drvdata(phy);
> - struct qcom_qmp *qmp = qphy->qmp;
>
> - qmp->mode = mode;
> + qphy->mode = mode;
>
> return 0;
> }
> @@ -2816,8 +2815,8 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
> void __iomem *pcs_misc = qphy->pcs_misc;
> u32 intr_mask;
>
> - if (qmp->mode == PHY_MODE_USB_HOST_SS ||
> - qmp->mode == PHY_MODE_USB_DEVICE_SS)
> + if (qphy->mode == PHY_MODE_USB_HOST_SS ||
> + qphy->mode == PHY_MODE_USB_DEVICE_SS)
> intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
> else
> intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
> @@ -2863,7 +2862,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
> struct qmp_phy *qphy = qmp->phys[0];
> const struct qmp_phy_cfg *cfg = qmp->cfg;
>
> - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
> + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
>
> /* Supported only for USB3 PHY */
> if (cfg->type != PHY_TYPE_USB3)
> @@ -2889,7 +2888,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
> const struct qmp_phy_cfg *cfg = qmp->cfg;
> int ret = 0;
>
> - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
> + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
>
> /* Supported only for USB3 PHY */
> if (cfg->type != PHY_TYPE_USB3)
> --
> Sent by a computer, using git, on the internet
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 3/9] phy: qcom-qmp: Remove 'initialized' in favor of 'init_count'
2020-08-26 2:47 ` [PATCH v1 3/9] phy: qcom-qmp: Remove 'initialized' in favor of 'init_count' Stephen Boyd
@ 2020-08-26 3:44 ` Bjorn Andersson
0 siblings, 0 replies; 21+ messages in thread
From: Bjorn Andersson @ 2020-08-26 3:44 UTC (permalink / raw)
To: Stephen Boyd
Cc: Kishon Vijay Abraham I, Vinod Koul, linux-kernel, linux-arm-msm,
Jeykumar Sankaran, Chandan Uddaraju, Vara Reddy, Tanmay Shah,
Manu Gautam, Sandeep Maheswaram, Douglas Anderson, Sean Paul,
Jonathan Marek, Dmitry Baryshkov, Rob Clark
On Tue 25 Aug 21:47 CDT 2020, Stephen Boyd wrote:
> We already track if any phy inside the qmp wrapper has been initialized
> by means of the struct qcom_qmp::init_count member. Let's drop the
> duplicate 'initialized' member to simplify the code a bit.
>
> Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
> Cc: Chandan Uddaraju <chandanu@codeaurora.org>
> Cc: Vara Reddy <varar@codeaurora.org>
> Cc: Tanmay Shah <tanmay@codeaurora.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Cc: Manu Gautam <mgautam@codeaurora.org>
> Cc: Sandeep Maheswaram <sanm@codeaurora.org>
> Cc: Douglas Anderson <dianders@chromium.org>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Jonathan Marek <jonathan@marek.ca>
> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Cc: Rob Clark <robdclark@chromium.org>
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 7ee9e966dc6d..4a23ba9361b3 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -1844,7 +1844,6 @@ struct qmp_phy {
> * @phys: array of per-lane phy descriptors
> * @phy_mutex: mutex lock for PHY common block initialization
> * @init_count: phy common block initialization count
> - * @phy_initialized: indicate if PHY has been initialized
> * @ufs_reset: optional UFS PHY reset handle
> */
> struct qcom_qmp {
> @@ -1861,7 +1860,6 @@ struct qcom_qmp {
>
> struct mutex phy_mutex;
> int init_count;
> - bool phy_initialized;
>
> struct reset_control *ufs_reset;
> };
> @@ -2748,7 +2746,6 @@ static int qcom_qmp_phy_enable(struct phy *phy)
> dev_err(qmp->dev, "phy initialization timed-out\n");
> goto err_pcs_ready;
> }
> - qmp->phy_initialized = true;
> return 0;
>
> err_pcs_ready:
> @@ -2792,8 +2789,6 @@ static int qcom_qmp_phy_disable(struct phy *phy)
>
> qcom_qmp_phy_com_exit(qmp);
>
> - qmp->phy_initialized = false;
> -
> return 0;
> }
>
> @@ -2868,7 +2863,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
> if (cfg->type != PHY_TYPE_USB3)
> return 0;
>
> - if (!qmp->phy_initialized) {
> + if (!qmp->init_count) {
> dev_vdbg(dev, "PHY not initialized, bailing out\n");
> return 0;
> }
> @@ -2894,7 +2889,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
> if (cfg->type != PHY_TYPE_USB3)
> return 0;
>
> - if (!qmp->phy_initialized) {
> + if (!qmp->init_count) {
> dev_vdbg(dev, "PHY not initialized, bailing out\n");
> return 0;
> }
> --
> Sent by a computer, using git, on the internet
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 5/9] phy: qcom-qmp: Get dp_com I/O resource by index
2020-08-26 2:47 ` [PATCH v1 5/9] phy: qcom-qmp: Get dp_com I/O resource by index Stephen Boyd
@ 2020-08-26 4:36 ` Bjorn Andersson
2020-08-26 21:32 ` Stephen Boyd
0 siblings, 1 reply; 21+ messages in thread
From: Bjorn Andersson @ 2020-08-26 4:36 UTC (permalink / raw)
To: Stephen Boyd
Cc: Kishon Vijay Abraham I, Vinod Koul, linux-kernel, linux-arm-msm,
Jeykumar Sankaran, Chandan Uddaraju, Vara Reddy, Tanmay Shah,
Manu Gautam, Sandeep Maheswaram, Douglas Anderson, Sean Paul,
Jonathan Marek, Dmitry Baryshkov, Rob Clark
On Tue 25 Aug 21:47 CDT 2020, Stephen Boyd wrote:
> The dp_com resource is always at index 1 according to the dts files in
> the kernel. Get this resource by index so that we don't need to make
> future additions to the DT binding use 'reg-names'.
>
Afaict the DT binding for the USB/DP phy defines that there should be a
reg name of "dp_com" and the current dts files all specifies this. Am I
missing something?
PS. Why isn't this a devm_platform_ioremap_resource{,_byname}()?
Regards,
Bjorn
> Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
> Cc: Chandan Uddaraju <chandanu@codeaurora.org>
> Cc: Vara Reddy <varar@codeaurora.org>
> Cc: Tanmay Shah <tanmay@codeaurora.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Manu Gautam <mgautam@codeaurora.org>
> Cc: Sandeep Maheswaram <sanm@codeaurora.org>
> Cc: Douglas Anderson <dianders@chromium.org>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Jonathan Marek <jonathan@marek.ca>
> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Cc: Rob Clark <robdclark@chromium.org>
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 40c051813c34..76d7a9e80f04 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -3266,8 +3266,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
>
> /* per PHY dp_com; if PHY has dp_com control block */
> if (cfg->has_phy_dp_com_ctrl) {
> - res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> - "dp_com");
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> base = devm_ioremap_resource(dev, res);
> if (IS_ERR(base))
> return PTR_ERR(base);
> --
> Sent by a computer, using git, on the internet
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 5/9] phy: qcom-qmp: Get dp_com I/O resource by index
2020-08-26 4:36 ` Bjorn Andersson
@ 2020-08-26 21:32 ` Stephen Boyd
2020-08-27 1:59 ` Bjorn Andersson
0 siblings, 1 reply; 21+ messages in thread
From: Stephen Boyd @ 2020-08-26 21:32 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Kishon Vijay Abraham I, Vinod Koul, linux-kernel, linux-arm-msm,
Jeykumar Sankaran, Chandan Uddaraju, Vara Reddy, Tanmay Shah,
Manu Gautam, Sandeep Maheswaram, Douglas Anderson, Sean Paul,
Jonathan Marek, Dmitry Baryshkov, Rob Clark
Quoting Bjorn Andersson (2020-08-25 21:36:16)
> On Tue 25 Aug 21:47 CDT 2020, Stephen Boyd wrote:
>
> > The dp_com resource is always at index 1 according to the dts files in
> > the kernel. Get this resource by index so that we don't need to make
> > future additions to the DT binding use 'reg-names'.
> >
>
> Afaict the DT binding for the USB/DP phy defines that there should be a
> reg name of "dp_com" and the current dts files all specifies this. Am I
> missing something?
Yes the binding enforces this but this patch is removing that
enforcement and instead mandating that dp_com is always at index 1 (i.e.
the second one) so that we can add the DP serdes region directly after
and avoid adding yet another reg-names property. I changed the binding
for this usb3-dp phy compatible to make reg-names optional as well. I
don't see any gain from using reg-names.
>
> PS. Why isn't this a devm_platform_ioremap_resource{,_byname}()?
Sure. I'll roll that into this patch.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 5/9] phy: qcom-qmp: Get dp_com I/O resource by index
2020-08-26 21:32 ` Stephen Boyd
@ 2020-08-27 1:59 ` Bjorn Andersson
0 siblings, 0 replies; 21+ messages in thread
From: Bjorn Andersson @ 2020-08-27 1:59 UTC (permalink / raw)
To: Stephen Boyd
Cc: Kishon Vijay Abraham I, Vinod Koul, linux-kernel, linux-arm-msm,
Jeykumar Sankaran, Chandan Uddaraju, Vara Reddy, Tanmay Shah,
Manu Gautam, Sandeep Maheswaram, Douglas Anderson, Sean Paul,
Jonathan Marek, Dmitry Baryshkov, Rob Clark
On Wed 26 Aug 16:32 CDT 2020, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2020-08-25 21:36:16)
> > On Tue 25 Aug 21:47 CDT 2020, Stephen Boyd wrote:
> >
> > > The dp_com resource is always at index 1 according to the dts files in
> > > the kernel. Get this resource by index so that we don't need to make
> > > future additions to the DT binding use 'reg-names'.
> > >
> >
> > Afaict the DT binding for the USB/DP phy defines that there should be a
> > reg name of "dp_com" and the current dts files all specifies this. Am I
> > missing something?
>
> Yes the binding enforces this but this patch is removing that
> enforcement and instead mandating that dp_com is always at index 1 (i.e.
> the second one) so that we can add the DP serdes region directly after
> and avoid adding yet another reg-names property. I changed the binding
> for this usb3-dp phy compatible to make reg-names optional as well. I
> don't see any gain from using reg-names.
>
Thanks for the explanation, I don't have any objections to this.
> >
> > PS. Why isn't this a devm_platform_ioremap_resource{,_byname}()?
>
> Sure. I'll roll that into this patch.
Thanks,
Bjorn
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy
2020-08-26 2:47 ` [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy Stephen Boyd
@ 2020-09-01 13:36 ` Dmitry Baryshkov
2020-09-02 1:01 ` Stephen Boyd
0 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2020-09-01 13:36 UTC (permalink / raw)
To: Stephen Boyd, Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Stephen Boyd,
Jonathan Marek, Rob Clark
On 26/08/2020 05:47, Stephen Boyd wrote:
> Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy
> driver. We already have support for the USB3 part of the combo phy, so
> most additions are for the DP phy.
>
> Split up the qcom_qmp_phy{enable,disable}() functions into the phy init,
> power on, power off, and exit functions that the common phy framework
> expects so that the DP phy can add even more phy ops like
> phy_calibrate() and phy_configure(). This allows us to initialize the DP
> PHY and configure the AUX channel before powering on the PHY at the link
> rate that was negotiated during link training.
>
> The general design is as follows:
>
> 1) DP controller calls phy_init() to initialize the PHY and configure
> the dp_com register region.
>
> 2) DP controller calls phy_configure() to tune the link rate and
> voltage swing and pre-emphasis settings.
>
> 3) DP controller calls phy_power_on() to enable the PLL and power on
> the phy.
>
> 4) DP controller calls phy_configure() again to tune the voltage swing
> and pre-emphasis settings determind during link training.
>
> 5) DP controller calls phy_calibrate() some number of times to change
> the aux settings if the aux channel times out during link training.
>
> 6) DP controller calls phy_power_off() if the link rate is to be
> changed and goes back to step 2 to try again at a different link rate.
>
> 5) DP controller calls phy_power_off() and then phy_exit() to power
> down the PHY when it is done.
>
> The DP PHY contains a PLL that is different from the one used for the
> USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk
> output from the DP PLL after going through various dividers. Introduce
> clk ops for these two clks that just tell the child clks what the
> frequency of the pixel and link are. When the phy link rate is
> configured we call clk_set_rate() to update the child clks in the
> display clk controller on what rate is in use. The clk frequencies
> always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or
> 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or
> HBR3) so we simply store the link rate and use that to calculate the clk
> frequencies.
>
> The PLL enable sequence is a little different from other QMP phy PLLs so
> we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called
> from phy_power_on(). This should probably be split out better so that
> each phy has a way to run the final PLL/PHY enable sequence.
>
> This code is based on a submission of this phy and PLL in the drm
> subsystem.
>
> Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
> Cc: Chandan Uddaraju <chandanu@codeaurora.org>
> Cc: Vara Reddy <varar@codeaurora.org>
> Cc: Tanmay Shah <tanmay@codeaurora.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Manu Gautam <mgautam@codeaurora.org>
> Cc: Sandeep Maheswaram <sanm@codeaurora.org>
> Cc: Douglas Anderson <dianders@chromium.org>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Jonathan Marek <jonathan@marek.ca>
> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Cc: Rob Clark <robdclark@chromium.org>
> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 935 +++++++++++++++++++++++++---
> drivers/phy/qualcomm/phy-qcom-qmp.h | 80 +++
> 2 files changed, 926 insertions(+), 89 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index 76d7a9e80f04..dd77c7dfa310 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -947,6 +947,130 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> };
>
I'd suggest to split common part of the following tables into
dpphy_cfg->serdes_tbl and add the rest as "addon tables"
(serdes_tbl_rbr, serdes_rbl_hbr/2/3) into the same dpphy_cfg.
It would ease V4 QMP DP PHY support.
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
> +};
> +
> static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
> @@ -1798,6 +1922,11 @@ struct qmp_phy_cfg {
> bool no_pcs_sw_reset;
> };
>
> +struct qmp_phy_combo_cfg {
> + const struct qmp_phy_cfg *usb_cfg;
> + const struct qmp_phy_cfg *dp_cfg;
> +};
> +
> /**
> * struct qmp_phy - per-lane phy descriptor
> *
> @@ -1831,6 +1960,15 @@ struct qmp_phy {
> struct qcom_qmp *qmp;
> struct reset_control *lane_rst;
> enum phy_mode mode;
> + unsigned int dp_aux_cfg;
> + struct phy_configure_opts_dp dp_opts;
> + struct qmp_phy_dp_clks *dp_clks;
> +};
> +
> +struct qmp_phy_dp_clks {
> + struct qmp_phy *qphy;
> + struct clk_hw dp_link_hw;
> + struct clk_hw dp_pixel_hw;
> };
>
> /**
> @@ -2475,6 +2613,329 @@ static void qcom_qmp_phy_configure(void __iomem *base,
> qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
> }
>
> +static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
> +{
> + struct qcom_qmp *qmp = qphy->qmp;
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> + const struct qmp_phy_init_tbl *serdes_tbl;
> + int serdes_tbl_num;
> + int ret;
> +
> + if (cfg->type == PHY_TYPE_DP) {
> + switch (dp_opts->link_rate) {
> + case 1620:
> + serdes_tbl = qmp_v3_dp_serdes_tbl_rbr;
> + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr);
> + break;
> + case 2700:
> + serdes_tbl = qmp_v3_dp_serdes_tbl_hbr;
> + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr);
> + break;
> + case 5400:
> + serdes_tbl = qmp_v3_dp_serdes_tbl_hbr2;
> + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2);
> + break;
> + case 8100:
> + serdes_tbl = qmp_v3_dp_serdes_tbl_hbr3;
> + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3);
> + break;
> + default:
> + /* Other link rates aren't supported */
> + return -EINVAL;
> + }
> + } else {
> + serdes_tbl = cfg->serdes_tbl;
> + serdes_tbl_num = cfg->serdes_tbl_num;
> + } > +
> + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
If we split DP serdes tables, it would look lile:
qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
cfg->serdes_tbl_num);
if (cfg->type == PHY_TYPE_DP) {
switch (dp_opts->link_rate) {
case 1620:
qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_rbr,
cfg->serdes_tbl_rbr_num);
break;
case 2700:
qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr,
cfg->serdes_tbl_hbr_num);
break;
case 5400:
qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr2,
cfg->serdes_tbl_hbr2_num);
break;
case 8100:
qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr3,
cfg->serdes_tbl_hbr3_num);
break;
default:
/* Other link rates aren't supported */
return -EINVAL;
}
}
> + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
> +
> + if (cfg->has_phy_com_ctrl) {
> + void __iomem *status;
> + unsigned int mask, val;
> +
> + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
> + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> + SERDES_START | PCS_START);
> +
> + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
> + mask = cfg->mask_com_pcs_ready;
> +
> + ret = readl_poll_timeout(status, val, (val & mask), 10,
> + PHY_INIT_COMPLETE_TIMEOUT);
> + if (ret) {
> + dev_err(qmp->dev,
> + "phy common block init timed-out\n");
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy)
> +{
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
> +
> + /* Turn on BIAS current for PHY/PLL */
> + writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
> +
> + /* Make sure that hardware is done with PSR power down */
> + wmb();
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_LANE_0_1_PWRDN |
> + DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
> + DP_PHY_PD_CTL_DP_CLAMP_EN,
> + qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
> +
> + writel(QSERDES_V3_COM_BIAS_EN |
> + QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
> + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
> + QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
> + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> +
> + writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
> + writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
> + writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
> + writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
> + writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
> + writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
> + writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
> + writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
> + writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
> + writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
> + qphy->dp_aux_cfg = 0;
> +
> + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> + PHY_AUX_REQ_ERR_MASK,
> + qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
> +}
> +
> +static const u8 vm_pre_emphasis[4][4] = {
Could you please prefix with v3? V4 will use different tables here
> + { 0x00, 0x0b, 0x12, 0xff }, /* pe0, 0 db */
> + { 0x00, 0x0a, 0x12, 0xff }, /* pe1, 3.5 db */
> + { 0x00, 0x0c, 0xff, 0xff }, /* pe2, 6.0 db */
> + { 0xff, 0xff, 0xff, 0xff } /* pe3, 9.5 db */
> +};
> +
> +/* voltage swing, 0.2v and 1.0v are not support */
> +static const u8 vm_voltage_swing[4][4] = {
> + { 0x07, 0x0f, 0x14, 0xff }, /* sw0, 0.4v */
> + { 0x11, 0x1d, 0x1f, 0xff }, /* sw1, 0.6 v */
> + { 0x18, 0x1f, 0xff, 0xff }, /* sw1, 0.8 v */
> + { 0xff, 0xff, 0xff, 0xff } /* sw1, 1.2 v, optional */
> +};
> +
> +static const u8 vm_pre_emphasis_hbr3_hbr2[4][4] = {
> + { 0x00, 0x0c, 0x15, 0x1a },
> + { 0x02, 0x0e, 0x16, 0xff },
> + { 0x02, 0x11, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 vm_voltage_swing_hbr3_hbr2[4][4] = {
> + { 0x02, 0x12, 0x16, 0x1a },
> + { 0x09, 0x19, 0x1f, 0xff },
> + { 0x10, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 vm_pre_emphasis_hbr_rbr[4][4] = {
> + { 0x00, 0x0c, 0x14, 0x19 },
> + { 0x00, 0x0b, 0x12, 0xff },
> + { 0x00, 0x0b, 0xff, 0xff },
> + { 0x04, 0xff, 0xff, 0xff }
> +};
> +
> +static const u8 vm_voltage_swing_hbr_rbr[4][4] = {
> + { 0x08, 0x0f, 0x16, 0x1f },
> + { 0x11, 0x1e, 0x1f, 0xff },
> + { 0x19, 0x1f, 0xff, 0xff },
> + { 0x1f, 0xff, 0xff, 0xff }
> +};
> +
> +static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy)
With these functions I'm struggling between introducing
PHY_TYPE_DP_V3/V4 and introducing callbacks into qmp_phy_cfg. What would
you prefer?
What about the following struct?
struct qmp_phy_dp_opts {
void (*dp_aux_init)(struct qmp_phy *qphy);
void (*dp_configure_tx)(struct qmp_phy *qphy);
void (*dp_configure_lanes)(struct qmp_phy *qphy);
};
I'm not sure about dp_calibrate().
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy
2020-09-01 13:36 ` Dmitry Baryshkov
@ 2020-09-02 1:01 ` Stephen Boyd
2020-09-03 12:37 ` Dmitry Baryshkov
0 siblings, 1 reply; 21+ messages in thread
From: Stephen Boyd @ 2020-09-02 1:01 UTC (permalink / raw)
To: Dmitry Baryshkov, Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Stephen Boyd,
Jonathan Marek, Rob Clark
Quoting Dmitry Baryshkov (2020-09-01 06:36:34)
> On 26/08/2020 05:47, Stephen Boyd wrote:
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> > index 76d7a9e80f04..dd77c7dfa310 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> > @@ -947,6 +947,130 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
> > QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
> > };
> >
>
> I'd suggest to split common part of the following tables into
> dpphy_cfg->serdes_tbl and add the rest as "addon tables"
> (serdes_tbl_rbr, serdes_rbl_hbr/2/3) into the same dpphy_cfg.
> It would ease V4 QMP DP PHY support.
Ok. I tried to avoid doing that initially in case something is wrong
from the copy over from the DP driver. Also it means the sequence of
writes is different order but I don't think that matters.
>
> > +static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
> > + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
> > + QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> > + QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
[...]
> > @@ -2475,6 +2613,329 @@ static void qcom_qmp_phy_configure(void __iomem *base,
> > qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
> > }
> >
> > +static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
> > +{
> > + struct qcom_qmp *qmp = qphy->qmp;
> > + const struct qmp_phy_cfg *cfg = qphy->cfg;
> > + void __iomem *serdes = qphy->serdes;
> > + const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
> > + const struct qmp_phy_init_tbl *serdes_tbl;
> > + int serdes_tbl_num;
> > + int ret;
> > +
> > + if (cfg->type == PHY_TYPE_DP) {
> > + switch (dp_opts->link_rate) {
> > + case 1620:
> > + serdes_tbl = qmp_v3_dp_serdes_tbl_rbr;
> > + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr);
> > + break;
> > + case 2700:
> > + serdes_tbl = qmp_v3_dp_serdes_tbl_hbr;
> > + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr);
> > + break;
> > + case 5400:
> > + serdes_tbl = qmp_v3_dp_serdes_tbl_hbr2;
> > + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2);
> > + break;
> > + case 8100:
> > + serdes_tbl = qmp_v3_dp_serdes_tbl_hbr3;
> > + serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3);
> > + break;
> > + default:
> > + /* Other link rates aren't supported */
> > + return -EINVAL;
> > + }
> > + } else {
> > + serdes_tbl = cfg->serdes_tbl;
> > + serdes_tbl_num = cfg->serdes_tbl_num;
> > + }
> > + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
>
> If we split DP serdes tables, it would look lile:
> qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
> cfg->serdes_tbl_num);
> if (cfg->type == PHY_TYPE_DP) {
> switch (dp_opts->link_rate) {
> case 1620:
> qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_rbr,
> cfg->serdes_tbl_rbr_num);
> break;
> case 2700:
> qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr,
> cfg->serdes_tbl_hbr_num);
> break;
> case 5400:
> qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr2,
> cfg->serdes_tbl_hbr2_num);
> break;
> case 8100:
> qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr3,
> cfg->serdes_tbl_hbr3_num);
> break;
> default:
> /* Other link rates aren't supported */
> return -EINVAL;
> }
> }
Ok, sure!
>
>
> > + qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
>
>
> > +
> > + if (cfg->has_phy_com_ctrl) {
> > + void __iomem *status;
> > + unsigned int mask, val;
> > +
> > + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
> > + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
> > + SERDES_START | PCS_START);
> > +
> > + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
> > + mask = cfg->mask_com_pcs_ready;
> > +
> > + ret = readl_poll_timeout(status, val, (val & mask), 10,
> > + PHY_INIT_COMPLETE_TIMEOUT);
> > + if (ret) {
> > + dev_err(qmp->dev,
> > + "phy common block init timed-out\n");
> > + return ret;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy)
> > +{
> > + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> > + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> > + qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
> > +
> > + /* Turn on BIAS current for PHY/PLL */
> > + writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
> > + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
> > + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> > +
> > + writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
> > +
> > + /* Make sure that hardware is done with PSR power down */
> > + wmb();
> > + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> > + DP_PHY_PD_CTL_LANE_0_1_PWRDN |
> > + DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
> > + DP_PHY_PD_CTL_DP_CLAMP_EN,
> > + qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
> > +
> > + writel(QSERDES_V3_COM_BIAS_EN |
> > + QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
> > + QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
> > + QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
> > + qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
> > +
> > + writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
> > + writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
> > + writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
> > + writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
> > + writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
> > + writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
> > + writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
> > + writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
> > + writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
> > + writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
> > + qphy->dp_aux_cfg = 0;
> > +
> > + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
> > + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
> > + PHY_AUX_REQ_ERR_MASK,
> > + qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
> > +}
> > +
> > +static const u8 vm_pre_emphasis[4][4] = {
>
> Could you please prefix with v3? V4 will use different tables here
Done.
>
> > + { 0x00, 0x0b, 0x12, 0xff }, /* pe0, 0 db */
> > + { 0x00, 0x0a, 0x12, 0xff }, /* pe1, 3.5 db */
> > + { 0x00, 0x0c, 0xff, 0xff }, /* pe2, 6.0 db */
> > + { 0xff, 0xff, 0xff, 0xff } /* pe3, 9.5 db */
> > +};
> > +
> > +/* voltage swing, 0.2v and 1.0v are not support */
> > +static const u8 vm_voltage_swing[4][4] = {
> > + { 0x07, 0x0f, 0x14, 0xff }, /* sw0, 0.4v */
> > + { 0x11, 0x1d, 0x1f, 0xff }, /* sw1, 0.6 v */
> > + { 0x18, 0x1f, 0xff, 0xff }, /* sw1, 0.8 v */
> > + { 0xff, 0xff, 0xff, 0xff } /* sw1, 1.2 v, optional */
> > +};
> > +
> > +static const u8 vm_pre_emphasis_hbr3_hbr2[4][4] = {
> > + { 0x00, 0x0c, 0x15, 0x1a },
> > + { 0x02, 0x0e, 0x16, 0xff },
> > + { 0x02, 0x11, 0xff, 0xff },
> > + { 0x04, 0xff, 0xff, 0xff }
> > +};
> > +
> > +static const u8 vm_voltage_swing_hbr3_hbr2[4][4] = {
> > + { 0x02, 0x12, 0x16, 0x1a },
> > + { 0x09, 0x19, 0x1f, 0xff },
> > + { 0x10, 0x1f, 0xff, 0xff },
> > + { 0x1f, 0xff, 0xff, 0xff }
> > +};
> > +
> > +static const u8 vm_pre_emphasis_hbr_rbr[4][4] = {
> > + { 0x00, 0x0c, 0x14, 0x19 },
> > + { 0x00, 0x0b, 0x12, 0xff },
> > + { 0x00, 0x0b, 0xff, 0xff },
> > + { 0x04, 0xff, 0xff, 0xff }
> > +};
> > +
> > +static const u8 vm_voltage_swing_hbr_rbr[4][4] = {
> > + { 0x08, 0x0f, 0x16, 0x1f },
> > + { 0x11, 0x1e, 0x1f, 0xff },
> > + { 0x19, 0x1f, 0xff, 0xff },
> > + { 0x1f, 0xff, 0xff, 0xff }
> > +};
> > +
> > +static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy)
>
> With these functions I'm struggling between introducing
> PHY_TYPE_DP_V3/V4 and introducing callbacks into qmp_phy_cfg. What would
> you prefer?
>
> What about the following struct?
>
> struct qmp_phy_dp_opts {
> void (*dp_aux_init)(struct qmp_phy *qphy);
> void (*dp_configure_tx)(struct qmp_phy *qphy);
> void (*dp_configure_lanes)(struct qmp_phy *qphy);
> };
>
> I'm not sure about dp_calibrate().
>
Is there v4 code somewhere that I can see? Another level of indirection
is always a solution, so it is probably fine. This driver is currently
written with many conditionals instead of function tables so I'm not
sure it fits in with the style of how things are done though. The
alternative is to use an enum and call different functions?
The calibrate call is there to "turn the crank" on the aux settings. I
need to cycle through the different values for that aux register so that
aux can be tuned properly. The AUX channel really has another phy that
needs tuning so we're sort of combining the aux and DP link phy together
here by letting the calibrate call tune the AUX phy and the configure
call tune the DP phy. I don't see any sort of concept of an AUX phy
though so this seemed ok. Does v4 need to tune more registers?
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy
2020-09-02 1:01 ` Stephen Boyd
@ 2020-09-03 12:37 ` Dmitry Baryshkov
2020-09-03 12:41 ` Jonathan Marek
2020-09-03 22:55 ` Stephen Boyd
0 siblings, 2 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2020-09-03 12:37 UTC (permalink / raw)
To: Stephen Boyd, Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Stephen Boyd,
Jonathan Marek, Rob Clark
On 02/09/2020 04:01, Stephen Boyd wrote:
> Quoting Dmitry Baryshkov (2020-09-01 06:36:34)
>> With these functions I'm struggling between introducing
>> PHY_TYPE_DP_V3/V4 and introducing callbacks into qmp_phy_cfg. What would
>> you prefer?
>>
>> What about the following struct?
>>
>> struct qmp_phy_dp_opts {
>> void (*dp_aux_init)(struct qmp_phy *qphy);
>> void (*dp_configure_tx)(struct qmp_phy *qphy);
>> void (*dp_configure_lanes)(struct qmp_phy *qphy);
>> };
>>
>> I'm not sure about dp_calibrate().
>>
>
> Is there v4 code somewhere that I can see? Another level of indirection
> is always a solution, so it is probably fine. This driver is currently
> written with many conditionals instead of function tables so I'm not
> sure it fits in with the style of how things are done though. The
> alternative is to use an enum and call different functions?
Downstream DP driver sources can be found here:
https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/dp/dp_catalog_v420.c?h=LA.UM.8.12.r1-13900-sm8250.0
https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/pll/dp_pll_7nm_util.c?h=LA.UM.8.12.r1-13900-sm8250.0
>
> The calibrate call is there to "turn the crank" on the aux settings. I
> need to cycle through the different values for that aux register so that
> aux can be tuned properly. The AUX channel really has another phy that
> needs tuning so we're sort of combining the aux and DP link phy together
> here by letting the calibrate call tune the AUX phy and the configure
> call tune the DP phy. I don't see any sort of concept of an AUX phy
> though so this seemed ok. Does v4 need to tune more registers?
It looks like four values are written to AUX_CFG1:
0x20, 0x13, 0x23, 0x1d
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy
2020-09-03 12:37 ` Dmitry Baryshkov
@ 2020-09-03 12:41 ` Jonathan Marek
2020-09-03 21:35 ` Dmitry Baryshkov
2020-09-03 22:55 ` Stephen Boyd
1 sibling, 1 reply; 21+ messages in thread
From: Jonathan Marek @ 2020-09-03 12:41 UTC (permalink / raw)
To: Dmitry Baryshkov, Stephen Boyd, Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Stephen Boyd,
Rob Clark
On 9/3/20 8:37 AM, Dmitry Baryshkov wrote:
> On 02/09/2020 04:01, Stephen Boyd wrote:
>> Quoting Dmitry Baryshkov (2020-09-01 06:36:34)
>>> With these functions I'm struggling between introducing
>>> PHY_TYPE_DP_V3/V4 and introducing callbacks into qmp_phy_cfg. What would
>>> you prefer?
>>>
>>> What about the following struct?
>>>
>>> struct qmp_phy_dp_opts {
>>> void (*dp_aux_init)(struct qmp_phy *qphy);
>>> void (*dp_configure_tx)(struct qmp_phy *qphy);
>>> void (*dp_configure_lanes)(struct qmp_phy *qphy);
>>> };
>>>
>>> I'm not sure about dp_calibrate().
>>>
>>
>> Is there v4 code somewhere that I can see? Another level of indirection
>> is always a solution, so it is probably fine. This driver is currently
>> written with many conditionals instead of function tables so I'm not
>> sure it fits in with the style of how things are done though. The
>> alternative is to use an enum and call different functions?
>
> Downstream DP driver sources can be found here:
> https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/dp/dp_catalog_v420.c?h=LA.UM.8.12.r1-13900-sm8250.0
>
>
> https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/pll/dp_pll_7nm_util.c?h=LA.UM.8.12.r1-13900-sm8250.0
>
>
>>
>> The calibrate call is there to "turn the crank" on the aux settings. I
>> need to cycle through the different values for that aux register so that
>> aux can be tuned properly. The AUX channel really has another phy that
>> needs tuning so we're sort of combining the aux and DP link phy together
>> here by letting the calibrate call tune the AUX phy and the configure
>> call tune the DP phy. I don't see any sort of concept of an AUX phy
>> though so this seemed ok. Does v4 need to tune more registers?
>
>
> It looks like four values are written to AUX_CFG1:
> 0x20, 0x13, 0x23, 0x1d
>
AFAICT, it only writes 0x13 to AUX_CFG1, in dp_pll_7nm_util.c, and the
qcom,aux-cfg1-settings in dts only has 0x13. Same for all other
AUX_CFGn, which only have one value written. Am I missing something?
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy
2020-09-03 12:41 ` Jonathan Marek
@ 2020-09-03 21:35 ` Dmitry Baryshkov
0 siblings, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2020-09-03 21:35 UTC (permalink / raw)
To: Jonathan Marek, Stephen Boyd, Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Stephen Boyd,
Rob Clark
On 03/09/2020 15:41, Jonathan Marek wrote:
> On 9/3/20 8:37 AM, Dmitry Baryshkov wrote:
>> On 02/09/2020 04:01, Stephen Boyd wrote:
>>> Quoting Dmitry Baryshkov (2020-09-01 06:36:34)
>>>> With these functions I'm struggling between introducing
>>>> PHY_TYPE_DP_V3/V4 and introducing callbacks into qmp_phy_cfg. What
>>>> would
>>>> you prefer?
>>>>
>>>> What about the following struct?
>>>>
>>>> struct qmp_phy_dp_opts {
>>>> void (*dp_aux_init)(struct qmp_phy *qphy);
>>>> void (*dp_configure_tx)(struct qmp_phy *qphy);
>>>> void (*dp_configure_lanes)(struct qmp_phy *qphy);
>>>> };
>>>>
>>>> I'm not sure about dp_calibrate().
>>>>
>>>
>>> Is there v4 code somewhere that I can see? Another level of indirection
>>> is always a solution, so it is probably fine. This driver is currently
>>> written with many conditionals instead of function tables so I'm not
>>> sure it fits in with the style of how things are done though. The
>>> alternative is to use an enum and call different functions?
>>
>> Downstream DP driver sources can be found here:
>> https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/dp/dp_catalog_v420.c?h=LA.UM.8.12.r1-13900-sm8250.0
>>
>>
>> https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/pll/dp_pll_7nm_util.c?h=LA.UM.8.12.r1-13900-sm8250.0
>>
>>
>>>
>>> The calibrate call is there to "turn the crank" on the aux settings. I
>>> need to cycle through the different values for that aux register so that
>>> aux can be tuned properly. The AUX channel really has another phy that
>>> needs tuning so we're sort of combining the aux and DP link phy together
>>> here by letting the calibrate call tune the AUX phy and the configure
>>> call tune the DP phy. I don't see any sort of concept of an AUX phy
>>> though so this seemed ok. Does v4 need to tune more registers?
>>
>>
>> It looks like four values are written to AUX_CFG1:
>> 0x20, 0x13, 0x23, 0x1d
>>
>
> AFAICT, it only writes 0x13 to AUX_CFG1, in dp_pll_7nm_util.c, and the
> qcom,aux-cfg1-settings in dts only has 0x13. Same for all other
> AUX_CFGn, which only have one value written. Am I missing something?
Firmware sources.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy
2020-09-03 12:37 ` Dmitry Baryshkov
2020-09-03 12:41 ` Jonathan Marek
@ 2020-09-03 22:55 ` Stephen Boyd
1 sibling, 0 replies; 21+ messages in thread
From: Stephen Boyd @ 2020-09-03 22:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Kishon Vijay Abraham I, Vinod Koul
Cc: linux-kernel, linux-arm-msm, Jeykumar Sankaran, Chandan Uddaraju,
Vara Reddy, Tanmay Shah, Bjorn Andersson, Manu Gautam,
Sandeep Maheswaram, Douglas Anderson, Sean Paul, Stephen Boyd,
Jonathan Marek, Rob Clark
Quoting Dmitry Baryshkov (2020-09-03 05:37:02)
> On 02/09/2020 04:01, Stephen Boyd wrote:
> > Quoting Dmitry Baryshkov (2020-09-01 06:36:34)
> >> With these functions I'm struggling between introducing
> >> PHY_TYPE_DP_V3/V4 and introducing callbacks into qmp_phy_cfg. What would
> >> you prefer?
> >>
> >> What about the following struct?
> >>
> >> struct qmp_phy_dp_opts {
> >> void (*dp_aux_init)(struct qmp_phy *qphy);
> >> void (*dp_configure_tx)(struct qmp_phy *qphy);
> >> void (*dp_configure_lanes)(struct qmp_phy *qphy);
> >> };
> >>
> >> I'm not sure about dp_calibrate().
> >>
> >
> > Is there v4 code somewhere that I can see? Another level of indirection
> > is always a solution, so it is probably fine. This driver is currently
> > written with many conditionals instead of function tables so I'm not
> > sure it fits in with the style of how things are done though. The
> > alternative is to use an enum and call different functions?
>
> Downstream DP driver sources can be found here:
> https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/dp/dp_catalog_v420.c?h=LA.UM.8.12.r1-13900-sm8250.0
>
> https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/pll/dp_pll_7nm_util.c?h=LA.UM.8.12.r1-13900-sm8250.0
>
Awesome thanks for the pointer.
> >
> > The calibrate call is there to "turn the crank" on the aux settings. I
> > need to cycle through the different values for that aux register so that
> > aux can be tuned properly. The AUX channel really has another phy that
> > needs tuning so we're sort of combining the aux and DP link phy together
> > here by letting the calibrate call tune the AUX phy and the configure
> > call tune the DP phy. I don't see any sort of concept of an AUX phy
> > though so this seemed ok. Does v4 need to tune more registers?
>
>
> It looks like four values are written to AUX_CFG1:
> 0x20, 0x13, 0x23, 0x1d
>
Ok, so still just AUX_CFG1 but now some different values. Maybe it
should come from DT if it really differs based on board design. I don't
know if it does though. If it does differ it would be nice to know what
the settings are and if it doesn't just make sense to iterate through
all 256 of them instead of targeting specific ones.
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2020-09-03 22:55 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-26 2:47 [PATCH v1 0/9] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 1/9] dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 2/9] phy: qcom-qmp: Move phy mode into struct qmp_phy Stephen Boyd
2020-08-26 3:37 ` Bjorn Andersson
2020-08-26 2:47 ` [PATCH v1 3/9] phy: qcom-qmp: Remove 'initialized' in favor of 'init_count' Stephen Boyd
2020-08-26 3:44 ` Bjorn Andersson
2020-08-26 2:47 ` [PATCH v1 4/9] phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy' Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 5/9] phy: qcom-qmp: Get dp_com I/O resource by index Stephen Boyd
2020-08-26 4:36 ` Bjorn Andersson
2020-08-26 21:32 ` Stephen Boyd
2020-08-27 1:59 ` Bjorn Andersson
2020-08-26 2:47 ` [PATCH v1 6/9] phy: qcom-qmp: Add support for DP in USB3+DP combo phy Stephen Boyd
2020-09-01 13:36 ` Dmitry Baryshkov
2020-09-02 1:01 ` Stephen Boyd
2020-09-03 12:37 ` Dmitry Baryshkov
2020-09-03 12:41 ` Jonathan Marek
2020-09-03 21:35 ` Dmitry Baryshkov
2020-09-03 22:55 ` Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 7/9] phy: qcom-qmp: Add support for sc7180 DP phy Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 8/9] clk: qcom: dispcc: Update DP clk ops for phy design Stephen Boyd
2020-08-26 2:47 ` [PATCH v1 9/9] drm/msm/dp: Use qmp phy for DP PLL and PHY Stephen Boyd
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