From: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: "Andreas Färber" <afaerber@suse.de>,
"Rob Herring" <robh+dt@kernel.org>,
"Peter Korsgaard" <peter@korsgaard.com>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-actions@lists.infradead.org
Subject: Re: [PATCH v2 1/4] arm: dts: owl-s500: Fix incorrect PPI interrupt specifiers
Date: Mon, 31 Aug 2020 20:05:20 +0300 [thread overview]
Message-ID: <20200831170520.GA2551342@BV030612LT> (raw)
In-Reply-To: <20200831091925.GC4154@mani>
On Mon, Aug 31, 2020 at 02:49:25PM +0530, Manivannan Sadhasivam wrote:
> On 0828, Cristian Ciocaltea wrote:
> > The PPI interrupts for cortex-a9 were incorrectly specified, fix them.
> >
> > Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar")
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > Reviewed-by: Peter Korsgaard <peter@korsgaard.com>
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Cristi
> Thanks,
> Mani
>
> > ---
> > arch/arm/boot/dts/owl-s500.dtsi | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> > index 5ceb6cc4451d..1dbe4e8b38ac 100644
> > --- a/arch/arm/boot/dts/owl-s500.dtsi
> > +++ b/arch/arm/boot/dts/owl-s500.dtsi
> > @@ -84,21 +84,21 @@ scu: scu@b0020000 {
> > global_timer: timer@b0020200 {
> > compatible = "arm,cortex-a9-global-timer";
> > reg = <0xb0020200 0x100>;
> > - interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> > + interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> > status = "disabled";
> > };
> >
> > twd_timer: timer@b0020600 {
> > compatible = "arm,cortex-a9-twd-timer";
> > reg = <0xb0020600 0x20>;
> > - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> > status = "disabled";
> > };
> >
> > twd_wdt: wdt@b0020620 {
> > compatible = "arm,cortex-a9-twd-wdt";
> > reg = <0xb0020620 0xe0>;
> > - interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> > + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> > status = "disabled";
> > };
> >
> > --
> > 2.28.0
> >
next prev parent reply other threads:[~2020-08-31 17:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-28 13:53 [PATCH v2 0/4] Add initial support for RoseapplePi SBC Cristian Ciocaltea
2020-08-28 13:53 ` [PATCH v2 1/4] arm: dts: owl-s500: Fix incorrect PPI interrupt specifiers Cristian Ciocaltea
2020-08-31 9:19 ` Manivannan Sadhasivam
2020-08-31 17:05 ` Cristian Ciocaltea [this message]
2020-08-28 13:53 ` [PATCH v2 2/4] dt-bindings: Add vendor prefix for RoseapplePi.org Cristian Ciocaltea
2020-08-31 9:28 ` Manivannan Sadhasivam
2020-09-22 8:13 ` Manivannan Sadhasivam
2020-08-28 13:53 ` [PATCH v2 3/4] dt-bindings: arm: actions: Document RoseapplePi Cristian Ciocaltea
2020-08-28 13:53 ` [PATCH v2 4/4] arm: dts: owl-s500: Add RoseapplePi Cristian Ciocaltea
2020-08-31 9:26 ` Manivannan Sadhasivam
2020-08-31 17:06 ` Cristian Ciocaltea
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