From: Yazen Ghannam <Yazen.Ghannam@amd.com>
To: linux-edac@vger.kernel.org
Cc: Yazen Ghannam <Yazen.Ghannam@amd.com>,
linux-kernel@vger.kernel.org, tony.luck@intel.com,
x86@kernel.org, Smita.KoralahalliChannabasappa@amd.com
Subject: [PATCH v2 4/8] x86/MCE/AMD: Use defines for register addresses in translation code
Date: Thu, 3 Sep 2020 20:01:40 +0000 [thread overview]
Message-ID: <20200903200144.310991-5-Yazen.Ghannam@amd.com> (raw)
In-Reply-To: <20200903200144.310991-1-Yazen.Ghannam@amd.com>
From: Yazen Ghannam <yazen.ghannam@amd.com>
Replace raw register offset values in the AMD address translation code
with named definitions.
Also, drop comments that only note the register names.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20200814191449.183998-3-Yazen.Ghannam@amd.com
v1 -> v2:
* New patch based on comments for v1 Patch 2.
arch/x86/kernel/cpu/mce/amd.c | 26 +++++++++++++++-----------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index be96f77004ad..1e0510fd5afc 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -675,6 +675,14 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
deferred_error_interrupt_enable(c);
}
+#define DF_F0_FABRICINSTINFO3 0x50
+#define DF_F0_MMIOHOLE 0x104
+#define DF_F0_DRAMBASEADDR 0x110
+#define DF_F0_DRAMLIMITADDR 0x114
+#define DF_F0_DRAMOFFSET 0x1B4
+
+#define DF_F1_SYSFABRICID 0x208
+
int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
{
u64 dram_base_addr, dram_limit_addr, dram_hole_base;
@@ -691,22 +699,21 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
u8 cs_mask, cs_id = 0;
bool hash_enabled = false;
- /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
- if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
+ if (amd_df_indirect_read(nid, 0, DF_F0_DRAMOFFSET, umc, &tmp))
goto out_err;
/* Remove HiAddrOffset from normalized address, if enabled: */
if (tmp & BIT(0)) {
u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
+ /* Check if base 1 is used. */
if (norm_addr >= hi_addr_offset) {
ret_addr -= hi_addr_offset;
base = 1;
}
}
- /* Read D18F0x110 (DramBaseAddress). */
- if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
+ if (amd_df_indirect_read(nid, 0, DF_F0_DRAMBASEADDR + (8 * base), umc, &tmp))
goto out_err;
/* Check if address range is valid. */
@@ -728,8 +735,7 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
goto out_err;
}
- /* Read D18F0x114 (DramLimitAddress). */
- if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
+ if (amd_df_indirect_read(nid, 0, DF_F0_DRAMLIMITADDR + (8 * base), umc, &tmp))
goto out_err;
intlv_num_sockets = (tmp >> 8) & 0x1;
@@ -780,12 +786,11 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
u8 die_id_bit, sock_id_bit, cs_fabric_id;
/*
- * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
* This is the fabric id for this coherent slave. Use
* umc/channel# as instance id of the coherent slave
* for FICAA.
*/
- if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
+ if (amd_df_indirect_read(nid, 0, DF_F0_FABRICINSTINFO3, umc, &tmp))
goto out_err;
cs_fabric_id = (tmp >> 8) & 0xFF;
@@ -800,9 +805,8 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
sock_id_bit = die_id_bit;
- /* Read D18F1x208 (SystemFabricIdMask). */
if (intlv_num_dies || intlv_num_sockets)
- if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
+ if (amd_df_indirect_read(nid, 1, DF_F1_SYSFABRICID, umc, &tmp))
goto out_err;
/* If interleaved over more than 1 die. */
@@ -841,7 +845,7 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
/* If legacy MMIO hole enabled */
if (lgcy_mmio_hole_en) {
- if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
+ if (amd_df_indirect_read(nid, 0, DF_F0_MMIOHOLE, umc, &tmp))
goto out_err;
dram_hole_base = tmp & GENMASK(31, 24);
--
2.25.1
next prev parent reply other threads:[~2020-09-03 20:02 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-03 20:01 [PATCH v2 0/8] AMD MCA Address Translation Updates Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 1/8] x86/CPU/AMD: Save NodeId on AMD-based systems Yazen Ghannam
2020-09-09 18:06 ` Borislav Petkov
2020-09-09 20:17 ` Yazen Ghannam
2020-09-10 10:14 ` Borislav Petkov
2020-09-14 19:20 ` Yazen Ghannam
2020-09-15 8:35 ` Borislav Petkov
2020-09-16 19:51 ` Yazen Ghannam
2020-09-17 10:37 ` Borislav Petkov
2020-09-17 16:20 ` Yazen Ghannam
2020-09-17 16:40 ` Borislav Petkov
2020-09-17 19:44 ` Yazen Ghannam
2020-09-17 20:10 ` Borislav Petkov
2020-09-03 20:01 ` [PATCH v2 2/8] x86/CPU/AMD: Remove amd_get_nb_id() Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 3/8] EDAC/mce_amd: Use struct cpuinfo_x86.node_id for NodeId Yazen Ghannam
2020-09-03 20:01 ` Yazen Ghannam [this message]
2020-09-03 20:01 ` [PATCH v2 5/8] x86/MCE/AMD: Use macros to get bitfields in translation code Yazen Ghannam
2020-09-21 13:58 ` Borislav Petkov
2020-09-03 20:01 ` [PATCH v2 6/8] x86/MCE/AMD: Drop tmp variable " Yazen Ghannam
2020-09-23 8:05 ` Borislav Petkov
2020-09-23 16:05 ` Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 7/8] x86/MCE/AMD: Group register reads " Yazen Ghannam
2020-09-03 20:01 ` [PATCH v2 8/8] x86/MCE/AMD Support new memory interleaving modes during address translation Yazen Ghannam
2020-09-23 8:20 ` Borislav Petkov
2020-09-23 16:25 ` Yazen Ghannam
2020-09-25 7:22 ` Borislav Petkov
2020-09-25 19:51 ` Yazen Ghannam
2020-09-28 9:47 ` Borislav Petkov
2020-09-28 15:53 ` Yazen Ghannam
2020-09-28 18:14 ` Borislav Petkov
2020-09-29 13:21 ` Yazen Ghannam
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