From: Krzysztof Kozlowski <krzk@kernel.org>
To: Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Subject: [PATCH v2 03/14] arm64: dts: imx8mm-evk: Align pin configuration group names with schema
Date: Fri, 4 Sep 2020 08:27:32 +0200 [thread overview]
Message-ID: <20200904062743.6273-3-krzk@kernel.org> (raw)
In-Reply-To: <20200904062743.6273-1-krzk@kernel.org>
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index 1c39a2b90ee1..27e54583a8e4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -456,13 +456,13 @@
>;
};
- pinctrl_pmic: pmicirq {
+ pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
@@ -490,7 +490,7 @@
>;
};
- pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>;
@@ -508,7 +508,7 @@
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
@@ -520,7 +520,7 @@
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
@@ -548,7 +548,7 @@
>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
@@ -564,7 +564,7 @@
>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
--
2.17.1
next prev parent reply other threads:[~2020-09-04 6:28 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-04 6:27 [PATCH v2 01/14] arm64: dts: imx8mm-beacon: Align pin configuration group names with schema Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 02/14] arm64: dts: imx8mm-evk: Add 32.768 kHz clock to PMIC Krzysztof Kozlowski
2020-09-04 6:27 ` Krzysztof Kozlowski [this message]
2020-09-04 6:27 ` [PATCH v2 04/14] arm64: dts: imx8mm-ddr4-evk: Align pin configuration group names with schema Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 05/14] arm64: dts: imx8mn-ddr4-evk: Align regulator " Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 06/14] arm64: dts: imx8mn-evk: Align pin configuration group " Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 07/14] arm64: dts: imx8mq-evk: " Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 08/14] arm64: dts: imx8mq-librem5-devkit: " Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 09/14] arm64: dts: imx8mq-phanbell: " Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 10/14] arm64: dts: imx8mq-pico-pi: " Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 11/14] arm64: dts: imx8mq-sr-som: " Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 12/14] arm64: dts: imx8mq-hummingboard-pulse: " Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 13/14] arm64: dts: imx8qxp-colibri: " Krzysztof Kozlowski
2020-09-04 6:27 ` [PATCH v2 14/14] ARM: dts: imx28-m28: Align GPMI NAND node name " Krzysztof Kozlowski
2020-09-05 8:05 ` Shawn Guo
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