From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BACC0C43461 for ; Fri, 4 Sep 2020 19:19:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 821C4206B8 for ; Fri, 4 Sep 2020 19:19:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1599247140; bh=r1W+FDL0N2JbSaXM09U2olvU+2IazujrmTKEKN7XGCE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=oXFAE40XZwUQFqk5lYl3ulNL4SipfM5qDiUxmybo52HH7QhIa8Z3rJXlgQ1LNcGDd BzGv1gxJdsJ3VpmLejXZMPigXgSPheE8Nx7qtirjIQMAEA+pMWUHgJuk1q2hKfP81y N7rzwvWya5MYmZK8iy4ZM4UXt2W4j1H493KRCfNc= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727905AbgIDTS7 (ORCPT ); Fri, 4 Sep 2020 15:18:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:48028 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727792AbgIDTSz (ORCPT ); Fri, 4 Sep 2020 15:18:55 -0400 Received: from quaco.ghostprotocols.net (unknown [179.97.37.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 62A5A208CA; Fri, 4 Sep 2020 19:18:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1599247134; bh=r1W+FDL0N2JbSaXM09U2olvU+2IazujrmTKEKN7XGCE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=gdHozSgaYHu1p9+x78KMilXM9wfNS77hr7aaE3CE+810s8miAMJfNCLoNIY1I/4ZB Zyi/HrESlM7XWCLOJ8fobfFF2HAarYOoDXYvfcroMGxnAKJxUSPtd1QuyLQ/f23pVN WEfmxlTOlWK4VZnL2QKjLg3JVFOBZnwkQRK4Q/uk= Received: by quaco.ghostprotocols.net (Postfix, from userid 1000) id 470A640D3D; Fri, 4 Sep 2020 16:18:52 -0300 (-03) Date: Fri, 4 Sep 2020 16:18:52 -0300 From: Arnaldo Carvalho de Melo To: Kim Phillips Cc: Arnaldo Carvalho de Melo , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Vijay Thakkar , Andi Kleen , John Garry , Kan Liang , Yunfeng Ye , Jin Yao , Martin =?utf-8?B?TGnFoWth?= , Borislav Petkov , Jon Grimm , Martin Jambor , Michael Petlan , William Cohen , Stephane Eranian , Ian Rogers , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH 1/4] perf vendor events amd: Add L2 Prefetch events for zen1 Message-ID: <20200904191852.GE3753976@kernel.org> References: <20200901220944.277505-1-kim.phillips@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20200901220944.277505-1-kim.phillips@amd.com> X-Url: http://acmel.wordpress.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Em Tue, Sep 01, 2020 at 05:09:41PM -0500, Kim Phillips escreveu: > Later revisions of PPRs that post-date the original Family 17h events > submission patch add these events. > > Specifically, they were not in this 2017 revision of the F17h PPR: > > Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors Rev 1.14 - April 15, 2017 > > But e.g., are included in this 2019 version of the PPR: > > Processor Programming Reference (PPR) for AMD Family 17h Model 18h, Revision B1 Processors Rev. 3.14 - Sep 26, 2019 Thanks, applied. - Arnaldo > Signed-off-by: Kim Phillips > Fixes: 98c07a8f74f8 ("perf vendor events amd: perf PMU events for AMD Family 17h") > Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 > Cc: Peter Zijlstra > Cc: Ingo Molnar > Cc: Arnaldo Carvalho de Melo > Cc: Mark Rutland > Cc: Alexander Shishkin > Cc: Jiri Olsa > Cc: Namhyung Kim > Cc: Vijay Thakkar > Cc: Andi Kleen > Cc: John Garry > Cc: Kan Liang > Cc: Yunfeng Ye > Cc: Jin Yao > Cc: "Martin Liška" > Cc: Borislav Petkov > Cc: Jon Grimm > Cc: Martin Jambor > Cc: Michael Petlan > Cc: William Cohen > Cc: Stephane Eranian > Cc: Ian Rogers > Cc: linux-perf-users@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: stable@vger.kernel.org > --- > .../pmu-events/arch/x86/amdzen1/cache.json | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > index 404d4c569c01..695ed3ffa3a6 100644 > --- a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > +++ b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > @@ -249,6 +249,24 @@ > "BriefDescription": "Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2.", > "UMask": "0x1" > }, > + { > + "EventName": "l2_pf_hit_l2", > + "EventCode": "0x70", > + "BriefDescription": "L2 prefetch hit in L2.", > + "UMask": "0xff" > + }, > + { > + "EventName": "l2_pf_miss_l2_hit_l3", > + "EventCode": "0x71", > + "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", > + "UMask": "0xff" > + }, > + { > + "EventName": "l2_pf_miss_l2_l3", > + "EventCode": "0x72", > + "BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.", > + "UMask": "0xff" > + }, > { > "EventName": "l3_request_g1.caching_l3_cache_accesses", > "EventCode": "0x01", > -- > 2.27.0 > -- - Arnaldo