From: Rob Clark <robdclark@gmail.com>
To: iommu@lists.linux-foundation.org,
dri-devel@lists.freedesktop.org, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>
Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Sibi Sankar <sibis@codeaurora.org>,
Vivek Gautam <vivek.gautam@codeaurora.org>,
Stephen Boyd <swboyd@chromium.org>,
Akhil P Oommen <akhilpo@codeaurora.org>,
Rob Clark <robdclark@chromium.org>,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
Jordan Crouse <jcrouse@codeaurora.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Thierry Reding <treding@nvidia.com>,
Krishna Reddy <vdumpa@nvidia.com>,
linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU
DRIVERS), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v17 17/20] iommu/arm-smmu: Add a way for implementations to influence SCTLR
Date: Sat, 5 Sep 2020 13:04:23 -0700 [thread overview]
Message-ID: <20200905200454.240929-18-robdclark@gmail.com> (raw)
In-Reply-To: <20200905200454.240929-1-robdclark@gmail.com>
From: Rob Clark <robdclark@chromium.org>
For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
pending translations are not terminated on iova fault. Otherwise
a terminated CP read could hang the GPU by returning invalid
command-stream data.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++
drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++
drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++
3 files changed, 12 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 1e942eed2dfc..0663d7d26908 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -129,6 +129,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
(smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
+ /*
+ * On the GPU device we want to process subsequent transactions after a
+ * fault to keep the GPU from hanging
+ */
+ smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF;
+
/*
* Initialize private interface with GPU:
*/
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index dad7fa86fbd4..1f06ab219819 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
reg |= ARM_SMMU_SCTLR_E;
+ reg |= cfg->sctlr_set;
+ reg &= ~cfg->sctlr_clr;
+
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
}
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index 6c5ff9999eae..ddf2ca4c923d 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -144,6 +144,7 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_CB_SCTLR 0x0
#define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12)
#define ARM_SMMU_SCTLR_CFCFG BIT(7)
+#define ARM_SMMU_SCTLR_HUPCF BIT(8)
#define ARM_SMMU_SCTLR_CFIE BIT(6)
#define ARM_SMMU_SCTLR_CFRE BIT(5)
#define ARM_SMMU_SCTLR_E BIT(4)
@@ -341,6 +342,8 @@ struct arm_smmu_cfg {
u16 asid;
u16 vmid;
};
+ u32 sctlr_set; /* extra bits to set in SCTLR */
+ u32 sctlr_clr; /* bits to mask in SCTLR */
enum arm_smmu_cbar_type cbar;
enum arm_smmu_context_fmt fmt;
};
--
2.26.2
next prev parent reply other threads:[~2020-09-05 20:05 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-05 20:04 [PATCH v17 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables Rob Clark
2020-09-05 20:04 ` [PATCH v17 01/20] drm/msm: Remove dangling submitqueue references Rob Clark
2020-09-05 20:04 ` [PATCH v17 02/20] drm/msm: Add private interface for adreno-smmu Rob Clark
2020-09-05 20:04 ` [PATCH v17 03/20] drm/msm/gpu: Add dev_to_gpu() helper Rob Clark
2020-09-05 20:04 ` [PATCH v17 04/20] drm/msm: Set adreno_smmu as gpu's drvdata Rob Clark
2020-09-05 20:04 ` [PATCH v17 05/20] drm/msm: Add a context pointer to the submitqueue Rob Clark
2020-09-05 20:04 ` [PATCH v17 06/20] drm/msm: Drop context arg to gpu->submit() Rob Clark
2020-09-05 20:04 ` [PATCH v17 07/20] drm/msm: Set the global virtual address range from the IOMMU domain Rob Clark
2020-09-05 20:04 ` [PATCH v17 08/20] drm/msm: Add support to create a local pagetable Rob Clark
2020-09-05 20:04 ` [PATCH v17 09/20] drm/msm: Add support for private address space instances Rob Clark
2020-09-05 20:04 ` [PATCH v17 10/20] drm/msm/a6xx: Add support for per-instance pagetables Rob Clark
2020-09-05 20:04 ` [PATCH v17 11/20] drm/msm: Show process names in gem_describe Rob Clark
2020-09-05 20:04 ` [PATCH v17 12/20] iommu/arm-smmu: Pass io-pgtable config to implementation specific function Rob Clark
2020-09-05 20:04 ` [PATCH v17 13/20] iommu/arm-smmu: Add support for split pagetables Rob Clark
2020-09-05 20:04 ` [PATCH v17 14/20] iommu/arm-smmu: Prepare for the adreno-smmu implementation Rob Clark
2020-09-05 20:04 ` [PATCH v17 15/20] iommu/arm-smmu: Constify some helpers Rob Clark
2020-09-05 20:04 ` [PATCH v17 16/20] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU Rob Clark
2020-09-05 20:04 ` Rob Clark [this message]
2020-09-05 20:04 ` [PATCH v17 18/20] dt-bindings: arm-smmu: Add compatible string for Adreno " Rob Clark
2020-09-05 20:04 ` [PATCH v17 19/20] arm: dts: qcom: sm845: Set the compatible string for the " Rob Clark
2020-09-05 20:04 ` [PATCH v17 20/20] arm: dts: qcom: sc7180: " Rob Clark
2020-09-21 21:30 ` [PATCH v17 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables Will Deacon
2020-09-22 1:27 ` Rob Clark
2020-09-22 2:53 ` Jordan Crouse
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200905200454.240929-18-robdclark@gmail.com \
--to=robdclark@gmail.com \
--cc=akhilpo@codeaurora.org \
--cc=bjorn.andersson@linaro.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=freedreno@lists.freedesktop.org \
--cc=gregkh@linuxfoundation.org \
--cc=iommu@lists.linux-foundation.org \
--cc=jcrouse@codeaurora.org \
--cc=joro@8bytes.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robdclark@chromium.org \
--cc=robin.murphy@arm.com \
--cc=saiprakash.ranjan@codeaurora.org \
--cc=sibis@codeaurora.org \
--cc=swboyd@chromium.org \
--cc=treding@nvidia.com \
--cc=vdumpa@nvidia.com \
--cc=vivek.gautam@codeaurora.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).