From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Florian Fainelli <f.fainelli@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM
BCM7XXX ARM ARCHITECTURE),
devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
FLATTENED DEVICE TREE BINDINGS),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH 1/2] dt-bindings: bus: Document breakpoint interrupt for gisb-arb
Date: Sun, 6 Sep 2020 20:17:23 -0700 [thread overview]
Message-ID: <20200907031724.3512099-2-f.fainelli@gmail.com> (raw)
In-Reply-To: <20200907031724.3512099-1-f.fainelli@gmail.com>
The GISB arbiter can have a third and optional interrupt to handle GISB
breakpoints.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
index 729def62f0c5..10f6d0a8159d 100644
--- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
@@ -10,7 +10,8 @@ Required properties:
"brcm,bcm7038-gisb-arb" for 130nm chips
- reg: specifies the base physical address and size of the registers
- interrupts: specifies the two interrupts (timeout and TEA) to be used from
- the parent interrupt controller
+ the parent interrupt controller. A third optional interrupt may be specified
+ for breakpoints.
Optional properties:
--
2.25.1
next prev parent reply other threads:[~2020-09-07 3:17 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-07 3:17 [PATCH 0/2] bus: brcmstb_gisb: Add support for breakpoint interrupts Florian Fainelli
2020-09-07 3:17 ` Florian Fainelli [this message]
2020-09-07 3:17 ` [PATCH 2/2] " Florian Fainelli
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