From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3C0CC433E2 for ; Mon, 7 Sep 2020 11:35:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9D12320C09 for ; Mon, 7 Sep 2020 11:35:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729144AbgIGLfm (ORCPT ); Mon, 7 Sep 2020 07:35:42 -0400 Received: from foss.arm.com ([217.140.110.172]:33510 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729135AbgIGLfH (ORCPT ); Mon, 7 Sep 2020 07:35:07 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C99461045; Mon, 7 Sep 2020 04:02:13 -0700 (PDT) Received: from e121166-lin.cambridge.arm.com (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5E3693F66E; Mon, 7 Sep 2020 04:02:12 -0700 (PDT) Date: Mon, 7 Sep 2020 12:02:07 +0100 From: Lorenzo Pieralisi To: Ansuel Smith Cc: Stanimir Varbanov , stable@vger.kernel.org, Andy Gross , Bjorn Andersson , Rob Herring , Bjorn Helgaas , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0 Message-ID: <20200907110207.GA7573@e121166-lin.cambridge.arm.com> References: <20200901124955.137-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200901124955.137-1-ansuelsmth@gmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 01, 2020 at 02:49:54PM +0200, Ansuel Smith wrote: > Qsdk U-Boot can incorrectly leave the PCIe interface in an undefined > state if bootm command is used instead of bootipq. This is caused by the > not deinit of PCIe when bootm is called. Reset the PCIe before init > anyway to fix this U-Boot bug. > > Signed-off-by: Ansuel Smith > Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") > Cc: stable@vger.kernel.org # v4.19+ > --- > drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) Applied to pci/qcom, thanks. Lorenzo > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 3aac77a295ba..82336bbaf8dc 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -302,6 +302,9 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) > reset_control_assert(res->por_reset); > reset_control_assert(res->ext_reset); > reset_control_assert(res->phy_reset); > + > + writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); > + > regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); > } > > @@ -314,6 +317,16 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) > u32 val; > int ret; > > + /* reset the PCIe interface as uboot can leave it undefined state */ > + reset_control_assert(res->pci_reset); > + reset_control_assert(res->axi_reset); > + reset_control_assert(res->ahb_reset); > + reset_control_assert(res->por_reset); > + reset_control_assert(res->ext_reset); > + reset_control_assert(res->phy_reset); > + > + writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); > + > ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); > if (ret < 0) { > dev_err(dev, "cannot enable regulators\n"); > -- > 2.27.0 >