* [PATCH v3 0/2] Add MStar interrupt controller support
@ 2020-09-02 6:33 Mark-PK Tsai
2020-09-02 6:33 ` [PATCH v3 1/2] irqchip: irq-mst: " Mark-PK Tsai
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Mark-PK Tsai @ 2020-09-02 6:33 UTC (permalink / raw)
To: maz, robh+dt
Cc: mark-pk.tsai, alix.wu, daniel, devicetree, jason,
linux-arm-kernel, linux-kernel, linux-mediatek, matthias.bgg,
tglx, yj.chiang
MStar contain a legacy interrupt controller that routes interrupts
to the GIC. SigmaStar and Mediatek TV SoCs also have this interrupt
controller IP.
Mark-PK Tsai (2):
irqchip: irq-mst: Add MStar interrupt controller support
dt-bindings: interrupt-controller: Add MStar interrupt controller
.../interrupt-controller/mstar,mst-intc.yaml | 64 ++++++
MAINTAINERS | 7 +
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-mst-intc.c | 199 ++++++++++++++++++
5 files changed, 279 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
create mode 100644 drivers/irqchip/irq-mst-intc.c
--
2.18.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/2] irqchip: irq-mst: Add MStar interrupt controller support
2020-09-02 6:33 [PATCH v3 0/2] Add MStar interrupt controller support Mark-PK Tsai
@ 2020-09-02 6:33 ` Mark-PK Tsai
2020-10-11 17:57 ` [tip: irq/core] irqchip/irq-mst: " tip-bot2 for Mark-PK Tsai
2020-09-02 6:33 ` [PATCH v3 2/2] dt-bindings: interrupt-controller: Add MStar interrupt controller Mark-PK Tsai
2020-09-13 15:59 ` [PATCH v3 0/2] Add MStar interrupt controller support Marc Zyngier
2 siblings, 1 reply; 8+ messages in thread
From: Mark-PK Tsai @ 2020-09-02 6:33 UTC (permalink / raw)
To: maz, robh+dt
Cc: mark-pk.tsai, alix.wu, daniel, devicetree, jason,
linux-arm-kernel, linux-kernel, linux-mediatek, matthias.bgg,
tglx, yj.chiang
Add MStar interrupt controller support using hierarchy irq
domain.
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Tested-by: Daniel Palmer <daniel@thingy.jp>
---
MAINTAINERS | 7 ++
drivers/irqchip/Kconfig | 8 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-mst-intc.c | 199 +++++++++++++++++++++++++++++++++
4 files changed, 215 insertions(+)
create mode 100644 drivers/irqchip/irq-mst-intc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index e4647c84c987..f3ce60b181af 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11755,6 +11755,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/
T: git git://linuxtv.org/anttip/media_tree.git
F: drivers/media/usb/msi2500/
+MSTAR INTERRUPT CONTROLLER DRIVER
+M: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
+M: Daniel Palmer <daniel@thingy.jp>
+S: Maintained
+F: Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
+F: drivers/irqchip/irq-mst-intc.c
+
MSYSTEMS DISKONCHIP G3 MTD DRIVER
M: Robert Jarzmik <robert.jarzmik@free.fr>
L: linux-mtd@lists.infradead.org
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index bfc9719dbcdc..c6321a69aed9 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -571,4 +571,12 @@ config LOONGSON_PCH_MSI
help
Support for the Loongson PCH MSI Controller.
+config MST_IRQ
+ bool "MStar Interrupt Controller"
+ default ARCH_MEDIATEK
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Support MStar Interrupt Controller.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 133f9c45744a..e2688a62403e 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -111,3 +111,4 @@ obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
+obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
diff --git a/drivers/irqchip/irq-mst-intc.c b/drivers/irqchip/irq-mst-intc.c
new file mode 100644
index 000000000000..4be077591898
--- /dev/null
+++ b/drivers/irqchip/irq-mst-intc.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
+ */
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define INTC_MASK 0x0
+#define INTC_EOI 0x20
+
+struct mst_intc_chip_data {
+ raw_spinlock_t lock;
+ unsigned int irq_start, nr_irqs;
+ void __iomem *base;
+ bool no_eoi;
+};
+
+static void mst_set_irq(struct irq_data *d, u32 offset)
+{
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
+ u16 val, mask;
+ unsigned long flags;
+
+ mask = 1 << (hwirq % 16);
+ offset += (hwirq / 16) * 4;
+
+ raw_spin_lock_irqsave(&cd->lock, flags);
+ val = readw_relaxed(cd->base + offset) | mask;
+ writew_relaxed(val, cd->base + offset);
+ raw_spin_unlock_irqrestore(&cd->lock, flags);
+}
+
+static void mst_clear_irq(struct irq_data *d, u32 offset)
+{
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
+ u16 val, mask;
+ unsigned long flags;
+
+ mask = 1 << (hwirq % 16);
+ offset += (hwirq / 16) * 4;
+
+ raw_spin_lock_irqsave(&cd->lock, flags);
+ val = readw_relaxed(cd->base + offset) & ~mask;
+ writew_relaxed(val, cd->base + offset);
+ raw_spin_unlock_irqrestore(&cd->lock, flags);
+}
+
+static void mst_intc_mask_irq(struct irq_data *d)
+{
+ mst_set_irq(d, INTC_MASK);
+ irq_chip_mask_parent(d);
+}
+
+static void mst_intc_unmask_irq(struct irq_data *d)
+{
+ mst_clear_irq(d, INTC_MASK);
+ irq_chip_unmask_parent(d);
+}
+
+static void mst_intc_eoi_irq(struct irq_data *d)
+{
+ struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
+
+ if (!cd->no_eoi)
+ mst_set_irq(d, INTC_EOI);
+
+ irq_chip_eoi_parent(d);
+}
+
+static struct irq_chip mst_intc_chip = {
+ .name = "mst-intc",
+ .irq_mask = mst_intc_mask_irq,
+ .irq_unmask = mst_intc_unmask_irq,
+ .irq_eoi = mst_intc_eoi_irq,
+ .irq_get_irqchip_state = irq_chip_get_parent_state,
+ .irq_set_irqchip_state = irq_chip_set_parent_state,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
+ .irq_set_type = irq_chip_set_type_parent,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .flags = IRQCHIP_SET_TYPE_MASKED |
+ IRQCHIP_SKIP_SET_WAKE |
+ IRQCHIP_MASK_ON_SUSPEND,
+};
+
+static int mst_intc_domain_translate(struct irq_domain *d,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ struct mst_intc_chip_data *cd = d->host_data;
+
+ if (is_of_node(fwspec->fwnode)) {
+ if (fwspec->param_count != 3)
+ return -EINVAL;
+
+ /* No PPI should point to this domain */
+ if (fwspec->param[0] != 0)
+ return -EINVAL;
+
+ if (fwspec->param[1] >= cd->nr_irqs)
+ return -EINVAL;
+
+ *hwirq = fwspec->param[1];
+ *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int mst_intc_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *data)
+{
+ int i;
+ irq_hw_number_t hwirq;
+ struct irq_fwspec parent_fwspec, *fwspec = data;
+ struct mst_intc_chip_data *cd = domain->host_data;
+
+ /* Not GIC compliant */
+ if (fwspec->param_count != 3)
+ return -EINVAL;
+
+ /* No PPI should point to this domain */
+ if (fwspec->param[0])
+ return -EINVAL;
+
+ hwirq = fwspec->param[1];
+ for (i = 0; i < nr_irqs; i++)
+ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+ &mst_intc_chip,
+ domain->host_data);
+
+ parent_fwspec = *fwspec;
+ parent_fwspec.fwnode = domain->parent->fwnode;
+ parent_fwspec.param[1] = cd->irq_start + hwirq;
+ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_fwspec);
+}
+
+static const struct irq_domain_ops mst_intc_domain_ops = {
+ .translate = mst_intc_domain_translate,
+ .alloc = mst_intc_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+};
+
+int __init
+mst_intc_of_init(struct device_node *dn, struct device_node *parent)
+{
+ struct irq_domain *domain, *domain_parent;
+ struct mst_intc_chip_data *cd;
+ u32 irq_start, irq_end;
+
+ domain_parent = irq_find_host(parent);
+ if (!domain_parent) {
+ pr_err("mst-intc: interrupt-parent not found\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32_index(dn, "mstar,irqs-map-range", 0, &irq_start) ||
+ of_property_read_u32_index(dn, "mstar,irqs-map-range", 1, &irq_end))
+ return -EINVAL;
+
+ cd = kzalloc(sizeof(*cd), GFP_KERNEL);
+ if (!cd)
+ return -ENOMEM;
+
+ cd->base = of_iomap(dn, 0);
+ if (!cd->base) {
+ kfree(cd);
+ return -ENOMEM;
+ }
+
+ cd->no_eoi = of_property_read_bool(dn, "mstar,intc-no-eoi");
+ raw_spin_lock_init(&cd->lock);
+ cd->irq_start = irq_start;
+ cd->nr_irqs = irq_end - irq_start + 1;
+ domain = irq_domain_add_hierarchy(domain_parent, 0, cd->nr_irqs, dn,
+ &mst_intc_domain_ops, cd);
+ if (!domain) {
+ iounmap(cd->base);
+ kfree(cd);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+IRQCHIP_DECLARE(mst_intc, "mstar,mst-intc", mst_intc_of_init);
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] dt-bindings: interrupt-controller: Add MStar interrupt controller
2020-09-02 6:33 [PATCH v3 0/2] Add MStar interrupt controller support Mark-PK Tsai
2020-09-02 6:33 ` [PATCH v3 1/2] irqchip: irq-mst: " Mark-PK Tsai
@ 2020-09-02 6:33 ` Mark-PK Tsai
2020-09-02 6:52 ` [PATCH " Mark-PK Tsai
` (2 more replies)
2020-09-13 15:59 ` [PATCH v3 0/2] Add MStar interrupt controller support Marc Zyngier
2 siblings, 3 replies; 8+ messages in thread
From: Mark-PK Tsai @ 2020-09-02 6:33 UTC (permalink / raw)
To: maz, robh+dt
Cc: mark-pk.tsai, alix.wu, daniel, devicetree, jason,
linux-arm-kernel, linux-kernel, linux-mediatek, matthias.bgg,
tglx, yj.chiang
Add binding for MStar interrupt controller.
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
---
.../interrupt-controller/mstar,mst-intc.yaml | 64 +++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
new file mode 100644
index 000000000000..bbf0f26cd008
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MStar Interrupt Controller
+
+maintainers:
+ - Mark-PK Tsai <mark-pk.tsai@mediatek.com>
+
+description: |+
+ MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy
+ interrupt controllers that routes interrupts to the GIC.
+
+ The HW block exposes a number of interrupt controllers, each
+ can support up to 64 interrupts.
+
+properties:
+ compatible:
+ const: mstar,mst-intc
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 3
+ description: |
+ Use the same format as specified by GIC in arm,gic.yaml.
+
+ reg:
+ maxItems: 1
+
+ mstar,irqs-map-range:
+ description: |
+ The range <start, end> of parent interrupt controller's interrupt
+ lines that are hardwired to mstar interrupt controller.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ minItems: 2
+ maxItems: 2
+
+ mstar,intc-no-eoi:
+ description:
+ Mark this controller has no End Of Interrupt(EOI) implementation.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - mstar,irqs-map-range
+
+additionalProperties: false
+
+examples:
+ - |
+ mst_intc0: interrupt-controller@1f2032d0 {
+ compatible = "mstar,mst-intc";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x1f2032d0 0x30>;
+ mstar,irqs-map-range = <0 63>;
+ };
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: interrupt-controller: Add MStar interrupt controller
2020-09-02 6:33 ` [PATCH v3 2/2] dt-bindings: interrupt-controller: Add MStar interrupt controller Mark-PK Tsai
@ 2020-09-02 6:52 ` Mark-PK Tsai
2020-09-14 20:07 ` [PATCH v3 " Rob Herring
2020-10-11 17:57 ` [tip: irq/core] " tip-bot2 for Mark-PK Tsai
2 siblings, 0 replies; 8+ messages in thread
From: Mark-PK Tsai @ 2020-09-02 6:52 UTC (permalink / raw)
To: mark-pk.tsai, robh
Cc: alix.wu, daniel, devicetree, jason, linux-arm-kernel,
linux-kernel, linux-mediatek, matthias.bgg, maz, robh+dt, tglx,
yj.chiang
Hi,
I've updated the yaml and post it in the patch series v3[1].
But I still keep the vendor specific property mstar,irqs-map-range as I
mentioned in the last reply.
Please review it.
[1] https://lore.kernel.org/lkml/20200902063344.1852-3-mark-pk.tsai@mediatek.com/
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 0/2] Add MStar interrupt controller support
2020-09-02 6:33 [PATCH v3 0/2] Add MStar interrupt controller support Mark-PK Tsai
2020-09-02 6:33 ` [PATCH v3 1/2] irqchip: irq-mst: " Mark-PK Tsai
2020-09-02 6:33 ` [PATCH v3 2/2] dt-bindings: interrupt-controller: Add MStar interrupt controller Mark-PK Tsai
@ 2020-09-13 15:59 ` Marc Zyngier
2 siblings, 0 replies; 8+ messages in thread
From: Marc Zyngier @ 2020-09-13 15:59 UTC (permalink / raw)
To: Mark-PK Tsai
Cc: robh+dt, alix.wu, daniel, devicetree, jason, linux-arm-kernel,
linux-kernel, linux-mediatek, matthias.bgg, tglx, yj.chiang
On Wed, 02 Sep 2020 07:33:42 +0100,
Mark-PK Tsai <mark-pk.tsai@mediatek.com> wrote:
>
> MStar contain a legacy interrupt controller that routes interrupts
> to the GIC. SigmaStar and Mediatek TV SoCs also have this interrupt
> controller IP.
>
> Mark-PK Tsai (2):
> irqchip: irq-mst: Add MStar interrupt controller support
> dt-bindings: interrupt-controller: Add MStar interrupt controller
Once the binding gets approved, I'll queue this for 5.10.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] dt-bindings: interrupt-controller: Add MStar interrupt controller
2020-09-02 6:33 ` [PATCH v3 2/2] dt-bindings: interrupt-controller: Add MStar interrupt controller Mark-PK Tsai
2020-09-02 6:52 ` [PATCH " Mark-PK Tsai
@ 2020-09-14 20:07 ` Rob Herring
2020-10-11 17:57 ` [tip: irq/core] " tip-bot2 for Mark-PK Tsai
2 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-09-14 20:07 UTC (permalink / raw)
To: Mark-PK Tsai
Cc: jason, daniel, yj.chiang, tglx, linux-arm-kernel, matthias.bgg,
maz, linux-mediatek, linux-kernel, alix.wu, devicetree, robh+dt
On Wed, 02 Sep 2020 14:33:44 +0800, Mark-PK Tsai wrote:
> Add binding for MStar interrupt controller.
>
> Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
> ---
> .../interrupt-controller/mstar,mst-intc.yaml | 64 +++++++++++++++++++
> 1 file changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [tip: irq/core] dt-bindings: interrupt-controller: Add MStar interrupt controller
2020-09-02 6:33 ` [PATCH v3 2/2] dt-bindings: interrupt-controller: Add MStar interrupt controller Mark-PK Tsai
2020-09-02 6:52 ` [PATCH " Mark-PK Tsai
2020-09-14 20:07 ` [PATCH v3 " Rob Herring
@ 2020-10-11 17:57 ` tip-bot2 for Mark-PK Tsai
2 siblings, 0 replies; 8+ messages in thread
From: tip-bot2 for Mark-PK Tsai @ 2020-10-11 17:57 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Mark-PK Tsai, Marc Zyngier, Rob Herring, x86, LKML
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 6d8af863b89da6bdce013db2216b432b4016042e
Gitweb: https://git.kernel.org/tip/6d8af863b89da6bdce013db2216b432b4016042e
Author: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
AuthorDate: Wed, 02 Sep 2020 14:33:44 +08:00
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Sat, 10 Oct 2020 12:45:16 +01:00
dt-bindings: interrupt-controller: Add MStar interrupt controller
Add binding for MStar interrupt controller.
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200902063344.1852-3-mark-pk.tsai@mediatek.com
---
Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
new file mode 100644
index 0000000..bbf0f26
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MStar Interrupt Controller
+
+maintainers:
+ - Mark-PK Tsai <mark-pk.tsai@mediatek.com>
+
+description: |+
+ MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy
+ interrupt controllers that routes interrupts to the GIC.
+
+ The HW block exposes a number of interrupt controllers, each
+ can support up to 64 interrupts.
+
+properties:
+ compatible:
+ const: mstar,mst-intc
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 3
+ description: |
+ Use the same format as specified by GIC in arm,gic.yaml.
+
+ reg:
+ maxItems: 1
+
+ mstar,irqs-map-range:
+ description: |
+ The range <start, end> of parent interrupt controller's interrupt
+ lines that are hardwired to mstar interrupt controller.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ minItems: 2
+ maxItems: 2
+
+ mstar,intc-no-eoi:
+ description:
+ Mark this controller has no End Of Interrupt(EOI) implementation.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - mstar,irqs-map-range
+
+additionalProperties: false
+
+examples:
+ - |
+ mst_intc0: interrupt-controller@1f2032d0 {
+ compatible = "mstar,mst-intc";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x1f2032d0 0x30>;
+ mstar,irqs-map-range = <0 63>;
+ };
+...
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [tip: irq/core] irqchip/irq-mst: Add MStar interrupt controller support
2020-09-02 6:33 ` [PATCH v3 1/2] irqchip: irq-mst: " Mark-PK Tsai
@ 2020-10-11 17:57 ` tip-bot2 for Mark-PK Tsai
0 siblings, 0 replies; 8+ messages in thread
From: tip-bot2 for Mark-PK Tsai @ 2020-10-11 17:57 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Mark-PK Tsai, Marc Zyngier, Daniel Palmer, x86, LKML
The following commit has been merged into the irq/core branch of tip:
Commit-ID: ad4c938c92af91302e363b1842c82f1cc4a6c4fd
Gitweb: https://git.kernel.org/tip/ad4c938c92af91302e363b1842c82f1cc4a6c4fd
Author: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
AuthorDate: Wed, 02 Sep 2020 14:33:43 +08:00
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Sat, 10 Oct 2020 12:39:27 +01:00
irqchip/irq-mst: Add MStar interrupt controller support
Add MStar interrupt controller support using hierarchy irq
domain.
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Daniel Palmer <daniel@thingy.jp>
Link: https://lore.kernel.org/r/20200902063344.1852-2-mark-pk.tsai@mediatek.com
---
MAINTAINERS | 7 +-
drivers/irqchip/Kconfig | 8 +-
drivers/irqchip/Makefile | 1 +-
drivers/irqchip/irq-mst-intc.c | 199 ++++++++++++++++++++++++++++++++-
4 files changed, 215 insertions(+)
create mode 100644 drivers/irqchip/irq-mst-intc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index b5cfab0..c1e90fc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11771,6 +11771,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/
T: git git://linuxtv.org/anttip/media_tree.git
F: drivers/media/usb/msi2500/
+MSTAR INTERRUPT CONTROLLER DRIVER
+M: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
+M: Daniel Palmer <daniel@thingy.jp>
+S: Maintained
+F: Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
+F: drivers/irqchip/irq-mst-intc.c
+
MSYSTEMS DISKONCHIP G3 MTD DRIVER
M: Robert Jarzmik <robert.jarzmik@free.fr>
L: linux-mtd@lists.infradead.org
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index bfc9719..c6321a6 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -571,4 +571,12 @@ config LOONGSON_PCH_MSI
help
Support for the Loongson PCH MSI Controller.
+config MST_IRQ
+ bool "MStar Interrupt Controller"
+ default ARCH_MEDIATEK
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Support MStar Interrupt Controller.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 133f9c4..e2688a6 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -111,3 +111,4 @@ obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
+obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
diff --git a/drivers/irqchip/irq-mst-intc.c b/drivers/irqchip/irq-mst-intc.c
new file mode 100644
index 0000000..4be0775
--- /dev/null
+++ b/drivers/irqchip/irq-mst-intc.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
+ */
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define INTC_MASK 0x0
+#define INTC_EOI 0x20
+
+struct mst_intc_chip_data {
+ raw_spinlock_t lock;
+ unsigned int irq_start, nr_irqs;
+ void __iomem *base;
+ bool no_eoi;
+};
+
+static void mst_set_irq(struct irq_data *d, u32 offset)
+{
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
+ u16 val, mask;
+ unsigned long flags;
+
+ mask = 1 << (hwirq % 16);
+ offset += (hwirq / 16) * 4;
+
+ raw_spin_lock_irqsave(&cd->lock, flags);
+ val = readw_relaxed(cd->base + offset) | mask;
+ writew_relaxed(val, cd->base + offset);
+ raw_spin_unlock_irqrestore(&cd->lock, flags);
+}
+
+static void mst_clear_irq(struct irq_data *d, u32 offset)
+{
+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
+ struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
+ u16 val, mask;
+ unsigned long flags;
+
+ mask = 1 << (hwirq % 16);
+ offset += (hwirq / 16) * 4;
+
+ raw_spin_lock_irqsave(&cd->lock, flags);
+ val = readw_relaxed(cd->base + offset) & ~mask;
+ writew_relaxed(val, cd->base + offset);
+ raw_spin_unlock_irqrestore(&cd->lock, flags);
+}
+
+static void mst_intc_mask_irq(struct irq_data *d)
+{
+ mst_set_irq(d, INTC_MASK);
+ irq_chip_mask_parent(d);
+}
+
+static void mst_intc_unmask_irq(struct irq_data *d)
+{
+ mst_clear_irq(d, INTC_MASK);
+ irq_chip_unmask_parent(d);
+}
+
+static void mst_intc_eoi_irq(struct irq_data *d)
+{
+ struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
+
+ if (!cd->no_eoi)
+ mst_set_irq(d, INTC_EOI);
+
+ irq_chip_eoi_parent(d);
+}
+
+static struct irq_chip mst_intc_chip = {
+ .name = "mst-intc",
+ .irq_mask = mst_intc_mask_irq,
+ .irq_unmask = mst_intc_unmask_irq,
+ .irq_eoi = mst_intc_eoi_irq,
+ .irq_get_irqchip_state = irq_chip_get_parent_state,
+ .irq_set_irqchip_state = irq_chip_set_parent_state,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
+ .irq_set_type = irq_chip_set_type_parent,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .flags = IRQCHIP_SET_TYPE_MASKED |
+ IRQCHIP_SKIP_SET_WAKE |
+ IRQCHIP_MASK_ON_SUSPEND,
+};
+
+static int mst_intc_domain_translate(struct irq_domain *d,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ struct mst_intc_chip_data *cd = d->host_data;
+
+ if (is_of_node(fwspec->fwnode)) {
+ if (fwspec->param_count != 3)
+ return -EINVAL;
+
+ /* No PPI should point to this domain */
+ if (fwspec->param[0] != 0)
+ return -EINVAL;
+
+ if (fwspec->param[1] >= cd->nr_irqs)
+ return -EINVAL;
+
+ *hwirq = fwspec->param[1];
+ *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int mst_intc_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *data)
+{
+ int i;
+ irq_hw_number_t hwirq;
+ struct irq_fwspec parent_fwspec, *fwspec = data;
+ struct mst_intc_chip_data *cd = domain->host_data;
+
+ /* Not GIC compliant */
+ if (fwspec->param_count != 3)
+ return -EINVAL;
+
+ /* No PPI should point to this domain */
+ if (fwspec->param[0])
+ return -EINVAL;
+
+ hwirq = fwspec->param[1];
+ for (i = 0; i < nr_irqs; i++)
+ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+ &mst_intc_chip,
+ domain->host_data);
+
+ parent_fwspec = *fwspec;
+ parent_fwspec.fwnode = domain->parent->fwnode;
+ parent_fwspec.param[1] = cd->irq_start + hwirq;
+ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_fwspec);
+}
+
+static const struct irq_domain_ops mst_intc_domain_ops = {
+ .translate = mst_intc_domain_translate,
+ .alloc = mst_intc_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+};
+
+int __init
+mst_intc_of_init(struct device_node *dn, struct device_node *parent)
+{
+ struct irq_domain *domain, *domain_parent;
+ struct mst_intc_chip_data *cd;
+ u32 irq_start, irq_end;
+
+ domain_parent = irq_find_host(parent);
+ if (!domain_parent) {
+ pr_err("mst-intc: interrupt-parent not found\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u32_index(dn, "mstar,irqs-map-range", 0, &irq_start) ||
+ of_property_read_u32_index(dn, "mstar,irqs-map-range", 1, &irq_end))
+ return -EINVAL;
+
+ cd = kzalloc(sizeof(*cd), GFP_KERNEL);
+ if (!cd)
+ return -ENOMEM;
+
+ cd->base = of_iomap(dn, 0);
+ if (!cd->base) {
+ kfree(cd);
+ return -ENOMEM;
+ }
+
+ cd->no_eoi = of_property_read_bool(dn, "mstar,intc-no-eoi");
+ raw_spin_lock_init(&cd->lock);
+ cd->irq_start = irq_start;
+ cd->nr_irqs = irq_end - irq_start + 1;
+ domain = irq_domain_add_hierarchy(domain_parent, 0, cd->nr_irqs, dn,
+ &mst_intc_domain_ops, cd);
+ if (!domain) {
+ iounmap(cd->base);
+ kfree(cd);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+IRQCHIP_DECLARE(mst_intc, "mstar,mst-intc", mst_intc_of_init);
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-10-11 18:01 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-02 6:33 [PATCH v3 0/2] Add MStar interrupt controller support Mark-PK Tsai
2020-09-02 6:33 ` [PATCH v3 1/2] irqchip: irq-mst: " Mark-PK Tsai
2020-10-11 17:57 ` [tip: irq/core] irqchip/irq-mst: " tip-bot2 for Mark-PK Tsai
2020-09-02 6:33 ` [PATCH v3 2/2] dt-bindings: interrupt-controller: Add MStar interrupt controller Mark-PK Tsai
2020-09-02 6:52 ` [PATCH " Mark-PK Tsai
2020-09-14 20:07 ` [PATCH v3 " Rob Herring
2020-10-11 17:57 ` [tip: irq/core] " tip-bot2 for Mark-PK Tsai
2020-09-13 15:59 ` [PATCH v3 0/2] Add MStar interrupt controller support Marc Zyngier
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