From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93465C2BBD1 for ; Mon, 14 Sep 2020 23:23:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3228C20936 for ; Mon, 14 Sep 2020 23:23:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600125838; bh=ikicTrlhRe46VLzjVNAQVlHHEbpBBWVBfJ4BPBf/ZwA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=iKttPxjaa2FBzHvqt2F9OIB3VYdsCgTE6jnGb2YH5v47boWUZWS3T8wQvH5j/EkcB z2RRr+KdxQY5e35Cn/6Arwr8icFdnu8hbgFXeGNORkahVgBpgbvZ6b/NJgeq24SM7e 7CYZ5wGE/vxp5HPVGv6lFzEfsMFq2wQ9g7S5GPVY= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726095AbgINXX4 (ORCPT ); Mon, 14 Sep 2020 19:23:56 -0400 Received: from mail-il1-f194.google.com ([209.85.166.194]:41170 "EHLO mail-il1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725994AbgINXXw (ORCPT ); Mon, 14 Sep 2020 19:23:52 -0400 Received: by mail-il1-f194.google.com with SMTP id f82so1228058ilh.8; Mon, 14 Sep 2020 16:23:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=qrruw9ue02RZKTW0CSzwWkM5yY6NhWe7VBLMc8X9q+M=; b=tZNhpRKZyt871mBR+/7EpMDVGFwV/rGv4CkcAsNYLNz4S7NywGxoTiMrT+nErdJdM2 AdTNbwebW6VKs1C+bA0P1vDklmFvOAx7CXNy7u0z6fToQBLi3A4YtrdfXnH/1b8+KqeN GYQTJog6NNYAL1fhNFj/2K+yDTy0u1UbsL+iM1N80JEQMTe+OOpU+dVCLDrBjI2iZ7cE anUSRmfhwNSVksS+aeoRIV4t7FsMz2VOwo+zdIStrG1Es46SGi1hzv16uNNhbCxdPSOx L//ARwLUo8Nrl9RlWz6hfR+LnSNlJYwmBLvAaRpZr0V2YNR2McF2h4mJLDY4ukDU9i5H u1yQ== X-Gm-Message-State: AOAM532/Znl9bpc+kElHbHJ9Dq1QTUxA3n4TOf5T41YhZHYmpN5U4ljQ PICWdwE8XNNua3d0VzsjNmSbO0/0t2Mu X-Google-Smtp-Source: ABdhPJxJX9TOkRZgJ+qIU6GplErz8LO2MPXNTt9eV9FAc/wZ6hnMsHnbptckLBHpwZ3HKXPs3pblZw== X-Received: by 2002:a92:d08a:: with SMTP id h10mr10004440ilh.109.1600125829929; Mon, 14 Sep 2020 16:23:49 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id w13sm7803443ilg.65.2020.09.14.16.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 16:23:49 -0700 (PDT) Received: (nullmailer pid 468030 invoked by uid 1000); Mon, 14 Sep 2020 23:23:45 -0000 Date: Mon, 14 Sep 2020 17:23:45 -0600 From: Rob Herring To: Yong Wu Cc: Joerg Roedel , Matthias Brugger , Robin Murphy , Will Deacon , Evan Green , Tomasz Figa , linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, youlin.pei@mediatek.com, Nicolas Boichat , anan.sun@mediatek.com, chao.hao@mediatek.com, ming-fan.chen@mediatek.com Subject: Re: [PATCH v2 02/23] dt-bindings: memory: mediatek: Convert SMI to DT schema Message-ID: <20200914232345.GA465583@bogus> References: <20200905080920.13396-1-yong.wu@mediatek.com> <20200905080920.13396-3-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200905080920.13396-3-yong.wu@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Sep 05, 2020 at 04:08:59PM +0800, Yong Wu wrote: > Convert MediaTek SMI to DT schema. > > Signed-off-by: Yong Wu > --- > .../mediatek,smi-common.txt | 49 ---------- > .../mediatek,smi-common.yaml | 96 +++++++++++++++++++ > .../memory-controllers/mediatek,smi-larb.txt | 49 ---------- > .../memory-controllers/mediatek,smi-larb.yaml | 85 ++++++++++++++++ > 4 files changed, 181 insertions(+), 98 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt > create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml > > diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt > deleted file mode 100644 > index b64573680b42..000000000000 > --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt > +++ /dev/null > @@ -1,49 +0,0 @@ > -SMI (Smart Multimedia Interface) Common > - > -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt > - > -Mediatek SMI have two generations of HW architecture, here is the list > -which generation the SoCs use: > -generation 1: mt2701 and mt7623. > -generation 2: mt2712, mt6779, mt8173 and mt8183. > - > -There's slight differences between the two SMI, for generation 2, the > -register which control the iommu port is at each larb's register base. But > -for generation 1, the register is at smi ao base(smi always on register > -base). Besides that, the smi async clock should be prepared and enabled for > -SMI generation 1 to transform the smi clock into emi clock domain, but that is > -not needed for SMI generation 2. > - > -Required properties: > -- compatible : must be one of : > - "mediatek,mt2701-smi-common" > - "mediatek,mt2712-smi-common" > - "mediatek,mt6779-smi-common" > - "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common" > - "mediatek,mt8173-smi-common" > - "mediatek,mt8183-smi-common" > -- reg : the register and size of the SMI block. > -- power-domains : a phandle to the power domain of this local arbiter. > -- clocks : Must contain an entry for each entry in clock-names. > -- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries > - for generation 2 smi HW as follows: > - - "apb" : Advanced Peripheral Bus clock, It's the clock for setting > - the register. > - - "smi" : It's the clock for transfer data and command. > - They may be the same if both source clocks are the same. > - - "async" : asynchronous clock, it help transform the smi clock into the emi > - clock domain, this clock is only needed by generation 1 smi HW. > - and these 2 option clocks for generation 2 smi HW: > - - "gals0": the path0 clock of GALS(Global Async Local Sync). > - - "gals1": the path1 clock of GALS(Global Async Local Sync). > - Here is the list which has this GALS: mt6779 and mt8183. > - > -Example: > - smi_common: smi@14022000 { > - compatible = "mediatek,mt8173-smi-common"; > - reg = <0 0x14022000 0 0x1000>; > - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > - clocks = <&mmsys CLK_MM_SMI_COMMON>, > - <&mmsys CLK_MM_SMI_COMMON>; > - clock-names = "apb", "smi"; > - }; > diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > new file mode 100644 > index 000000000000..781d7b7617d9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > @@ -0,0 +1,96 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SMI (Smart Multimedia Interface) Common > + > +maintainers: > + - Yong Wu > + > +description: |+ > + The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml > + > + MediaTek SMI have two generations of HW architecture, here is the list > + which generation the SoCs use: > + generation 1: mt2701 and mt7623. > + generation 2: mt2712, mt6779, mt8173 and mt8183. > + > + There's slight differences between the two SMI, for generation 2, the > + register which control the iommu port is at each larb's register base. But > + for generation 1, the register is at smi ao base(smi always on register > + base). Besides that, the smi async clock should be prepared and enabled for > + SMI generation 1 to transform the smi clock into emi clock domain, but that is > + not needed for SMI generation 2. > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-smi-common > + - mediatek,mt2712-smi-common > + - mediatek,mt6779-smi-common > + - mediatek,mt7623-smi-common, mediatek,mt2701-smi-common Same problem here. > + - mediatek,mt8173-smi-common > + - mediatek,mt8183-smi-common > + > + reg: > + maxItems: 1 > + > + clocks: > + description: | > + apb and smi are mandatory. the async is only for generation 1 smi HW. > + gals(global async local sync) also is optional, here is the list which > + require gals: mt6779 and mt8183. > + minItems: 2 > + maxItems: 4 > + items: > + - description: apb is Advanced Peripheral Bus clock, It's the clock for > + setting the register. > + - description: smi is the clock for transfer data and command. > + - description: async is asynchronous clock, it help transform the smi clock > + into the emi clock domain. > + - description: gals0 is the path0 clock of gals. > + - description: gals1 is the path1 clock of gals. > + > + clock-names: > + oneOf: > + - items: > + - const: apb > + - const: smi > + - items: > + - const: apb > + - const: smi > + - const: async > + - items: > + - const: apb > + - const: smi > + - const: gals0 > + - const: gals1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + smi_common: smi@14022000 { > + compatible = "mediatek,mt8173-smi-common"; > + reg = <0x14022000 0x1000>; > + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_SMI_COMMON>, > + <&mmsys CLK_MM_SMI_COMMON>; > + clock-names = "apb", "smi"; > + }; > + > diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt > deleted file mode 100644 > index 8f19dfe7d80e..000000000000 > --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt > +++ /dev/null > @@ -1,49 +0,0 @@ > -SMI (Smart Multimedia Interface) Local Arbiter > - > -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt > - > -Required properties: > -- compatible : must be one of : > - "mediatek,mt2701-smi-larb" > - "mediatek,mt2712-smi-larb" > - "mediatek,mt6779-smi-larb" > - "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb" > - "mediatek,mt8173-smi-larb" > - "mediatek,mt8183-smi-larb" > -- reg : the register and size of this local arbiter. > -- mediatek,smi : a phandle to the smi_common node. > -- power-domains : a phandle to the power domain of this local arbiter. > -- clocks : Must contain an entry for each entry in clock-names. > -- clock-names: must contain 2 entries, as follows: > - - "apb" : Advanced Peripheral Bus clock, It's the clock for setting > - the register. > - - "smi" : It's the clock for transfer data and command. > - and this optional clock name: > - - "gals": the clock for GALS(Global Async Local Sync). > - Here is the list which has this GALS: mt8183. > - > -Required property for mt2701, mt2712, mt6779 and mt7623: > -- mediatek,larb-id :the hardware id of this larb. > - > -Example: > - larb1: larb@16010000 { > - compatible = "mediatek,mt8173-smi-larb"; > - reg = <0 0x16010000 0 0x1000>; > - mediatek,smi = <&smi_common>; > - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; > - clocks = <&vdecsys CLK_VDEC_CKEN>, > - <&vdecsys CLK_VDEC_LARB_CKEN>; > - clock-names = "apb", "smi"; > - }; > - > -Example for mt2701: > - larb0: larb@14010000 { > - compatible = "mediatek,mt2701-smi-larb"; > - reg = <0 0x14010000 0 0x1000>; > - mediatek,smi = <&smi_common>; > - mediatek,larb-id = <0>; > - clocks = <&mmsys CLK_MM_SMI_LARB0>, > - <&mmsys CLK_MM_SMI_LARB0>; > - clock-names = "apb", "smi"; > - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; > - }; > diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml > new file mode 100644 > index 000000000000..e8919f280c84 > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SMI (Smart Multimedia Interface) Local Arbiter > + > +maintainers: > + - Yong Wu > + > +description: |+ > + The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-smi-larb > + - mediatek,mt2712-smi-larb > + - mediatek,mt6779-smi-larb > + - mediatek,mt7623-smi-larb, mediatek,mt2701-smi-larb And here. > + - mediatek,mt8173-smi-larb > + - mediatek,mt8183-smi-larb > + > + reg: > + maxItems: 1 > + > + clocks: > + description: | > + apb and smi are mandatory. gals(global async local sync) is optional, > + here is the list which require gals: mt8183. > + minItems: 2 > + maxItems: 3 > + items: > + - description: apb is Advanced Peripheral Bus clock, It's the clock for > + setting the register. > + - description: smi is the clock for transfer data and command. > + - description: the clock for gals. > + > + clock-names: > + oneOf: > + - items: > + - const: apb > + - const: smi > + - items: > + - const: apb > + - const: smi > + - const: gals > + > + power-domains: > + maxItems: 1 > + > + mediatek,smi: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: a phandle to the smi_common node. > + > + mediatek,larb-id: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: the hardware id of this larb. > + Required property for mt2701, mt2712, mt6779 and mt7623. Is there a set of valid values? > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + larb1: larb@16010000 { > + compatible = "mediatek,mt8173-smi-larb"; > + reg = <0x16010000 0x1000>; > + mediatek,smi = <&smi_common>; > + power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; > + clocks = <&vdecsys CLK_VDEC_CKEN>, > + <&vdecsys CLK_VDEC_LARB_CKEN>; > + clock-names = "apb", "smi"; > + }; > + > -- > 2.18.0