From: Borislav Petkov <bp@alien8.de>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, H Peter Anvin <hpa@zytor.com>,
Andy Lutomirski <luto@kernel.org>,
Jean-Philippe Brucker <jean-philippe@linaro.org>,
Christoph Hellwig <hch@infradead.org>,
Peter Zijlstra <peterz@infradead.org>,
David Woodhouse <dwmw2@infradead.org>,
Lu Baolu <baolu.lu@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Tony Luck <tony.luck@intel.com>,
Randy Dunlap <rdunlap@infradead.org>,
Ashok Raj <ashok.raj@intel.com>,
Jacob Jun Pan <jacob.jun.pan@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
Sohil Mehta <sohil.mehta@intel.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
iommu@lists.linux-foundation.org
Subject: Re: [PATCH v8 3/9] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing)
Date: Thu, 17 Sep 2020 09:53:38 +0200 [thread overview]
Message-ID: <20200917075338.GC31960@zn.tnic> (raw)
In-Reply-To: <1600187413-163670-4-git-send-email-fenghua.yu@intel.com>
On Tue, Sep 15, 2020 at 09:30:07AM -0700, Fenghua Yu wrote:
> +Background
> +==========
> +
> +Shared Virtual Addressing (SVA) allows the processor and device to use the
> +same virtual addresses avoiding the need for software to translate virtual
> +addresses to physical addresses. SVA is what PCIe calls Shared Virtual
> +Memory (SVM).
> +
> +In addition to the convenience of using application virtual addresses
> +by the device, it also doesn't require pinning pages for DMA.
> +PCIe Address Translation Services (ATS) along with Page Request Interface
> +(PRI) allow devices to function much the same way as the CPU handling
> +application page-faults. For more information please refer to the PCIe
> +specification Chapter 10: ATS Specification.
> +
> +Use of SVA requires IOMMU support in the platform. IOMMU also is required
> +to support PCIe features ATS and PRI. ATS allows devices to cache
> +translations for virtual addresses. The IOMMU driver uses the mmu_notifier()
> +support to keep the device TLB cache and the CPU cache in sync. PRI allows
> +the device to request paging the virtual address by using the CPU page tables
> +before accessing the address.
That still reads funny, the "the device to request paging the virtual
address" part. Do you mean that per chance here:
"Before the device can access that address, the device uses the PRI in
order to request the virtual address to be paged in into the CPU page
tables."
?
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2020-09-17 7:56 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1600187413-163670-1-git-send-email-fenghua.yu@intel.com>
2020-09-15 16:30 ` [PATCH v8 2/9] iommu/vt-d: Change flags type to unsigned int in binding mm Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Fenghua Yu
2020-09-15 16:30 ` [PATCH v8 4/9] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Fenghua Yu
2020-09-15 16:30 ` [PATCH v8 5/9] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] x86/fpu/xstate: Add supervisor PASID state for ENQCMD tip-bot2 for Yu-cheng Yu
2020-09-15 16:30 ` [PATCH v8 6/9] x86/msr-index: Define IA32_PASID MSR Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] x86/msr-index: Define an " tip-bot2 for Fenghua Yu
2020-09-15 16:30 ` [PATCH v8 9/9] x86/mmu: Allocate/free PASID Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] x86/mmu: Allocate/free a PASID tip-bot2 for Fenghua Yu
2021-05-29 9:17 ` [PATCH] x86/cpufeatures: Force disable X86_FEATURE_ENQCMD and remove update_pasid() Thomas Gleixner
2021-05-31 8:43 ` Borislav Petkov
2021-05-31 10:16 ` Thomas Gleixner
2021-06-02 20:37 ` Luck, Tony
2021-06-03 17:31 ` Andy Lutomirski
2021-06-09 17:32 ` Luck, Tony
2021-06-09 23:34 ` Andy Lutomirski
2021-06-25 15:46 ` Luck, Tony
2021-06-02 10:14 ` Borislav Petkov
2021-06-02 10:20 ` Thomas Gleixner
2021-06-03 11:20 ` Vinod Koul
2021-06-03 11:42 ` Borislav Petkov
2021-06-03 12:47 ` Vinod Koul
2021-06-03 14:33 ` Borislav Petkov
2021-06-02 19:49 ` [tip: x86/urgent] " tip-bot2 for Thomas Gleixner
2021-06-03 14:38 ` tip-bot2 for Thomas Gleixner
2020-09-16 8:06 ` [PATCH v8 0/9] x86: tag application address space for devices Joerg Roedel
2020-09-17 23:53 ` Fenghua Yu
[not found] ` <1600187413-163670-4-git-send-email-fenghua.yu@intel.com>
2020-09-17 7:53 ` Borislav Petkov [this message]
2020-09-17 14:56 ` [PATCH v8 3/9] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing) Raj, Ashok
2020-09-17 17:18 ` Borislav Petkov
2020-09-17 17:22 ` Raj, Ashok
2020-09-17 17:30 ` Borislav Petkov
2020-09-18 16:22 ` Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Ashok Raj
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