From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB154C433E2 for ; Thu, 17 Sep 2020 16:42:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6ACF3206B6 for ; Thu, 17 Sep 2020 16:42:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728555AbgIQQhs (ORCPT ); Thu, 17 Sep 2020 12:37:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:44906 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728513AbgIQQfn (ORCPT ); Thu, 17 Sep 2020 12:35:43 -0400 Received: from gaia (unknown [31.124.44.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0D54420672; Thu, 17 Sep 2020 16:35:39 +0000 (UTC) Date: Thu, 17 Sep 2020 17:35:37 +0100 From: Catalin Marinas To: Andrey Konovalov Cc: Dmitry Vyukov , Vincenzo Frascino , kasan-dev@googlegroups.com, Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Elena Petrova , Branislav Rankov , Kevin Brodsky , Will Deacon , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 25/37] arm64: kasan: Enable in-kernel MTE Message-ID: <20200917163536.GE10662@gaia> References: <859111cf1d862ce26f094cf14511461c372e5bbc.1600204505.git.andreyknvl@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <859111cf1d862ce26f094cf14511461c372e5bbc.1600204505.git.andreyknvl@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 15, 2020 at 11:16:07PM +0200, Andrey Konovalov wrote: > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 23c326a06b2d..5ba7ac5e9c77 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -427,6 +427,10 @@ SYM_FUNC_START(__cpu_setup) > */ > mov_q x5, MAIR_EL1_SET > #ifdef CONFIG_ARM64_MTE > + mte_present .req x20 > + > + mov mte_present, #0 > + > /* > * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported > * (ID_AA64PFR1_EL1[11:8] > 1). > @@ -447,6 +451,8 @@ SYM_FUNC_START(__cpu_setup) > /* clear any pending tag check faults in TFSR*_EL1 */ > msr_s SYS_TFSR_EL1, xzr > msr_s SYS_TFSRE0_EL1, xzr > + > + mov mte_present, #1 > 1: > #endif > msr mair_el1, x5 > @@ -485,6 +491,13 @@ SYM_FUNC_START(__cpu_setup) > orr x10, x10, #TCR_HA // hardware Access flag update > 1: > #endif /* CONFIG_ARM64_HW_AFDBM */ > +#ifdef CONFIG_ARM64_MTE > + /* Update TCR_EL1 if MTE is supported (ID_AA64PFR1_EL1[11:8] > 1) */ > + cbz mte_present, 1f > + orr x10, x10, #SYS_TCR_EL1_TCMA1 > +1: > + .unreq mte_present > +#endif > msr tcr_el1, x10 > /* > * Prepare SCTLR I'd keep this simpler, no branches or #ifdefs (you can still add the .req if you want): diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 23c326a06b2d..a35344754081 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -426,6 +426,7 @@ SYM_FUNC_START(__cpu_setup) * Memory region attributes */ mov_q x5, MAIR_EL1_SET + mov x8, #0 #ifdef CONFIG_ARM64_MTE /* * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported @@ -447,6 +448,9 @@ SYM_FUNC_START(__cpu_setup) /* clear any pending tag check faults in TFSR*_EL1 */ msr_s SYS_TFSR_EL1, xzr msr_s SYS_TFSRE0_EL1, xzr + + /* set the TCR_EL1 bits */ + orr x8, x8, #SYS_TCR_EL1_TCMA1 1: #endif msr mair_el1, x5 @@ -457,6 +461,7 @@ SYM_FUNC_START(__cpu_setup) mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS + orr x10, x10, x8 tcr_clear_errata_bits x10, x9, x5 #ifdef CONFIG_ARM64_VA_BITS_52 -- Catalin