From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8519C43461 for ; Thu, 17 Sep 2020 17:09:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A4DA6221E7 for ; Thu, 17 Sep 2020 17:09:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727151AbgIQRIo (ORCPT ); Thu, 17 Sep 2020 13:08:44 -0400 Received: from mail.kernel.org ([198.145.29.99]:52940 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727052AbgIQRIK (ORCPT ); Thu, 17 Sep 2020 13:08:10 -0400 Received: from gaia (unknown [31.124.44.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 18D84206CA; Thu, 17 Sep 2020 17:07:54 +0000 (UTC) Date: Thu, 17 Sep 2020 18:07:52 +0100 From: Catalin Marinas To: Vincenzo Frascino Cc: Andrey Konovalov , Dmitry Vyukov , kasan-dev@googlegroups.com, Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Elena Petrova , Branislav Rankov , Kevin Brodsky , Will Deacon , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 22/37] arm64: mte: Add in-kernel MTE helpers Message-ID: <20200917170752.GS10662@gaia> References: <4ac1ed624dd1b0851d8cf2861b4f4aac4d2dbc83.1600204505.git.andreyknvl@google.com> <20200917134653.GB10662@gaia> <9ef0a773-71f0-c1d6-b67e-ccf7d8bcbbe6@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9ef0a773-71f0-c1d6-b67e-ccf7d8bcbbe6@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 17, 2020 at 05:17:00PM +0100, Vincenzo Frascino wrote: > On 9/17/20 2:46 PM, Catalin Marinas wrote: > >> diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c > >> index 52a0638ed967..e238ffde2679 100644 > >> --- a/arch/arm64/kernel/mte.c > >> +++ b/arch/arm64/kernel/mte.c > >> @@ -72,6 +74,52 @@ int memcmp_pages(struct page *page1, struct page *page2) > >> return ret; > >> } > >> > >> +u8 mte_get_mem_tag(void *addr) > >> +{ > >> + if (system_supports_mte()) > >> + asm volatile(ALTERNATIVE("ldr %0, [%0]", > >> + __MTE_PREAMBLE "ldg %0, [%0]", > >> + ARM64_MTE) > >> + : "+r" (addr)); > > This doesn't do what you think it does. LDG indeed reads the tag from > > memory but LDR loads the actual data at that address. Instead of the > > first LDR, you may want something like "mov %0, #0xf << 56" (and use > > some macros to avoid the hard-coded 56). > > > > Seems I can't encode a shift of 56 neither in mov nor in orr. I propose to > replace both with an and of the address with itself. > This should not change anything. Then use a NOP. -- Catalin