From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A618DC43466 for ; Mon, 21 Sep 2020 13:44:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5437B20B1F for ; Mon, 21 Sep 2020 13:44:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600695850; bh=MWMbTeQXgsSrcke9ClQCdlLOJJmrD/yGsUoAPqwbB1c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=j8HdONs9T4GseoWxcTrHAbXz8X2J93wTmSpVmEz4UWO2PEzaL0WumhZbhTrx+aW+P 26oQHf6rsxJ2MtZX8Q6a2AkvLGrW5DX087hIKQ6f8PSwelLCQ5U+qfODS3bWIYFdFe TpyWFw4BZ/VzdzEm+CtpZgidW609HQtck4ir/Rws= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727360AbgIUNoJ (ORCPT ); Mon, 21 Sep 2020 09:44:09 -0400 Received: from mail.kernel.org ([198.145.29.99]:56670 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726830AbgIUNoF (ORCPT ); Mon, 21 Sep 2020 09:44:05 -0400 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B269220888; Mon, 21 Sep 2020 13:44:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600695844; bh=MWMbTeQXgsSrcke9ClQCdlLOJJmrD/yGsUoAPqwbB1c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=glGVInNpxoukIMGGUaJ7ob5aWbbmyaI3ZQ0mPg5DXA71utsj8OfFA/4d6AD47Gn3h ee1v1lAsMEkPgVJWp0qDUrlMre9NV6ogj4CXNgd+OVS7lNP+AnmAXrmlOg8xlOo6sM FLIUhvOeKaR2/dW/EY0bbeqkzOOHXbaDFSykNsoM= Date: Mon, 21 Sep 2020 14:43:58 +0100 From: Will Deacon To: Alexandru Elisei Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, maz@kernel.org, catalin.marinas@arm.com, swboyd@chromium.org, sumit.garg@linaro.org, Julien Thierry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Julien Thierry Subject: Re: [PATCH v6 2/7] arm64: perf: Avoid PMXEV* indirection Message-ID: <20200921134357.GL2139@willie-the-truck> References: <20200819133419.526889-1-alexandru.elisei@arm.com> <20200819133419.526889-3-alexandru.elisei@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200819133419.526889-3-alexandru.elisei@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 19, 2020 at 02:34:14PM +0100, Alexandru Elisei wrote: > From: Mark Rutland > > Currently we access the counter registers and their respective type > registers indirectly. This requires us to write to PMSELR, issue an ISB, > then access the relevant PMXEV* registers. > > This is unfortunate, because: > > * Under virtualization, accessing one register requires two traps to > the hypervisor, even though we could access the register directly with > a single trap. > > * We have to issue an ISB which we could otherwise avoid the cost of. > > * When we use NMIs, the NMI handler will have to save/restore the select > register in case the code it preempted was attempting to access a > counter or its type register. > > We can avoid these issues by directly accessing the relevant registers. > This patch adds helpers to do so. > > In armv8pmu_enable_event() we still need the ISB to prevent the PE from > reordering the write to PMINTENSET_EL1 register. If the interrupt is > enabled before we disable the counter and the new event is configured, > we might get an interrupt triggered by the previously programmed event > overflowing, but which we wrongly attribute to the event that we are > enabling. > > In the process, remove the comment that refers to the ARMv7 PMU. > > Cc: Julien Thierry > Cc: Will Deacon > Cc: Peter Zijlstra > Cc: Ingo Molnar > Cc: Arnaldo Carvalho de Melo > Cc: Alexander Shishkin > Cc: Jiri Olsa > Cc: Namhyung Kim > Cc: Catalin Marinas > Signed-off-by: Mark Rutland > [Julien T.: Don't inline read/write functions to avoid big code-size > increase, remove unused read_pmevtypern function, > fix counter index issue.] > Signed-off-by: Julien Thierry > [Removed comment, removed trailing semicolons in macros, added ISB] nit: but it's customary to prefix these with your name, so it's easy to figure out who made changes (like Julien did above). (similar comment for other patches in this series) > @@ -620,9 +686,14 @@ static void armv8pmu_enable_event(struct perf_event *event) > * Disable counter > */ > armv8pmu_disable_event_counter(event); > + /* > + * Make sure the effects of disabling the counter are visible before we > + * start configuring the event. > + */ > + isb(); With the isb() added by patch 1, why don't we just make these implicit in armv8_{enable,disable}_event_counter() ? Will