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a=rsa-sha256; c=simple/simple; d=aosc.io; s=default; t=1600822892; bh=lGGQP3uOC1+o8heVDFTEK+4+dQ+oafICIec/tyjv7zw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E7yJxjFHXxqqs1Xo60G0fc3N9pMkkocPvrm6ALdwUlZM4E6KVum7vbYjZwo6fHby+ rIEFsfHv6DeWQUtKhMSdgLZGeqYoKUY0AmkDVwhr61jEsopey+OFzT4lFqgsIOtWIO P3Y68Dode0MukneNxGPOeY3VsJPWAG6RWL4i4AvM= From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [PATCH 4/7] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for 8-bit parallel CSI Date: Wed, 23 Sep 2020 09:01:21 +0800 Message-Id: <20200923010122.148661-1-icenowy@aosc.io> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200923005709.147966-1-icenowy@aosc.io> References: <20200923005709.147966-1-icenowy@aosc.io> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: A448241009 X-Spamd-Result: default: False [6.40 / 20.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; R_DKIM_ALLOW(0.00)[aosc.io:s=default]; RECEIVED_SPAMHAUS_PBL(0.00)[59.41.160.155:received]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; R_MISSING_CHARSET(2.50)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; TAGGED_RCPT(0.00)[dt]; MIME_GOOD(-0.10)[text/plain]; BROKEN_CONTENT_TYPE(1.50)[]; R_SPF_SOFTFAIL(0.00)[~all:c]; DMARC_NA(0.00)[aosc.io]; ML_SERVERS(-3.10)[213.133.102.83]; DKIM_TRACE(0.00)[aosc.io:+]; RCPT_COUNT_SEVEN(0.00)[8]; MID_CONTAINS_FROM(1.00)[]; RCVD_NO_TLS_LAST(0.10)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:24940, ipnet:213.133.96.0/19, country:DE]; RCVD_COUNT_TWO(0.00)[2]; SUSPICIOUS_RECIPS(1.50)[]; HFILTER_HELO_BAREIP(3.00)[213.133.102.83,1] X-Rspamd-Server: mail20.mymailcheap.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The CSI1 controller of V3/V3s/S3/S3L SoCs is used for parallel CSI. As we're going to add support for Pine64 SCC board, which uses 8-bit parallel CSI (and the MCLK output), add the pinctrl node of 8-bit CSI and MCLK to the DTSI file. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 3e079973672d..19fba1a9115b 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -312,6 +312,20 @@ pio: pinctrl@1c20800 { interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + csi1_8bit_pins: csi1-8bit-pins { + pins = "PE0", "PE2", "PE3", "PE8", "PE9", + "PE10", "PE11", "PE12", "PE13", "PE14", + "PE15"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi1_mclk_pin: csi1-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + i2c0_pins: i2c0-pins { pins = "PB6", "PB7"; function = "i2c0"; -- 2.27.0