From: Yuichi Ito <ito-yuichi@fujitsu.com>
To: maz@kernel.org, sumit.garg@linaro.org, tglx@linutronix.de,
jason@lakedaemon.net, catalin.marinas@arm.com, will@kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Yuichi Ito <ito-yuichi@fujitsu.com>
Subject: [PATCH 2/2] Register IPI_CPU_CRASH_STOP IPI as pseudo-NMI
Date: Thu, 24 Sep 2020 13:42:36 +0900 [thread overview]
Message-ID: <20200924044236.1245808-3-ito-yuichi@fujitsu.com> (raw)
In-Reply-To: <20200924044236.1245808-1-ito-yuichi@fujitsu.com>
Register IPI_CPU_CRASH_STOP IPI as pseudo-NMI.
For systems that do not support pseudo-NMI, register as a normal IRQ.
Signed-off-by: Yuichi Ito <ito-yuichi@fujitsu.com>
---
arch/arm64/kernel/smp.c | 39 +++++++++++++++++++++++++++++++--------
1 file changed, 31 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index b6bde2675ccc..d929dd7221ff 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -79,6 +79,8 @@ enum ipi_msg_type {
static int ipi_irq_base __read_mostly;
static int nr_ipi __read_mostly = NR_IPI;
static struct irq_desc *ipi_desc[NR_IPI] __read_mostly;
+static int ipi_crash_stop = -1;
+static int ipi_crash_stop_enable_nmi;
static void ipi_setup(int cpu);
static void ipi_teardown(int cpu);
@@ -954,8 +956,16 @@ static void ipi_setup(int cpu)
if (WARN_ON_ONCE(!ipi_irq_base))
return;
- for (i = 0; i < nr_ipi; i++)
- enable_percpu_irq(ipi_irq_base + i, 0);
+ for (i = 0; i < nr_ipi; i++) {
+ if (ipi_irq_base + i == ipi_crash_stop) {
+ if (!prepare_percpu_nmi(ipi_irq_base + i)) {
+ enable_percpu_nmi(ipi_irq_base + i, 0);
+ ipi_crash_stop_enable_nmi = 1;
+ } else
+ pr_crit("CPU%u: IPI_CPU_CRASH_STOP cannot be enabled NMI.\n", cpu);
+ } else
+ enable_percpu_irq(ipi_irq_base + i, 0);
+ }
}
static void ipi_teardown(int cpu)
@@ -965,23 +975,37 @@ static void ipi_teardown(int cpu)
if (WARN_ON_ONCE(!ipi_irq_base))
return;
- for (i = 0; i < nr_ipi; i++)
- disable_percpu_irq(ipi_irq_base + i);
+ for (i = 0; i < nr_ipi; i++) {
+ if (ipi_irq_base + i == ipi_crash_stop) {
+ if (ipi_crash_stop_enable_nmi) {
+ disable_percpu_nmi(ipi_irq_base + i);
+ teardown_percpu_nmi(ipi_irq_base + i);
+ }
+ } else
+ disable_percpu_irq(ipi_irq_base + i);
+ }
}
void __init set_smp_ipi_range(int ipi_base, int n)
{
- int i;
+ int i, ret;
WARN_ON(n < NR_IPI);
nr_ipi = min(n, NR_IPI);
+ ret = request_percpu_nmi(ipi_base + IPI_CPU_CRASH_STOP,
+ ipi_handler, "IPI", &cpu_number);
+ if (!ret)
+ ipi_crash_stop = ipi_base + IPI_CPU_CRASH_STOP;
+
for (i = 0; i < nr_ipi; i++) {
int err;
- err = request_percpu_irq(ipi_base + i, ipi_handler,
- "IPI", &cpu_number);
- WARN_ON(err);
+ if (ipi_base + i != ipi_crash_stop) {
+ err = request_percpu_irq(ipi_base + i, ipi_handler,
+ "IPI", &cpu_number);
+ WARN_ON(err);
+ }
ipi_desc[i] = irq_to_desc(ipi_base + i);
irq_set_status_flags(ipi_base + i, IRQ_HIDDEN);
--
2.25.1
next prev parent reply other threads:[~2020-09-24 4:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-24 4:42 [PATCH 0/2] Enable support IPI_CPU_CRASH_STOP to be pseudo-NMI Yuichi Ito
2020-09-24 4:42 ` [PATCH 1/2] irqchip/gic-v3: Enable support for SGIs to act as NMIs Yuichi Ito
2020-09-24 4:42 ` Yuichi Ito [this message]
2020-09-28 2:43 ` [PATCH 0/2] Enable support IPI_CPU_CRASH_STOP to be pseudo-NMI ito-yuichi
2020-09-28 8:59 ` Marc Zyngier
2020-09-29 5:50 ` ito-yuichi
2020-09-29 10:54 ` Marc Zyngier
2020-09-30 8:51 ` ito-yuichi
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