From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6C1FC4741F for ; Mon, 28 Sep 2020 11:44:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B24DC2080C for ; Mon, 28 Sep 2020 11:44:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726691AbgI1Lo7 (ORCPT ); Mon, 28 Sep 2020 07:44:59 -0400 Received: from foss.arm.com ([217.140.110.172]:50024 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726625AbgI1Lo5 (ORCPT ); Mon, 28 Sep 2020 07:44:57 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A387231B; Mon, 28 Sep 2020 04:44:56 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1F0D23F6CF; Mon, 28 Sep 2020 04:44:55 -0700 (PDT) From: Sudeep Holla To: Jassi Brar , Jassi Brar , Viresh Kumar , ALKML , DTML , LKML Cc: Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: [PATCH 2/4] dt-bindings: mailbox: add doorbell support to ARM MHU Date: Mon, 28 Sep 2020 12:44:43 +0100 Message-Id: <20200928114445.19689-3-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200928114445.19689-1-sudeep.holla@arm.com> References: <20200928114445.19689-1-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ARM MHU's reference manual states following: "The MHU drives the signal using a 32-bit register, with all 32 bits logically ORed together. The MHU provides a set of registers to enable software to set, clear, and check the status of each of the bits of this register independently. The use of 32 bits for each interrupt line enables software to provide more information about the source of the interrupt. For example, each bit of the register can be associated with a type of event that can contribute to raising the interrupt." This patch thus extends the MHU controller's DT binding to add support for doorbell mode. Though the same MHU hardware controller is used in the two modes, A new compatible string is added here to represent the combination of the MHU hardware and the firmware sitting on the other side (which expects each bit to represent a different signal now). Reviewed-by: Rob Herring Acked-by: Arnd Bergmann Co-developed-by: Viresh Kumar Signed-off-by: Viresh Kumar Signed-off-by: Sudeep Holla --- .../devicetree/bindings/mailbox/arm,mhu.yaml | 60 +++++++++++++++++-- 1 file changed, 54 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml index 2c8df7979c22..d43791a2dde7 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -18,20 +18,40 @@ description: | remote clears it after having read the data. The last channel is specified to be a 'Secure' resource, hence can't be used by Linux running NS. + The MHU hardware also allows operations in doorbell mode. The MHU drives the + interrupt signal using a 32-bit register, with all 32-bits logically ORed + together. It provides a set of registers to enable software to set, clear and + check the status of each of the bits of this register independently. The use + of 32 bits per interrupt line enables software to provide more information + about the source of the interrupt. For example, each bit of the register can + be associated with a type of event that can contribute to raising the + interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote + processor. + # We need a select here so we don't match all nodes with 'arm,primecell' select: properties: compatible: contains: - const: arm,mhu + enum: + - arm,mhu + - arm,mhu-doorbell required: - compatible properties: compatible: - items: - - const: arm,mhu - - const: arm,primecell + oneOf: + - description: Data transfer mode + items: + - const: arm,mhu + - const: arm,primecell + + - description: Doorbell mode + items: + - const: arm,mhu-doorbell + - const: arm,primecell + reg: maxItems: 1 @@ -51,8 +71,11 @@ description: | - const: apb_pclk '#mbox-cells': - description: Index of the channel. - const: 1 + description: | + Set to 1 in data transfer mode and represents index of the channel. + Set to 2 in doorbell mode and represents index of the channel and doorbell + number. + enum: [ 1, 2 ] required: - compatible @@ -63,6 +86,7 @@ description: | additionalProperties: false examples: + # Data transfer mode. - | soc { #address-cells = <2>; @@ -85,3 +109,27 @@ additionalProperties: false mboxes = <&mhuA 1>; /* HP-NonSecure */ }; }; + + # Doorbell mode. + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mhuB: mailbox@2b2f0000 { + #mbox-cells = <2>; + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0 0x2b2f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client_scpi: scpi@2f000000 { + compatible = "arm,scpi"; + reg = <0 0x2f000000 0 0x200>; + mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */ + }; + }; -- 2.17.1