* [PATCH v4 00/20] add support for Hisilicon SD5203 SoC
@ 2020-09-28 15:13 Zhen Lei
2020-09-28 15:13 ` [PATCH v4 01/20] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Zhen Lei
` (19 more replies)
0 siblings, 20 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
v3 --> v4:
1. remove unexpected "\ No newline at end of file" of each new file.
2. discard the subdirectory "hi3620" and "hipxx", all files in the two
directories are moved to the parent directory.
3. add two spaces for the below cases:
- items:
- const: hisilicon,sysctrl. //add two spaces
4. only list the compatible of boards in hisilicon.yaml, that is:
1) a compatible of one board
2) a compatible of one board + a compatible of one SoC
5. other trival fixes are not mentioned.
v2 --> v3:
1. Convert hisilicon.txt to hisilicon.yaml. Because there are many kinds
of Hisilicon controllers in it, so split each of them into a separate
file first. Then I convert all of them to DT schema format, and also
convert the other files in directory "../bindings/arm/hisilicon/".
2. Add Patch 1: remove a unused compatible name in hip01-ca9x2.dts
This error is detected by hisilicon.yaml.
The merge window of 5.10 is narrow now, so please review Patch 1-7 first.
v1 --> v2:
1. add binding for SD5203 SoC, Patch 1
2. select DW_APB_ICTL instead of HISILICON_SD5203_VIC in Patch 2.
Meanwhile, change the compatible of interrupt-controller to "snps,dw-apb-ictl" in Patch 4.
3. Fix the errors detected by dtbs_check. For example: add "reg" for cpu node, use lowercase a-f
to describe address, add "baudclk" for "snps,dw-apb-uart".
v1:
Add SD5203 SoC config option and devicetree file, also enable its debug UART.
Kefeng Wang (3):
ARM: hisi: add support for SD5203 SoC
ARM: debug: add UART early console support for SD5203
ARM: dts: add SD5203 dts
Zhen Lei (17):
dt-bindings: arm: hisilicon: split the dt-bindings of each controller
into a separate file
dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to
json-schema
dt-bindings: arm: hisilicon: add binding for SD5203 SoC
dt-bindings: arm: hisilicon: convert system controller bindings to
json-schema
dt-bindings: arm: hisilicon: convert hisilicon,peri-subctrl bindings
to json-schema
dt-bindings: arm: hisilicon: convert hisilicon,pcie-sas-subctrl
bindings to json-schema
dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl bindings to
json-schema
dt-bindings: arm: hisilicon: convert hisilicon,pctrl bindings to
json-schema
dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl
bindings to json-schema
dt-bindings: arm: hisilicon: convert hisilicon,dsa-subctrl bindings to
json-schema
dt-bindings: arm: hisilicon: convert hisilicon,hip04-fabric bindings
to json-schema
dt-bindings: arm: hisilicon: convert hisilicon,hip04-bootwrapper
bindings to json-schema
dt-bindings: arm: hisilicon: convert hisilicon,hi6220-aoctrl bindings
to json-schema
dt-bindings: arm: hisilicon: convert hisilicon,hi6220-mediactrl
bindings to json-schema
dt-bindings: arm: hisilicon: convert hisilicon,hi6220-pmctrl bindings
to json-schema
dt-bindings: arm: hisilicon: convert hisilicon,hi6220-sramctrl
bindings to json-schema
dt-bindings: arm: hisilicon: convert LPC controller bindings to
json-schema
.../hisilicon/controller/hisilicon,cpuctrl.yaml | 28 ++
.../controller/hisilicon,dsa-subctrl.yaml | 37 +++
.../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 +++
.../controller/hisilicon,hi6220-aoctrl.yaml | 42 +++
.../controller/hisilicon,hi6220-mediactrl.yaml | 42 +++
.../controller/hisilicon,hi6220-pmctrl.yaml | 42 +++
.../controller/hisilicon,hi6220-sramctrl.yaml | 38 +++
.../controller/hisilicon,hip04-bootwrapper.yaml | 32 +++
.../controller/hisilicon,hip04-fabric.yaml | 26 ++
.../controller/hisilicon,pcie-sas-subctrl.yaml | 37 +++
.../arm/hisilicon/controller/hisilicon,pctrl.yaml | 34 +++
.../controller/hisilicon,peri-subctrl.yaml | 34 +++
.../hisilicon/controller/hisilicon,sysctrl.yaml | 115 ++++++++
.../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 -
.../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ---
.../arm/hisilicon/hisilicon-low-pin-count.yaml | 61 ++++
.../bindings/arm/hisilicon/hisilicon.txt | 319 ---------------------
.../bindings/arm/hisilicon/hisilicon.yaml | 66 +++++
arch/arm/Kconfig.debug | 11 +-
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sd5203.dts | 96 +++++++
arch/arm/mach-hisi/Kconfig | 16 +-
22 files changed, 801 insertions(+), 369 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
create mode 100644 arch/arm/boot/dts/sd5203.dts
--
1.8.3
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 01/20] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 19:05 ` Rob Herring
2020-09-28 15:13 ` [PATCH v4 02/20] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema Zhen Lei
` (18 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Split the devicetree bindings of each Hisilicon controller from
hisilicon.txt into a separate file, the file name is the compatible name
attach the .txt file name extension.
All Hi6220 dedicated controllers are grouped into subdirectory "hi3620".
All HiPxx dedicated controllers are grouped into subdirectory "hipxx"
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 +
.../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 ++
.../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ++
.../controller/hisilicon,hi6220-aoctrl.txt | 18 ++
.../controller/hisilicon,hi6220-mediactrl.txt | 18 ++
.../controller/hisilicon,hi6220-pmctrl.txt | 18 ++
.../controller/hisilicon,hi6220-sramctrl.txt | 16 ++
.../controller/hisilicon,hi6220-sysctrl.txt | 19 ++
.../controller/hisilicon,hip01-sysctrl.txt | 19 ++
.../controller/hisilicon,hip04-bootwrapper.txt | 9 +
.../controller/hisilicon,hip04-fabric.txt | 5 +
.../controller/hisilicon,pcie-sas-subctrl.txt | 15 ++
.../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 +
.../controller/hisilicon,peri-subctrl.txt | 16 ++
.../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ++
.../bindings/arm/hisilicon/hisilicon.txt | 262 ---------------------
16 files changed, 235 insertions(+), 262 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
new file mode 100644
index 000000000000000..ceffac537671668
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
@@ -0,0 +1,8 @@
+Hisilicon CPU controller
+
+Required properties:
+- compatible : "hisilicon,cpuctrl"
+- reg : Register address and size
+
+The clock registers and power registers of secondary cores are defined
+in CPU controller, especially in HIX5HD2 SoC.
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
new file mode 100644
index 000000000000000..4d1c6abf03f6f97
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
@@ -0,0 +1,15 @@
+Hisilicon HiP05/HiP06 DSA sub system controller
+
+Required properties:
+- compatible : "hisilicon,dsa-subctrl", "syscon";
+- reg : Register address and size
+
+The DSA sub system controller is shared by peripheral controllers in
+HiP05 or HiP06 Soc to implement some basic configurations.
+
+Example:
+ /* for HiP05 dsa sub system */
+ pcie_sas: system_controller@a0000000 {
+ compatible = "hisilicon,dsa-subctrl", "syscon";
+ reg = <0xa0000000 0x10000>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
new file mode 100644
index 000000000000000..0d5282f4670658d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
@@ -0,0 +1,21 @@
+Hisilicon Hi3798CV200 Peripheral Controller
+
+The Hi3798CV200 Peripheral Controller controls peripherals, queries
+their status, and configures some functions of peripherals.
+
+Required properties:
+- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
+ and "simple-mfd".
+- reg: Register address and size of Peripheral Controller.
+- #address-cells: Should be 1.
+- #size-cells: Should be 1.
+
+Examples:
+
+ perictrl: peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
+ "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt
new file mode 100644
index 000000000000000..5a723c1d45f4a17
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt
@@ -0,0 +1,18 @@
+Hisilicon Hi6220 Power Always ON domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-aoctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power always
+on domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ ao_ctrl: ao_ctrl@f7800000 {
+ compatible = "hisilicon,hi6220-aoctrl", "syscon";
+ reg = <0x0 0xf7800000 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt
new file mode 100644
index 000000000000000..dcfdcbcb6455771
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt
@@ -0,0 +1,18 @@
+Hisilicon Hi6220 Media domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-mediactrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the multimedia
+domain(e.g. codec, G3D ...) for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ media_ctrl: media_ctrl@f4410000 {
+ compatible = "hisilicon,hi6220-mediactrl", "syscon";
+ reg = <0x0 0xf4410000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt
new file mode 100644
index 000000000000000..972842f07b5a2ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt
@@ -0,0 +1,18 @@
+Hisilicon Hi6220 Power Management domain controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-pmctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, some clock registers are define
+ under this controller and this property must be present.
+
+Hisilicon designs this system controller to control the power management
+domain for mobile platform.
+
+Example:
+ /*for Hi6220*/
+ pm_ctrl: pm_ctrl@f7032000 {
+ compatible = "hisilicon,hi6220-pmctrl", "syscon";
+ reg = <0x0 0xf7032000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt
new file mode 100644
index 000000000000000..086b7acccc5edc4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt
@@ -0,0 +1,16 @@
+Hisilicon Hi6220 SRAM controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-sramctrl", "syscon"
+- reg : Register address and size
+
+Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
+SRAM banks for power management, modem, security, etc. Further, use "syscon"
+managing the common sram which can be shared by multiple modules.
+
+Example:
+ /*for Hi6220*/
+ sram: sram@fff80000 {
+ compatible = "hisilicon,hi6220-sramctrl", "syscon";
+ reg = <0x0 0xfff80000 0x0 0x12000>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
new file mode 100644
index 000000000000000..07e318eda254f52
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
@@ -0,0 +1,19 @@
+Hisilicon Hi6220 system controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-sysctrl"
+- reg : Register address and size
+- #clock-cells: should be set to 1, many clock registers are defined
+ under this controller and this property must be present.
+
+Hisilicon designs this controller as one of the system controllers,
+its main functions are the same as Hisilicon system controller, but
+the register offset of some core modules are different.
+
+Example:
+ /*for Hi6220*/
+ sys_ctrl: sys_ctrl@f7030000 {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf7030000 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
new file mode 100644
index 000000000000000..db2dfdce799db91
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
@@ -0,0 +1,19 @@
+Hisilicon HiP01 system controller
+
+Required properties:
+- compatible : "hisilicon,hip01-sysctrl"
+- reg : Register address and size
+
+The HiP01 system controller is mostly compatible with hisilicon
+system controller,but it has some specific control registers for
+HIP01 SoC family, such as slave core boot, and also some same
+registers located at different offset.
+
+Example:
+
+ /* for hip01-ca9x2 */
+ sysctrl: system-controller@10000000 {
+ compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
+ reg = <0x10000000 0x1000>;
+ reboot-offset = <0x4>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt
new file mode 100644
index 000000000000000..b0d53333f4fdae1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt
@@ -0,0 +1,9 @@
+Bootwrapper boot method (software protocol on SMP):
+
+Required Properties:
+- compatible: "hisilicon,hip04-bootwrapper";
+- boot-method: Address and size of boot method.
+ [0]: bootwrapper physical address
+ [1]: bootwrapper size
+ [2]: relocation physical address
+ [3]: relocation size
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt
new file mode 100644
index 000000000000000..40453d02f2024bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt
@@ -0,0 +1,5 @@
+Fabric:
+
+Required Properties:
+- compatible: "hisilicon,hip04-fabric";
+- reg: Address and size of Fabric
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
new file mode 100644
index 000000000000000..1ef086bda81a3f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
@@ -0,0 +1,15 @@
+Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
+
+Required properties:
+- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
+- reg : Register address and size
+
+The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
+HiP05 or HiP06 Soc to implement some basic configurations.
+
+Example:
+ /* for HiP05 PCIe-SAS sub system */
+ pcie_sas: system_controller@b0000000 {
+ compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+ reg = <0xb0000000 0x10000>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt
new file mode 100644
index 000000000000000..deec777bc3a850a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt
@@ -0,0 +1,13 @@
+PCTRL: Peripheral misc control register
+
+Required Properties:
+- compatible: "hisilicon,pctrl"
+- reg: Address and size of pctrl.
+
+Example:
+
+ /* for Hi3620 */
+ pctrl: pctrl@fca09000 {
+ compatible = "hisilicon,pctrl";
+ reg = <0xfca09000 0x1000>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt
new file mode 100644
index 000000000000000..b96c2896078b914
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt
@@ -0,0 +1,16 @@
+Hisilicon HiP05/HiP06 PERI sub system controller
+
+Required properties:
+- compatible : "hisilicon,peri-subctrl", "syscon";
+- reg : Register address and size
+
+The PERI sub system controller is shared by peripheral controllers in
+HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
+controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+ /* for HiP05 sub peri system */
+ peri_c_subctrl: syscon@80000000 {
+ compatible = "hisilicon,peri-subctrl", "syscon";
+ reg = <0x0 0x80000000 0x0 0x10000>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
new file mode 100644
index 000000000000000..963f7f1ca7a2f0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
@@ -0,0 +1,25 @@
+Hisilicon system controller
+
+Required properties:
+- compatible : "hisilicon,sysctrl"
+- reg : Register address and size
+
+Optional properties:
+- smp-offset : offset in sysctrl for notifying slave cpu booting
+ cpu 1, reg;
+ cpu 2, reg + 0x4;
+ cpu 3, reg + 0x8;
+ If reg value is not zero, cpun exit wfi and go
+- resume-offset : offset in sysctrl for notifying cpu0 when resume
+- reboot-offset : offset in sysctrl for system reboot
+
+Example:
+
+ /* for Hi3620 */
+ sysctrl: system-controller@fc802000 {
+ compatible = "hisilicon,sysctrl";
+ reg = <0xfc802000 0x1000>;
+ smp-offset = <0x31c>;
+ resume-offset = <0x308>;
+ reboot-offset = <0x4>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index a97f643e7d1c760..ffe760a636b5e7f 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -55,265 +55,3 @@ Required root node properties:
HiP07 D05 Board
Required root node properties:
- compatible = "hisilicon,hip07-d05";
-
-Hisilicon system controller
-
-Required properties:
-- compatible : "hisilicon,sysctrl"
-- reg : Register address and size
-
-Optional properties:
-- smp-offset : offset in sysctrl for notifying slave cpu booting
- cpu 1, reg;
- cpu 2, reg + 0x4;
- cpu 3, reg + 0x8;
- If reg value is not zero, cpun exit wfi and go
-- resume-offset : offset in sysctrl for notifying cpu0 when resume
-- reboot-offset : offset in sysctrl for system reboot
-
-Example:
-
- /* for Hi3620 */
- sysctrl: system-controller@fc802000 {
- compatible = "hisilicon,sysctrl";
- reg = <0xfc802000 0x1000>;
- smp-offset = <0x31c>;
- resume-offset = <0x308>;
- reboot-offset = <0x4>;
- };
-
------------------------------------------------------------------------
-Hisilicon Hi3798CV200 Peripheral Controller
-
-The Hi3798CV200 Peripheral Controller controls peripherals, queries
-their status, and configures some functions of peripherals.
-
-Required properties:
-- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
- and "simple-mfd".
-- reg: Register address and size of Peripheral Controller.
-- #address-cells: Should be 1.
-- #size-cells: Should be 1.
-
-Examples:
-
- perictrl: peripheral-controller@8a20000 {
- compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
- "simple-mfd";
- reg = <0x8a20000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
------------------------------------------------------------------------
-Hisilicon Hi6220 system controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-sysctrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, many clock registers are defined
- under this controller and this property must be present.
-
-Hisilicon designs this controller as one of the system controllers,
-its main functions are the same as Hisilicon system controller, but
-the register offset of some core modules are different.
-
-Example:
- /*for Hi6220*/
- sys_ctrl: sys_ctrl@f7030000 {
- compatible = "hisilicon,hi6220-sysctrl", "syscon";
- reg = <0x0 0xf7030000 0x0 0x2000>;
- #clock-cells = <1>;
- };
-
-
-Hisilicon Hi6220 Power Always ON domain controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-aoctrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, many clock registers are defined
- under this controller and this property must be present.
-
-Hisilicon designs this system controller to control the power always
-on domain for mobile platform.
-
-Example:
- /*for Hi6220*/
- ao_ctrl: ao_ctrl@f7800000 {
- compatible = "hisilicon,hi6220-aoctrl", "syscon";
- reg = <0x0 0xf7800000 0x0 0x2000>;
- #clock-cells = <1>;
- };
-
-
-Hisilicon Hi6220 Media domain controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-mediactrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, many clock registers are defined
- under this controller and this property must be present.
-
-Hisilicon designs this system controller to control the multimedia
-domain(e.g. codec, G3D ...) for mobile platform.
-
-Example:
- /*for Hi6220*/
- media_ctrl: media_ctrl@f4410000 {
- compatible = "hisilicon,hi6220-mediactrl", "syscon";
- reg = <0x0 0xf4410000 0x0 0x1000>;
- #clock-cells = <1>;
- };
-
-
-Hisilicon Hi6220 Power Management domain controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-pmctrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, some clock registers are define
- under this controller and this property must be present.
-
-Hisilicon designs this system controller to control the power management
-domain for mobile platform.
-
-Example:
- /*for Hi6220*/
- pm_ctrl: pm_ctrl@f7032000 {
- compatible = "hisilicon,hi6220-pmctrl", "syscon";
- reg = <0x0 0xf7032000 0x0 0x1000>;
- #clock-cells = <1>;
- };
-
-
-Hisilicon Hi6220 SRAM controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-sramctrl", "syscon"
-- reg : Register address and size
-
-Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
-SRAM banks for power management, modem, security, etc. Further, use "syscon"
-managing the common sram which can be shared by multiple modules.
-
-Example:
- /*for Hi6220*/
- sram: sram@fff80000 {
- compatible = "hisilicon,hi6220-sramctrl", "syscon";
- reg = <0x0 0xfff80000 0x0 0x12000>;
- };
-
------------------------------------------------------------------------
-Hisilicon HiP01 system controller
-
-Required properties:
-- compatible : "hisilicon,hip01-sysctrl"
-- reg : Register address and size
-
-The HiP01 system controller is mostly compatible with hisilicon
-system controller,but it has some specific control registers for
-HIP01 SoC family, such as slave core boot, and also some same
-registers located at different offset.
-
-Example:
-
- /* for hip01-ca9x2 */
- sysctrl: system-controller@10000000 {
- compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
- reg = <0x10000000 0x1000>;
- reboot-offset = <0x4>;
- };
-
------------------------------------------------------------------------
-Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
-
-Required properties:
-- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
-- reg : Register address and size
-
-The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
-HiP05 or HiP06 Soc to implement some basic configurations.
-
-Example:
- /* for HiP05 PCIe-SAS sub system */
- pcie_sas: system_controller@b0000000 {
- compatible = "hisilicon,pcie-sas-subctrl", "syscon";
- reg = <0xb0000000 0x10000>;
- };
-
-Hisilicon HiP05/HiP06 PERI sub system controller
-
-Required properties:
-- compatible : "hisilicon,peri-subctrl", "syscon";
-- reg : Register address and size
-
-The PERI sub system controller is shared by peripheral controllers in
-HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
-controllers include mdio, ddr, iic, uart, timer and so on.
-
-Example:
- /* for HiP05 sub peri system */
- peri_c_subctrl: syscon@80000000 {
- compatible = "hisilicon,peri-subctrl", "syscon";
- reg = <0x0 0x80000000 0x0 0x10000>;
- };
-
-Hisilicon HiP05/HiP06 DSA sub system controller
-
-Required properties:
-- compatible : "hisilicon,dsa-subctrl", "syscon";
-- reg : Register address and size
-
-The DSA sub system controller is shared by peripheral controllers in
-HiP05 or HiP06 Soc to implement some basic configurations.
-
-Example:
- /* for HiP05 dsa sub system */
- pcie_sas: system_controller@a0000000 {
- compatible = "hisilicon,dsa-subctrl", "syscon";
- reg = <0xa0000000 0x10000>;
- };
-
------------------------------------------------------------------------
-Hisilicon CPU controller
-
-Required properties:
-- compatible : "hisilicon,cpuctrl"
-- reg : Register address and size
-
-The clock registers and power registers of secondary cores are defined
-in CPU controller, especially in HIX5HD2 SoC.
-
------------------------------------------------------------------------
-PCTRL: Peripheral misc control register
-
-Required Properties:
-- compatible: "hisilicon,pctrl"
-- reg: Address and size of pctrl.
-
-Example:
-
- /* for Hi3620 */
- pctrl: pctrl@fca09000 {
- compatible = "hisilicon,pctrl";
- reg = <0xfca09000 0x1000>;
- };
-
------------------------------------------------------------------------
-Fabric:
-
-Required Properties:
-- compatible: "hisilicon,hip04-fabric";
-- reg: Address and size of Fabric
-
------------------------------------------------------------------------
-Bootwrapper boot method (software protocol on SMP):
-
-Required Properties:
-- compatible: "hisilicon,hip04-bootwrapper";
-- boot-method: Address and size of boot method.
- [0]: bootwrapper physical address
- [1]: bootwrapper size
- [2]: relocation physical address
- [3]: relocation size
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 02/20] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
2020-09-28 15:13 ` [PATCH v4 01/20] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 19:06 ` Rob Herring
2020-09-28 15:13 ` [PATCH v4 03/20] dt-bindings: arm: hisilicon: add binding for SD5203 SoC Zhen Lei
` (17 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert Hisilicon SoC bindings to DT schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../bindings/arm/hisilicon/hisilicon.txt | 57 --------------------
.../bindings/arm/hisilicon/hisilicon.yaml | 62 ++++++++++++++++++++++
2 files changed, 62 insertions(+), 57 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
deleted file mode 100644
index ffe760a636b5e7f..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-Hisilicon Platforms Device Tree Bindings
-----------------------------------------------------
-Hi3660 SoC
-Required root node properties:
- - compatible = "hisilicon,hi3660";
-
-HiKey960 Board
-Required root node properties:
- - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
-
-Hi3670 SoC
-Required root node properties:
- - compatible = "hisilicon,hi3670";
-
-HiKey970 Board
-Required root node properties:
- - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
-
-Hi3798cv200 SoC
-Required root node properties:
- - compatible = "hisilicon,hi3798cv200";
-
-Hi3798cv200 Poplar Board
-Required root node properties:
- - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
-
-Hi4511 Board
-Required root node properties:
- - compatible = "hisilicon,hi3620-hi4511";
-
-Hi6220 SoC
-Required root node properties:
- - compatible = "hisilicon,hi6220";
-
-HiKey Board
-Required root node properties:
- - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
-
-HiP01 ca9x2 Board
-Required root node properties:
- - compatible = "hisilicon,hip01-ca9x2";
-
-HiP04 D01 Board
-Required root node properties:
- - compatible = "hisilicon,hip04-d01";
-
-HiP05 D02 Board
-Required root node properties:
- - compatible = "hisilicon,hip05-d02";
-
-HiP06 D03 Board
-Required root node properties:
- - compatible = "hisilicon,hip06-d03";
-
-HiP07 D05 Board
-Required root node properties:
- - compatible = "hisilicon,hip07-d05";
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
new file mode 100644
index 000000000000000..6d17309c7c84308
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Platforms Device Tree Bindings
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+properties:
+ $nodename:
+ const: '/'
+
+ compatible:
+ oneOf:
+ - description: Hi3660 based boards.
+ items:
+ - const: hisilicon,hi3660-hikey960
+ - const: hisilicon,hi3660
+
+ - description: Hi3670 based boards.
+ items:
+ - const: hisilicon,hi3670-hikey970
+ - const: hisilicon,hi3670
+
+ - description: Hi3798cv200 based boards.
+ items:
+ - const: hisilicon,hi3798cv200-poplar
+ - const: hisilicon,hi3798cv200
+
+ - description: Hi4511 Board
+ items:
+ - const: hisilicon,hi3620-hi4511
+
+ - description: Hi6220 based boards.
+ items:
+ - const: hisilicon,hi6220-hikey
+ - const: hisilicon,hi6220
+
+ - description: HiP01 based boards.
+ items:
+ - const: hisilicon,hip01-ca9x2
+ - const: hisilicon,hip01
+
+ - description: HiP04 D01 Board
+ items:
+ - const: hisilicon,hip04-d01
+
+ - description: HiP05 D02 Board
+ items:
+ - const: hisilicon,hip05-d02
+
+ - description: HiP06 D03 Board
+ items:
+ - const: hisilicon,hip06-d03
+
+ - description: HiP07 D05 Board
+ items:
+ - const: hisilicon,hip07-d05
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 03/20] dt-bindings: arm: hisilicon: add binding for SD5203 SoC
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
2020-09-28 15:13 ` [PATCH v4 01/20] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Zhen Lei
2020-09-28 15:13 ` [PATCH v4 02/20] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 19:07 ` Rob Herring
2020-09-28 15:13 ` [PATCH v4 04/20] ARM: hisi: add support " Zhen Lei
` (16 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Add devicetree binding for Hisilicon SD5203 SoC.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
index 6d17309c7c84308..3337eebc61da812 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
@@ -59,4 +59,8 @@ properties:
- description: HiP07 D05 Board
items:
- const: hisilicon,hip07-d05
+
+ - description: SD5203 Board
+ items:
+ - const: hisilicon,sd5203
...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 04/20] ARM: hisi: add support for SD5203 SoC
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (2 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 03/20] dt-bindings: arm: hisilicon: add binding for SD5203 SoC Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 05/20] ARM: debug: add UART early console support for SD5203 Zhen Lei
` (15 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Enable support for the Hisilicon SD5203 SoC. The core is ARM926EJ-S.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm/mach-hisi/Kconfig | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 3b010fe7c0e9b48..2e980f834a6aa1b 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_HISI
bool "Hisilicon SoC Support"
- depends on ARCH_MULTI_V7
+ depends on ARCH_MULTI_V7 || ARCH_MULTI_V5
select ARM_AMBA
- select ARM_GIC
+ select ARM_GIC if ARCH_MULTI_V7
select ARM_TIMER_SP804
select POWER_RESET
select POWER_RESET_HISI
@@ -15,6 +15,7 @@ menu "Hisilicon platform type"
config ARCH_HI3xxx
bool "Hisilicon Hi36xx family"
+ depends on ARCH_MULTI_V7
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
@@ -25,6 +26,7 @@ config ARCH_HI3xxx
config ARCH_HIP01
bool "Hisilicon HIP01 family"
+ depends on ARCH_MULTI_V7
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select ARM_GLOBAL_TIMER
@@ -33,6 +35,7 @@ config ARCH_HIP01
config ARCH_HIP04
bool "Hisilicon HiP04 Cortex A15 family"
+ depends on ARCH_MULTI_V7
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
select MCPM if SMP
@@ -43,6 +46,7 @@ config ARCH_HIP04
config ARCH_HIX5HD2
bool "Hisilicon X5HD2 family"
+ depends on ARCH_MULTI_V7
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
@@ -50,6 +54,14 @@ config ARCH_HIX5HD2
select PINCTRL_SINGLE
help
Support for Hisilicon HIX5HD2 SoC family
+
+config ARCH_SD5203
+ bool "Hisilicon SD5203 family"
+ depends on ARCH_MULTI_V5
+ select DW_APB_ICTL
+ help
+ Support for Hisilicon SD5203 SoC family
+
endmenu
endif
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 05/20] ARM: debug: add UART early console support for SD5203
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (3 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 04/20] ARM: hisi: add support " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 06/20] ARM: dts: add SD5203 dts Zhen Lei
` (14 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Add support of early console for SD5203.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm/Kconfig.debug | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 80000a66a4e3549..d27a7764c3bfb46 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1086,6 +1086,14 @@ choice
on SA-11x0 UART ports. The kernel will check for the first
enabled UART in a sequence 3-1-2.
+ config DEBUG_SD5203_UART
+ bool "Hisilicon SD5203 Debug UART"
+ depends on ARCH_SD5203
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on SD5203 UART.
+
config DEBUG_SOCFPGA_UART0
depends on ARCH_SOCFPGA
bool "Use SOCFPGA UART0 for low-level debug"
@@ -1639,6 +1647,7 @@ config DEBUG_UART_PHYS
default 0x11006000 if DEBUG_MT6589_UART0
default 0x11009000 if DEBUG_MT8135_UART3
default 0x16000000 if DEBUG_INTEGRATOR
+ default 0x1600d000 if DEBUG_SD5203_UART
default 0x18000300 if DEBUG_BCM_5301X
default 0x18000400 if DEBUG_BCM_HR2
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
@@ -1841,7 +1850,7 @@ config DEBUG_UART_VIRT
default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
- default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
+ default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART
default 0xfed60000 if DEBUG_RK29_UART0
default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 06/20] ARM: dts: add SD5203 dts
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (4 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 05/20] ARM: debug: add UART early console support for SD5203 Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 07/20] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema Zhen Lei
` (13 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
From: Kefeng Wang <wangkefeng.wang@huawei.com>
Add sd5203.dts for Hisilicon SD5203 SoC platform.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sd5203.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 98 insertions(+)
create mode 100644 arch/arm/boot/dts/sd5203.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4572db3fa5ae302..1d1262df5c55907 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \
mps2-an399.dtb
dtb-$(CONFIG_ARCH_MOXART) += \
moxart-uc7112lx.dtb
+dtb-$(CONFIG_ARCH_SD5203) += \
+ sd5203.dtb
dtb-$(CONFIG_SOC_IMX1) += \
imx1-ads.dtb \
imx1-apf9328.dtb
diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
new file mode 100644
index 000000000000000..41113a46a71a584
--- /dev/null
+++ b/arch/arm/boot/dts/sd5203.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 Hisilicon Limited.
+ *
+ * DTS file for Hisilicon SD5203 Board
+ */
+
+/dts-v1/;
+
+/ {
+ model = "Hisilicon SD5203";
+ compatible = "hisilicon,sd5203";
+ interrupt-parent = <&vic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0 {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ reg = <0x0>;
+ };
+ };
+
+ memory@30000000 {
+ device_type = "memory";
+ reg = <0x30000000 0x8000000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+
+ vic: interrupt-controller@10130000 {
+ compatible = "snps,dw-apb-ictl";
+ reg = <0x10130000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ refclk125mhz: refclk125mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ timer0: timer@16002000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x16002000 0x1000>;
+ interrupts = <4>;
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ timer1: timer@16003000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x16003000 0x1000>;
+ interrupts = <5>;
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ uart0: serial@1600d000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x1600d000 0x1000>;
+ bus_id = "uart0";
+ clocks = <&refclk125mhz>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <17>;
+ };
+
+ uart1: serial@1600c000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x1600c000 0x1000>;
+ clocks = <&refclk125mhz>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+ };
+};
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 07/20] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (5 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 06/20] ARM: dts: add SD5203 dts Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 19:13 ` Rob Herring
2020-09-28 15:13 ` [PATCH v4 08/20] dt-bindings: arm: hisilicon: convert hisilicon,peri-subctrl " Zhen Lei
` (12 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon system controller and its variants binding to DT
schema format using json-schema. All of them are grouped into one yaml
file, to help users understand differences and avoid repeated
descriptions.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../controller/hisilicon,hi6220-sysctrl.txt | 19 ----
.../controller/hisilicon,hip01-sysctrl.txt | 19 ----
.../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 -----
.../hisilicon/controller/hisilicon,sysctrl.yaml | 115 +++++++++++++++++++++
.../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ---
5 files changed, 115 insertions(+), 77 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
deleted file mode 100644
index 07e318eda254f52..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Hisilicon Hi6220 system controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-sysctrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, many clock registers are defined
- under this controller and this property must be present.
-
-Hisilicon designs this controller as one of the system controllers,
-its main functions are the same as Hisilicon system controller, but
-the register offset of some core modules are different.
-
-Example:
- /*for Hi6220*/
- sys_ctrl: sys_ctrl@f7030000 {
- compatible = "hisilicon,hi6220-sysctrl", "syscon";
- reg = <0x0 0xf7030000 0x0 0x2000>;
- #clock-cells = <1>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
deleted file mode 100644
index db2dfdce799db91..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Hisilicon HiP01 system controller
-
-Required properties:
-- compatible : "hisilicon,hip01-sysctrl"
-- reg : Register address and size
-
-The HiP01 system controller is mostly compatible with hisilicon
-system controller,but it has some specific control registers for
-HIP01 SoC family, such as slave core boot, and also some same
-registers located at different offset.
-
-Example:
-
- /* for hip01-ca9x2 */
- sysctrl: system-controller@10000000 {
- compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
- reg = <0x10000000 0x1000>;
- reboot-offset = <0x4>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
deleted file mode 100644
index 963f7f1ca7a2f0c..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Hisilicon system controller
-
-Required properties:
-- compatible : "hisilicon,sysctrl"
-- reg : Register address and size
-
-Optional properties:
-- smp-offset : offset in sysctrl for notifying slave cpu booting
- cpu 1, reg;
- cpu 2, reg + 0x4;
- cpu 3, reg + 0x8;
- If reg value is not zero, cpun exit wfi and go
-- resume-offset : offset in sysctrl for notifying cpu0 when resume
-- reboot-offset : offset in sysctrl for system reboot
-
-Example:
-
- /* for Hi3620 */
- sysctrl: system-controller@fc802000 {
- compatible = "hisilicon,sysctrl";
- reg = <0xfc802000 0x1000>;
- smp-offset = <0x31c>;
- resume-offset = <0x308>;
- reboot-offset = <0x4>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml
new file mode 100644
index 000000000000000..37b214e0a401d7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,sysctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon system controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ The Hisilicon system controller is used on many Hisilicon boards, it can be
+ used to assist the slave core startup, reboot the system, etc.
+
+ There are some variants of the Hisilicon system controller, such as HiP01,
+ Hi3519, Hi6220 system controller, each of them is mostly compatible with the
+ Hisilicon system controller, but some same registers located at different
+ offset. In addition, the HiP01 system controller has some specific control
+ registers for HIP01 SoC family, such as slave core boot.
+
+ The compatible names of each system controller are as follows:
+ Hisilicon system controller --> hisilicon,sysctrl
+ HiP01 system controller --> hisilicon,hip01-sysctrl
+ Hi6220 system controller --> hisilicon,hi6220-sysctrl
+ Hi3519 system controller --> hisilicon,hi3519-sysctrl
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: hisilicon,hi6220-sysctrl
+ then:
+ required:
+ - '#clock-cells'
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: hisilicon,sysctrl
+ - items:
+ - const: hisilicon,sysctrl
+ - const: syscon
+ - items:
+ - const: hisilicon,hip01-sysctrl
+ - const: hisilicon,sysctrl
+ - items:
+ - const: hisilicon,hi6220-sysctrl
+ - const: syscon
+ - items:
+ - const: hisilicon,hi3519-sysctrl
+ - const: syscon
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+ smp-offset:
+ description: |
+ offset in sysctrl for notifying slave cpu booting
+ cpu 1, reg;
+ cpu 2, reg + 0x4;
+ cpu 3, reg + 0x8;
+ If reg value is not zero, cpun exit wfi and go
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ resume-offset:
+ description: offset in sysctrl for notifying cpu0 when resume
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ reboot-offset:
+ description: offset in sysctrl for system reboot
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ '#clock-cells':
+ description: the number of cells occupied by one clock ID.
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ /* Hisilicon system controller */
+ system-controller@fc802000 {
+ compatible = "hisilicon,sysctrl";
+ reg = <0xfc802000 0x1000>;
+ smp-offset = <0x31c>;
+ resume-offset = <0x308>;
+ reboot-offset = <0x4>;
+ };
+
+ /* HiP01 system controller */
+ system-controller@10000000 {
+ compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
+ reg = <0x10000000 0x1000>;
+ reboot-offset = <0x4>;
+ };
+
+ /* Hi6220 system controller */
+ system-controller@f7030000 {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0xf7030000 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ /* Hi3519 system controller */
+ system-controller@12010000 {
+ compatible = "hisilicon,hi3519-sysctrl", "syscon";
+ reg = <0x12010000 0x1000>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
deleted file mode 100644
index 8defacc44dd5b9e..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Hisilicon Hi3519 System Controller Block
-
-This bindings use the following binding:
-Documentation/devicetree/bindings/mfd/syscon.yaml
-
-Required properties:
-- compatible: "hisilicon,hi3519-sysctrl".
-- reg: the register region of this block
-
-Examples:
-sysctrl: system-controller@12010000 {
- compatible = "hisilicon,hi3519-sysctrl", "syscon";
- reg = <0x12010000 0x1000>;
-};
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 08/20] dt-bindings: arm: hisilicon: convert hisilicon,peri-subctrl bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (6 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 07/20] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 09/20] dt-bindings: arm: hisilicon: convert hisilicon,pcie-sas-subctrl " Zhen Lei
` (11 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon HiP05/HiP06 PERI subsystem controller binding to DT
schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../controller/hisilicon,peri-subctrl.txt | 16 ----------
.../controller/hisilicon,peri-subctrl.yaml | 34 ++++++++++++++++++++++
2 files changed, 34 insertions(+), 16 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt
deleted file mode 100644
index b96c2896078b914..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Hisilicon HiP05/HiP06 PERI sub system controller
-
-Required properties:
-- compatible : "hisilicon,peri-subctrl", "syscon";
-- reg : Register address and size
-
-The PERI sub system controller is shared by peripheral controllers in
-HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
-controllers include mdio, ddr, iic, uart, timer and so on.
-
-Example:
- /* for HiP05 sub peri system */
- peri_c_subctrl: syscon@80000000 {
- compatible = "hisilicon,peri-subctrl", "syscon";
- reg = <0x0 0x80000000 0x0 0x10000>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml
new file mode 100644
index 000000000000000..838b1a2a2c8a9a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon HiP05/HiP06 PERI subsystem controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ The PERI sub system controller is shared by peripheral controllers in
+ HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,peri-subctrl
+ - const: syscon
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+examples:
+ - |
+ /* for HiP05 sub peri system */
+ peri_c_subctrl: syscon@80000000 {
+ compatible = "hisilicon,peri-subctrl", "syscon";
+ reg = <0x80000000 0x10000>;
+ };
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 09/20] dt-bindings: arm: hisilicon: convert hisilicon,pcie-sas-subctrl bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (7 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 08/20] dt-bindings: arm: hisilicon: convert hisilicon,peri-subctrl " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 10/20] dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl " Zhen Lei
` (10 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller binding
to DT schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../controller/hisilicon,pcie-sas-subctrl.txt | 15 ---------
.../controller/hisilicon,pcie-sas-subctrl.yaml | 37 ++++++++++++++++++++++
2 files changed, 37 insertions(+), 15 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
deleted file mode 100644
index 1ef086bda81a3f5..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
-
-Required properties:
-- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
-- reg : Register address and size
-
-The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
-HiP05 or HiP06 Soc to implement some basic configurations.
-
-Example:
- /* for HiP05 PCIe-SAS sub system */
- pcie_sas: system_controller@b0000000 {
- compatible = "hisilicon,pcie-sas-subctrl", "syscon";
- reg = <0xb0000000 0x10000>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
new file mode 100644
index 000000000000000..2de875ae781cf8a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
+ HiP05 or HiP06 Soc to implement some basic configurations.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,pcie-sas-subctrl
+ - const: syscon
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ /* for HiP05 PCIe-SAS sub system */
+ pcie_sas: system_controller@b0000000 {
+ compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+ reg = <0xb0000000 0x10000>;
+ };
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 10/20] dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (8 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 09/20] dt-bindings: arm: hisilicon: convert hisilicon,pcie-sas-subctrl " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 11/20] dt-bindings: arm: hisilicon: convert hisilicon,pctrl " Zhen Lei
` (9 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon CPU controller binding to DT schema format using
json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 -------
.../hisilicon/controller/hisilicon,cpuctrl.yaml | 28 ++++++++++++++++++++++
2 files changed, 28 insertions(+), 8 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
deleted file mode 100644
index ceffac537671668..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-Hisilicon CPU controller
-
-Required properties:
-- compatible : "hisilicon,cpuctrl"
-- reg : Register address and size
-
-The clock registers and power registers of secondary cores are defined
-in CPU controller, especially in HIX5HD2 SoC.
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml
new file mode 100644
index 000000000000000..05b97e0bc35b090
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,cpuctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon CPU controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ The clock registers and power registers of secondary cores are defined
+ in CPU controller, especially in HIX5HD2 SoC.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,cpuctrl
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 11/20] dt-bindings: arm: hisilicon: convert hisilicon,pctrl bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (9 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 10/20] dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl " Zhen Lei
` (8 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon peripheral misc control register binding to DT
schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 ---------
.../arm/hisilicon/controller/hisilicon,pctrl.yaml | 34 ++++++++++++++++++++++
2 files changed, 34 insertions(+), 13 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt
deleted file mode 100644
index deec777bc3a850a..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-PCTRL: Peripheral misc control register
-
-Required Properties:
-- compatible: "hisilicon,pctrl"
-- reg: Address and size of pctrl.
-
-Example:
-
- /* for Hi3620 */
- pctrl: pctrl@fca09000 {
- compatible = "hisilicon,pctrl";
- reg = <0xfca09000 0x1000>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml
new file mode 100644
index 000000000000000..8b00e9c222594f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Peripheral misc control register
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: Peripheral misc control register
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,pctrl
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ /* for Hi3620 */
+ pctrl: pctrl@fca09000 {
+ compatible = "hisilicon,pctrl";
+ reg = <0xfca09000 0x1000>;
+ };
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (10 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 11/20] dt-bindings: arm: hisilicon: convert hisilicon,pctrl " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 19:14 ` Rob Herring
2020-09-28 15:13 ` [PATCH v4 13/20] dt-bindings: arm: hisilicon: convert hisilicon,dsa-subctrl " Zhen Lei
` (7 subsequent siblings)
19 siblings, 1 reply; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT
schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ----------
.../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++++++++++++++++++++++
2 files changed, 45 insertions(+), 21 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
deleted file mode 100644
index 0d5282f4670658d..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Hisilicon Hi3798CV200 Peripheral Controller
-
-The Hi3798CV200 Peripheral Controller controls peripherals, queries
-their status, and configures some functions of peripherals.
-
-Required properties:
-- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
- and "simple-mfd".
-- reg: Register address and size of Peripheral Controller.
-- #address-cells: Should be 1.
-- #size-cells: Should be 1.
-
-Examples:
-
- perictrl: peripheral-controller@8a20000 {
- compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
- "simple-mfd";
- reg = <0x8a20000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
new file mode 100644
index 000000000000000..4e547017e368393
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Hi3798CV200 Peripheral Controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ The Hi3798CV200 Peripheral Controller controls peripherals, queries
+ their status, and configures some functions of peripherals.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hi3798cv200-perictrl
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ perictrl: peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 13/20] dt-bindings: arm: hisilicon: convert hisilicon,dsa-subctrl bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (11 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 14/20] dt-bindings: arm: hisilicon: convert hisilicon,hip04-fabric " Zhen Lei
` (6 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon HiP05/HiP06 DSA subsystem controller binding to DT
schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 ---------
.../controller/hisilicon,dsa-subctrl.yaml | 37 ++++++++++++++++++++++
2 files changed, 37 insertions(+), 15 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
deleted file mode 100644
index 4d1c6abf03f6f97..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Hisilicon HiP05/HiP06 DSA sub system controller
-
-Required properties:
-- compatible : "hisilicon,dsa-subctrl", "syscon";
-- reg : Register address and size
-
-The DSA sub system controller is shared by peripheral controllers in
-HiP05 or HiP06 Soc to implement some basic configurations.
-
-Example:
- /* for HiP05 dsa sub system */
- pcie_sas: system_controller@a0000000 {
- compatible = "hisilicon,dsa-subctrl", "syscon";
- reg = <0xa0000000 0x10000>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml
new file mode 100644
index 000000000000000..3e18fd8debd92f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon HiP05/HiP06 DSA subsystem controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ The DSA sub system controller is shared by peripheral controllers in
+ HiP05 or HiP06 Soc to implement some basic configurations.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,dsa-subctrl
+ - const: syscon
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ /* for HiP05 dsa sub system */
+ pcie_sas: system_controller@a0000000 {
+ compatible = "hisilicon,dsa-subctrl", "syscon";
+ reg = <0xa0000000 0x10000>;
+ };
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 14/20] dt-bindings: arm: hisilicon: convert hisilicon,hip04-fabric bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (12 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 13/20] dt-bindings: arm: hisilicon: convert hisilicon,dsa-subctrl " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 15/20] dt-bindings: arm: hisilicon: convert hisilicon,hip04-bootwrapper " Zhen Lei
` (5 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon Fabric controller binding to DT schema format using
json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../controller/hisilicon,hip04-fabric.txt | 5 -----
.../controller/hisilicon,hip04-fabric.yaml | 26 ++++++++++++++++++++++
2 files changed, 26 insertions(+), 5 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt
deleted file mode 100644
index 40453d02f2024bd..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Fabric:
-
-Required Properties:
-- compatible: "hisilicon,hip04-fabric";
-- reg: Address and size of Fabric
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml
new file mode 100644
index 000000000000000..47a2ec6a4704f4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Fabric controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: Hisilicon Fabric controller
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hip04-fabric
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 15/20] dt-bindings: arm: hisilicon: convert hisilicon,hip04-bootwrapper bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (13 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 14/20] dt-bindings: arm: hisilicon: convert hisilicon,hip04-fabric " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 16/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-aoctrl " Zhen Lei
` (4 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon Bootwrapper boot method binding to DT schema format
using json-schema.
The property boot-method contains two groups of physical address range
information: bootwrapper and relocation. The "uint32-array" type is not
suitable for it, because the field "address" and "size" may occupy one or
two cells respectively. Use "minItems: 1" and "maxItems: 2" to allow it
can be written in "<addr size addr size>" or "<addr size>, <addr size>"
format.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../controller/hisilicon,hip04-bootwrapper.txt | 9 ------
.../controller/hisilicon,hip04-bootwrapper.yaml | 32 ++++++++++++++++++++++
2 files changed, 32 insertions(+), 9 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt
deleted file mode 100644
index b0d53333f4fdae1..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-Bootwrapper boot method (software protocol on SMP):
-
-Required Properties:
-- compatible: "hisilicon,hip04-bootwrapper";
-- boot-method: Address and size of boot method.
- [0]: bootwrapper physical address
- [1]: bootwrapper size
- [2]: relocation physical address
- [3]: relocation size
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml
new file mode 100644
index 000000000000000..d88ef8487879fc1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bootwrapper boot method
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: Bootwrapper boot method (software protocol on SMP)
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hip04-bootwrapper
+
+ boot-method:
+ description: |
+ Address and size of boot method.
+ [0]: bootwrapper physical address
+ [1]: bootwrapper size
+ [2]: relocation physical address
+ [3]: relocation size
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+ - boot-method
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 16/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-aoctrl bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (14 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 15/20] dt-bindings: arm: hisilicon: convert hisilicon,hip04-bootwrapper " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 17/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-mediactrl " Zhen Lei
` (3 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon Hi6220 Power Always ON domain controller binding to
DT schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../controller/hisilicon,hi6220-aoctrl.txt | 18 ----------
.../controller/hisilicon,hi6220-aoctrl.yaml | 42 ++++++++++++++++++++++
2 files changed, 42 insertions(+), 18 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt
deleted file mode 100644
index 5a723c1d45f4a17..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Hisilicon Hi6220 Power Always ON domain controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-aoctrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, many clock registers are defined
- under this controller and this property must be present.
-
-Hisilicon designs this system controller to control the power always
-on domain for mobile platform.
-
-Example:
- /*for Hi6220*/
- ao_ctrl: ao_ctrl@f7800000 {
- compatible = "hisilicon,hi6220-aoctrl", "syscon";
- reg = <0x0 0xf7800000 0x0 0x2000>;
- #clock-cells = <1>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml
new file mode 100644
index 000000000000000..6939fe85e1895f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Hi6220 Power Always ON domain controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ Hisilicon designs this system controller to control the power always
+ on domain for mobile platform.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hi6220-aoctrl
+ - const: syscon
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+examples:
+ - |
+ /*for Hi6220*/
+ ao_ctrl: ao_ctrl@f7800000 {
+ compatible = "hisilicon,hi6220-aoctrl", "syscon";
+ reg = <0xf7800000 0x2000>;
+ #clock-cells = <1>;
+ };
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 17/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-mediactrl bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (15 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 16/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-aoctrl " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 18/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-pmctrl " Zhen Lei
` (2 subsequent siblings)
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon Hi6220 Media domain controller binding to DT schema
format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../controller/hisilicon,hi6220-mediactrl.txt | 18 ----------
.../controller/hisilicon,hi6220-mediactrl.yaml | 42 ++++++++++++++++++++++
2 files changed, 42 insertions(+), 18 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt
deleted file mode 100644
index dcfdcbcb6455771..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Hisilicon Hi6220 Media domain controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-mediactrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, many clock registers are defined
- under this controller and this property must be present.
-
-Hisilicon designs this system controller to control the multimedia
-domain(e.g. codec, G3D ...) for mobile platform.
-
-Example:
- /*for Hi6220*/
- media_ctrl: media_ctrl@f4410000 {
- compatible = "hisilicon,hi6220-mediactrl", "syscon";
- reg = <0x0 0xf4410000 0x0 0x1000>;
- #clock-cells = <1>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml
new file mode 100644
index 000000000000000..d6edbe8773a103b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Hi6220 Media domain controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ Hisilicon designs this system controller to control the multimedia
+ domain(e.g. codec, G3D ...) for mobile platform.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hi6220-mediactrl
+ - const: syscon
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+examples:
+ - |
+ /* for Hi6220 */
+ media_ctrl: media_ctrl@f4410000 {
+ compatible = "hisilicon,hi6220-mediactrl", "syscon";
+ reg = <0xf4410000 0x1000>;
+ #clock-cells = <1>;
+ };
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 18/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-pmctrl bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (16 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 17/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-mediactrl " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 19/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-sramctrl " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 20/20] dt-bindings: arm: hisilicon: convert LPC controller " Zhen Lei
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon Hi6220 Power Management domain controller binding
to DT schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../controller/hisilicon,hi6220-pmctrl.txt | 18 ----------
.../controller/hisilicon,hi6220-pmctrl.yaml | 42 ++++++++++++++++++++++
2 files changed, 42 insertions(+), 18 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt
deleted file mode 100644
index 972842f07b5a2ce..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Hisilicon Hi6220 Power Management domain controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-pmctrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, some clock registers are define
- under this controller and this property must be present.
-
-Hisilicon designs this system controller to control the power management
-domain for mobile platform.
-
-Example:
- /*for Hi6220*/
- pm_ctrl: pm_ctrl@f7032000 {
- compatible = "hisilicon,hi6220-pmctrl", "syscon";
- reg = <0x0 0xf7032000 0x0 0x1000>;
- #clock-cells = <1>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml
new file mode 100644
index 000000000000000..978a6920d69c217
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Hi6220 Power Management domain controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ Hisilicon designs this system controller to control the power management
+ domain for mobile platform.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hi6220-pmctrl
+ - const: syscon
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+examples:
+ - |
+ /* for Hi6220 */
+ pm_ctrl: pm_ctrl@f7032000 {
+ compatible = "hisilicon,hi6220-pmctrl", "syscon";
+ reg = <0xf7032000 0x1000>;
+ #clock-cells = <1>;
+ };
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 19/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-sramctrl bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (17 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 18/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-pmctrl " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 15:13 ` [PATCH v4 20/20] dt-bindings: arm: hisilicon: convert LPC controller " Zhen Lei
19 siblings, 0 replies; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon Hi6220 SRAM controller binding to DT schema format
using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../controller/hisilicon,hi6220-sramctrl.txt | 16 ---------
.../controller/hisilicon,hi6220-sramctrl.yaml | 38 ++++++++++++++++++++++
2 files changed, 38 insertions(+), 16 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt
deleted file mode 100644
index 086b7acccc5edc4..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Hisilicon Hi6220 SRAM controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-sramctrl", "syscon"
-- reg : Register address and size
-
-Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
-SRAM banks for power management, modem, security, etc. Further, use "syscon"
-managing the common sram which can be shared by multiple modules.
-
-Example:
- /*for Hi6220*/
- sram: sram@fff80000 {
- compatible = "hisilicon,hi6220-sramctrl", "syscon";
- reg = <0x0 0xfff80000 0x0 0x12000>;
- };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml
new file mode 100644
index 000000000000000..4ac1e14420ecfe7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Hi6220 SRAM controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ Hisilicon's SoCs use SRAM for consistency purpose; on Hi6220 there have
+ several SRAM banks for power management, modem, security, etc. Further, use
+ "syscon" managing the common sram which can be shared by multiple modules.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hi6220-sramctrl
+ - const: syscon
+
+ reg:
+ description: Register address and size
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ /* for Hi6220 */
+ sram: sram@fff80000 {
+ compatible = "hisilicon,hi6220-sramctrl", "syscon";
+ reg = <0xfff80000 0x12000>;
+ };
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 20/20] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema
2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
` (18 preceding siblings ...)
2020-09-28 15:13 ` [PATCH v4 19/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-sramctrl " Zhen Lei
@ 2020-09-28 15:13 ` Zhen Lei
2020-09-28 19:16 ` Rob Herring
19 siblings, 1 reply; 36+ messages in thread
From: Zhen Lei @ 2020-09-28 15:13 UTC (permalink / raw)
To: Wei Xu, Rob Herring, Jonathan Cameron, devicetree,
linux-arm-kernel, linux-kernel
Cc: Zhen Lei, Libin, Kefeng Wang
Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC)
controller binding to DT schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------
.../arm/hisilicon/hisilicon-low-pin-count.yaml | 61 ++++++++++++++++++++++
2 files changed, 61 insertions(+), 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
deleted file mode 100644
index 10bd35f9207f2ee..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Hisilicon Hip06 Low Pin Count device
- Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
- provides I/O access to some legacy ISA devices.
- Hip06 is based on arm64 architecture where there is no I/O space. So, the
- I/O ports here are not CPU addresses, and there is no 'ranges' property in
- LPC device node.
-
-Required properties:
-- compatible: value should be as follows:
- (a) "hisilicon,hip06-lpc"
- (b) "hisilicon,hip07-lpc"
-- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
-- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
-- reg: base memory range where the LPC register set is mapped.
-
-Note:
- The node name before '@' must be "isa" to represent the binding stick to the
- ISA/EISA binding specification.
-
-Example:
-
-isa@a01b0000 {
- compatible = "hisilicon,hip06-lpc";
- #address-cells = <2>;
- #size-cells = <1>;
- reg = <0x0 0xa01b0000 0x0 0x1000>;
-
- ipmi0: bt@e4 {
- compatible = "ipmi-bt";
- device_type = "ipmi";
- reg = <0x01 0xe4 0x04>;
- };
-};
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
new file mode 100644
index 000000000000000..83ca10adce71b62
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon-low-pin-count.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Hip06 Low Pin Count device
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
+ provides I/O access to some legacy ISA devices.
+ Hip06 is based on arm64 architecture where there is no I/O space. So, the
+ I/O ports here are not CPU addresses, and there is no 'ranges' property in
+ LPC device node.
+
+properties:
+ $nodename:
+ pattern: '^isa@[0-9a-f]+$'
+ description: |
+ The node name before '@' must be "isa" to represent the binding stick
+ to the ISA/EISA binding specification.
+
+ compatible:
+ enum:
+ - hisilicon,hip06-lpc
+ - hisilicon,hip07-lpc
+
+ reg:
+ description: base memory range where the LPC register set is mapped.
+ maxItems: 1
+
+ '#address-cells':
+ description: must be 2 which stick to the ISA/EISA binding doc.
+ const: 2
+
+ '#size-cells':
+ description: must be 1 which stick to the ISA/EISA binding doc.
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ isa@a01b0000 {
+ compatible = "hisilicon,hip06-lpc";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0xa01b0000 0x1000>;
+
+ ipmi0: bt@e4 {
+ compatible = "ipmi-bt";
+ device_type = "ipmi";
+ reg = <0x01 0xe4 0x04>;
+ };
+ };
+...
--
1.8.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH v4 01/20] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file
2020-09-28 15:13 ` [PATCH v4 01/20] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Zhen Lei
@ 2020-09-28 19:05 ` Rob Herring
2020-09-29 3:05 ` Leizhen (ThunderTown)
0 siblings, 1 reply; 36+ messages in thread
From: Rob Herring @ 2020-09-28 19:05 UTC (permalink / raw)
To: Zhen Lei
Cc: Wei Xu, Jonathan Cameron, devicetree, linux-arm-kernel,
linux-kernel, Libin, Kefeng Wang
On Mon, Sep 28, 2020 at 11:13:05PM +0800, Zhen Lei wrote:
> Split the devicetree bindings of each Hisilicon controller from
> hisilicon.txt into a separate file, the file name is the compatible name
> attach the .txt file name extension.
>
> All Hi6220 dedicated controllers are grouped into subdirectory "hi3620".
> All HiPxx dedicated controllers are grouped into subdirectory "hipxx"
>
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
> .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 +
> .../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 ++
> .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ++
> .../controller/hisilicon,hi6220-aoctrl.txt | 18 ++
> .../controller/hisilicon,hi6220-mediactrl.txt | 18 ++
> .../controller/hisilicon,hi6220-pmctrl.txt | 18 ++
> .../controller/hisilicon,hi6220-sramctrl.txt | 16 ++
> .../controller/hisilicon,hi6220-sysctrl.txt | 19 ++
> .../controller/hisilicon,hip01-sysctrl.txt | 19 ++
> .../controller/hisilicon,hip04-bootwrapper.txt | 9 +
> .../controller/hisilicon,hip04-fabric.txt | 5 +
> .../controller/hisilicon,pcie-sas-subctrl.txt | 15 ++
> .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 +
> .../controller/hisilicon,peri-subctrl.txt | 16 ++
> .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ++
> .../bindings/arm/hisilicon/hisilicon.txt | 262 ---------------------
> 16 files changed, 235 insertions(+), 262 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
> new file mode 100644
> index 000000000000000..ceffac537671668
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
> @@ -0,0 +1,8 @@
> +Hisilicon CPU controller
> +
> +Required properties:
> +- compatible : "hisilicon,cpuctrl"
> +- reg : Register address and size
> +
> +The clock registers and power registers of secondary cores are defined
> +in CPU controller, especially in HIX5HD2 SoC.
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
> new file mode 100644
> index 000000000000000..4d1c6abf03f6f97
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
> @@ -0,0 +1,15 @@
> +Hisilicon HiP05/HiP06 DSA sub system controller
> +
> +Required properties:
> +- compatible : "hisilicon,dsa-subctrl", "syscon";
This and others with only 'reg' can just be moved to syscon.yaml.
> +- reg : Register address and size
> +
> +The DSA sub system controller is shared by peripheral controllers in
> +HiP05 or HiP06 Soc to implement some basic configurations.
> +
> +Example:
> + /* for HiP05 dsa sub system */
> + pcie_sas: system_controller@a0000000 {
> + compatible = "hisilicon,dsa-subctrl", "syscon";
> + reg = <0xa0000000 0x10000>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
> new file mode 100644
> index 000000000000000..0d5282f4670658d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
> @@ -0,0 +1,21 @@
> +Hisilicon Hi3798CV200 Peripheral Controller
> +
> +The Hi3798CV200 Peripheral Controller controls peripherals, queries
> +their status, and configures some functions of peripherals.
> +
> +Required properties:
> +- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
> + and "simple-mfd".
> +- reg: Register address and size of Peripheral Controller.
> +- #address-cells: Should be 1.
> +- #size-cells: Should be 1.
> +
> +Examples:
> +
> + perictrl: peripheral-controller@8a20000 {
> + compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
> + "simple-mfd";
> + reg = <0x8a20000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt
> new file mode 100644
> index 000000000000000..5a723c1d45f4a17
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt
> @@ -0,0 +1,18 @@
> +Hisilicon Hi6220 Power Always ON domain controller
> +
> +Required properties:
> +- compatible : "hisilicon,hi6220-aoctrl"
> +- reg : Register address and size
> +- #clock-cells: should be set to 1, many clock registers are defined
> + under this controller and this property must be present.
> +
> +Hisilicon designs this system controller to control the power always
> +on domain for mobile platform.
> +
> +Example:
> + /*for Hi6220*/
> + ao_ctrl: ao_ctrl@f7800000 {
> + compatible = "hisilicon,hi6220-aoctrl", "syscon";
> + reg = <0x0 0xf7800000 0x0 0x2000>;
> + #clock-cells = <1>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt
> new file mode 100644
> index 000000000000000..dcfdcbcb6455771
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt
> @@ -0,0 +1,18 @@
> +Hisilicon Hi6220 Media domain controller
> +
> +Required properties:
> +- compatible : "hisilicon,hi6220-mediactrl"
> +- reg : Register address and size
> +- #clock-cells: should be set to 1, many clock registers are defined
> + under this controller and this property must be present.
> +
> +Hisilicon designs this system controller to control the multimedia
> +domain(e.g. codec, G3D ...) for mobile platform.
> +
> +Example:
> + /*for Hi6220*/
> + media_ctrl: media_ctrl@f4410000 {
> + compatible = "hisilicon,hi6220-mediactrl", "syscon";
> + reg = <0x0 0xf4410000 0x0 0x1000>;
> + #clock-cells = <1>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt
> new file mode 100644
> index 000000000000000..972842f07b5a2ce
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt
> @@ -0,0 +1,18 @@
> +Hisilicon Hi6220 Power Management domain controller
> +
> +Required properties:
> +- compatible : "hisilicon,hi6220-pmctrl"
> +- reg : Register address and size
> +- #clock-cells: should be set to 1, some clock registers are define
> + under this controller and this property must be present.
> +
> +Hisilicon designs this system controller to control the power management
> +domain for mobile platform.
> +
> +Example:
> + /*for Hi6220*/
> + pm_ctrl: pm_ctrl@f7032000 {
> + compatible = "hisilicon,hi6220-pmctrl", "syscon";
> + reg = <0x0 0xf7032000 0x0 0x1000>;
> + #clock-cells = <1>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt
> new file mode 100644
> index 000000000000000..086b7acccc5edc4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt
> @@ -0,0 +1,16 @@
> +Hisilicon Hi6220 SRAM controller
> +
> +Required properties:
> +- compatible : "hisilicon,hi6220-sramctrl", "syscon"
> +- reg : Register address and size
> +
> +Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
> +SRAM banks for power management, modem, security, etc. Further, use "syscon"
> +managing the common sram which can be shared by multiple modules.
> +
> +Example:
> + /*for Hi6220*/
> + sram: sram@fff80000 {
> + compatible = "hisilicon,hi6220-sramctrl", "syscon";
> + reg = <0x0 0xfff80000 0x0 0x12000>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
> new file mode 100644
> index 000000000000000..07e318eda254f52
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
> @@ -0,0 +1,19 @@
> +Hisilicon Hi6220 system controller
> +
> +Required properties:
> +- compatible : "hisilicon,hi6220-sysctrl"
> +- reg : Register address and size
> +- #clock-cells: should be set to 1, many clock registers are defined
> + under this controller and this property must be present.
> +
> +Hisilicon designs this controller as one of the system controllers,
> +its main functions are the same as Hisilicon system controller, but
> +the register offset of some core modules are different.
> +
> +Example:
> + /*for Hi6220*/
> + sys_ctrl: sys_ctrl@f7030000 {
> + compatible = "hisilicon,hi6220-sysctrl", "syscon";
> + reg = <0x0 0xf7030000 0x0 0x2000>;
> + #clock-cells = <1>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
> new file mode 100644
> index 000000000000000..db2dfdce799db91
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
> @@ -0,0 +1,19 @@
> +Hisilicon HiP01 system controller
> +
> +Required properties:
> +- compatible : "hisilicon,hip01-sysctrl"
> +- reg : Register address and size
> +
> +The HiP01 system controller is mostly compatible with hisilicon
> +system controller,but it has some specific control registers for
> +HIP01 SoC family, such as slave core boot, and also some same
> +registers located at different offset.
> +
> +Example:
> +
> + /* for hip01-ca9x2 */
> + sysctrl: system-controller@10000000 {
> + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
> + reg = <0x10000000 0x1000>;
> + reboot-offset = <0x4>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt
> new file mode 100644
> index 000000000000000..b0d53333f4fdae1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt
> @@ -0,0 +1,9 @@
> +Bootwrapper boot method (software protocol on SMP):
> +
> +Required Properties:
> +- compatible: "hisilicon,hip04-bootwrapper";
> +- boot-method: Address and size of boot method.
> + [0]: bootwrapper physical address
> + [1]: bootwrapper size
> + [2]: relocation physical address
> + [3]: relocation size
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt
> new file mode 100644
> index 000000000000000..40453d02f2024bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt
> @@ -0,0 +1,5 @@
> +Fabric:
> +
> +Required Properties:
> +- compatible: "hisilicon,hip04-fabric";
> +- reg: Address and size of Fabric
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
> new file mode 100644
> index 000000000000000..1ef086bda81a3f5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
> @@ -0,0 +1,15 @@
> +Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
> +
> +Required properties:
> +- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
> +- reg : Register address and size
> +
> +The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
> +HiP05 or HiP06 Soc to implement some basic configurations.
> +
> +Example:
> + /* for HiP05 PCIe-SAS sub system */
> + pcie_sas: system_controller@b0000000 {
> + compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> + reg = <0xb0000000 0x10000>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt
> new file mode 100644
> index 000000000000000..deec777bc3a850a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt
> @@ -0,0 +1,13 @@
> +PCTRL: Peripheral misc control register
> +
> +Required Properties:
> +- compatible: "hisilicon,pctrl"
> +- reg: Address and size of pctrl.
> +
> +Example:
> +
> + /* for Hi3620 */
> + pctrl: pctrl@fca09000 {
> + compatible = "hisilicon,pctrl";
> + reg = <0xfca09000 0x1000>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt
> new file mode 100644
> index 000000000000000..b96c2896078b914
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt
> @@ -0,0 +1,16 @@
> +Hisilicon HiP05/HiP06 PERI sub system controller
> +
> +Required properties:
> +- compatible : "hisilicon,peri-subctrl", "syscon";
> +- reg : Register address and size
> +
> +The PERI sub system controller is shared by peripheral controllers in
> +HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
> +controllers include mdio, ddr, iic, uart, timer and so on.
> +
> +Example:
> + /* for HiP05 sub peri system */
> + peri_c_subctrl: syscon@80000000 {
> + compatible = "hisilicon,peri-subctrl", "syscon";
> + reg = <0x0 0x80000000 0x0 0x10000>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
> new file mode 100644
> index 000000000000000..963f7f1ca7a2f0c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
> @@ -0,0 +1,25 @@
> +Hisilicon system controller
> +
> +Required properties:
> +- compatible : "hisilicon,sysctrl"
> +- reg : Register address and size
> +
> +Optional properties:
> +- smp-offset : offset in sysctrl for notifying slave cpu booting
> + cpu 1, reg;
> + cpu 2, reg + 0x4;
> + cpu 3, reg + 0x8;
> + If reg value is not zero, cpun exit wfi and go
> +- resume-offset : offset in sysctrl for notifying cpu0 when resume
> +- reboot-offset : offset in sysctrl for system reboot
> +
> +Example:
> +
> + /* for Hi3620 */
> + sysctrl: system-controller@fc802000 {
> + compatible = "hisilicon,sysctrl";
> + reg = <0xfc802000 0x1000>;
> + smp-offset = <0x31c>;
> + resume-offset = <0x308>;
> + reboot-offset = <0x4>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> index a97f643e7d1c760..ffe760a636b5e7f 100644
> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> @@ -55,265 +55,3 @@ Required root node properties:
> HiP07 D05 Board
> Required root node properties:
> - compatible = "hisilicon,hip07-d05";
> -
> -Hisilicon system controller
> -
> -Required properties:
> -- compatible : "hisilicon,sysctrl"
> -- reg : Register address and size
> -
> -Optional properties:
> -- smp-offset : offset in sysctrl for notifying slave cpu booting
> - cpu 1, reg;
> - cpu 2, reg + 0x4;
> - cpu 3, reg + 0x8;
> - If reg value is not zero, cpun exit wfi and go
> -- resume-offset : offset in sysctrl for notifying cpu0 when resume
> -- reboot-offset : offset in sysctrl for system reboot
> -
> -Example:
> -
> - /* for Hi3620 */
> - sysctrl: system-controller@fc802000 {
> - compatible = "hisilicon,sysctrl";
> - reg = <0xfc802000 0x1000>;
> - smp-offset = <0x31c>;
> - resume-offset = <0x308>;
> - reboot-offset = <0x4>;
> - };
> -
> ------------------------------------------------------------------------
> -Hisilicon Hi3798CV200 Peripheral Controller
> -
> -The Hi3798CV200 Peripheral Controller controls peripherals, queries
> -their status, and configures some functions of peripherals.
> -
> -Required properties:
> -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
> - and "simple-mfd".
> -- reg: Register address and size of Peripheral Controller.
> -- #address-cells: Should be 1.
> -- #size-cells: Should be 1.
> -
> -Examples:
> -
> - perictrl: peripheral-controller@8a20000 {
> - compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
> - "simple-mfd";
> - reg = <0x8a20000 0x1000>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - };
> -
> ------------------------------------------------------------------------
> -Hisilicon Hi6220 system controller
> -
> -Required properties:
> -- compatible : "hisilicon,hi6220-sysctrl"
> -- reg : Register address and size
> -- #clock-cells: should be set to 1, many clock registers are defined
> - under this controller and this property must be present.
> -
> -Hisilicon designs this controller as one of the system controllers,
> -its main functions are the same as Hisilicon system controller, but
> -the register offset of some core modules are different.
> -
> -Example:
> - /*for Hi6220*/
> - sys_ctrl: sys_ctrl@f7030000 {
> - compatible = "hisilicon,hi6220-sysctrl", "syscon";
> - reg = <0x0 0xf7030000 0x0 0x2000>;
> - #clock-cells = <1>;
> - };
> -
> -
> -Hisilicon Hi6220 Power Always ON domain controller
> -
> -Required properties:
> -- compatible : "hisilicon,hi6220-aoctrl"
> -- reg : Register address and size
> -- #clock-cells: should be set to 1, many clock registers are defined
> - under this controller and this property must be present.
> -
> -Hisilicon designs this system controller to control the power always
> -on domain for mobile platform.
> -
> -Example:
> - /*for Hi6220*/
> - ao_ctrl: ao_ctrl@f7800000 {
> - compatible = "hisilicon,hi6220-aoctrl", "syscon";
> - reg = <0x0 0xf7800000 0x0 0x2000>;
> - #clock-cells = <1>;
> - };
> -
> -
> -Hisilicon Hi6220 Media domain controller
> -
> -Required properties:
> -- compatible : "hisilicon,hi6220-mediactrl"
> -- reg : Register address and size
> -- #clock-cells: should be set to 1, many clock registers are defined
> - under this controller and this property must be present.
> -
> -Hisilicon designs this system controller to control the multimedia
> -domain(e.g. codec, G3D ...) for mobile platform.
> -
> -Example:
> - /*for Hi6220*/
> - media_ctrl: media_ctrl@f4410000 {
> - compatible = "hisilicon,hi6220-mediactrl", "syscon";
> - reg = <0x0 0xf4410000 0x0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> -
> -Hisilicon Hi6220 Power Management domain controller
> -
> -Required properties:
> -- compatible : "hisilicon,hi6220-pmctrl"
> -- reg : Register address and size
> -- #clock-cells: should be set to 1, some clock registers are define
> - under this controller and this property must be present.
> -
> -Hisilicon designs this system controller to control the power management
> -domain for mobile platform.
> -
> -Example:
> - /*for Hi6220*/
> - pm_ctrl: pm_ctrl@f7032000 {
> - compatible = "hisilicon,hi6220-pmctrl", "syscon";
> - reg = <0x0 0xf7032000 0x0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> -
> -Hisilicon Hi6220 SRAM controller
> -
> -Required properties:
> -- compatible : "hisilicon,hi6220-sramctrl", "syscon"
> -- reg : Register address and size
> -
> -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
> -SRAM banks for power management, modem, security, etc. Further, use "syscon"
> -managing the common sram which can be shared by multiple modules.
> -
> -Example:
> - /*for Hi6220*/
> - sram: sram@fff80000 {
> - compatible = "hisilicon,hi6220-sramctrl", "syscon";
> - reg = <0x0 0xfff80000 0x0 0x12000>;
> - };
> -
> ------------------------------------------------------------------------
> -Hisilicon HiP01 system controller
> -
> -Required properties:
> -- compatible : "hisilicon,hip01-sysctrl"
> -- reg : Register address and size
> -
> -The HiP01 system controller is mostly compatible with hisilicon
> -system controller,but it has some specific control registers for
> -HIP01 SoC family, such as slave core boot, and also some same
> -registers located at different offset.
> -
> -Example:
> -
> - /* for hip01-ca9x2 */
> - sysctrl: system-controller@10000000 {
> - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
> - reg = <0x10000000 0x1000>;
> - reboot-offset = <0x4>;
> - };
> -
> ------------------------------------------------------------------------
> -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
> -
> -Required properties:
> -- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
> -- reg : Register address and size
> -
> -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
> -HiP05 or HiP06 Soc to implement some basic configurations.
> -
> -Example:
> - /* for HiP05 PCIe-SAS sub system */
> - pcie_sas: system_controller@b0000000 {
> - compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> - reg = <0xb0000000 0x10000>;
> - };
> -
> -Hisilicon HiP05/HiP06 PERI sub system controller
> -
> -Required properties:
> -- compatible : "hisilicon,peri-subctrl", "syscon";
> -- reg : Register address and size
> -
> -The PERI sub system controller is shared by peripheral controllers in
> -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
> -controllers include mdio, ddr, iic, uart, timer and so on.
> -
> -Example:
> - /* for HiP05 sub peri system */
> - peri_c_subctrl: syscon@80000000 {
> - compatible = "hisilicon,peri-subctrl", "syscon";
> - reg = <0x0 0x80000000 0x0 0x10000>;
> - };
> -
> -Hisilicon HiP05/HiP06 DSA sub system controller
> -
> -Required properties:
> -- compatible : "hisilicon,dsa-subctrl", "syscon";
> -- reg : Register address and size
> -
> -The DSA sub system controller is shared by peripheral controllers in
> -HiP05 or HiP06 Soc to implement some basic configurations.
> -
> -Example:
> - /* for HiP05 dsa sub system */
> - pcie_sas: system_controller@a0000000 {
> - compatible = "hisilicon,dsa-subctrl", "syscon";
> - reg = <0xa0000000 0x10000>;
> - };
> -
> ------------------------------------------------------------------------
> -Hisilicon CPU controller
> -
> -Required properties:
> -- compatible : "hisilicon,cpuctrl"
> -- reg : Register address and size
> -
> -The clock registers and power registers of secondary cores are defined
> -in CPU controller, especially in HIX5HD2 SoC.
> -
> ------------------------------------------------------------------------
> -PCTRL: Peripheral misc control register
> -
> -Required Properties:
> -- compatible: "hisilicon,pctrl"
> -- reg: Address and size of pctrl.
> -
> -Example:
> -
> - /* for Hi3620 */
> - pctrl: pctrl@fca09000 {
> - compatible = "hisilicon,pctrl";
> - reg = <0xfca09000 0x1000>;
> - };
> -
> ------------------------------------------------------------------------
> -Fabric:
> -
> -Required Properties:
> -- compatible: "hisilicon,hip04-fabric";
> -- reg: Address and size of Fabric
> -
> ------------------------------------------------------------------------
> -Bootwrapper boot method (software protocol on SMP):
> -
> -Required Properties:
> -- compatible: "hisilicon,hip04-bootwrapper";
> -- boot-method: Address and size of boot method.
> - [0]: bootwrapper physical address
> - [1]: bootwrapper size
> - [2]: relocation physical address
> - [3]: relocation size
> --
> 1.8.3
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 02/20] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema
2020-09-28 15:13 ` [PATCH v4 02/20] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema Zhen Lei
@ 2020-09-28 19:06 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2020-09-28 19:06 UTC (permalink / raw)
To: Zhen Lei
Cc: devicetree, linux-kernel, Libin, Kefeng Wang, Wei Xu,
Jonathan Cameron, linux-arm-kernel, Rob Herring
On Mon, 28 Sep 2020 23:13:06 +0800, Zhen Lei wrote:
> Convert Hisilicon SoC bindings to DT schema format using json-schema.
>
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
> .../bindings/arm/hisilicon/hisilicon.txt | 57 --------------------
> .../bindings/arm/hisilicon/hisilicon.yaml | 62 ++++++++++++++++++++++
> 2 files changed, 62 insertions(+), 57 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 03/20] dt-bindings: arm: hisilicon: add binding for SD5203 SoC
2020-09-28 15:13 ` [PATCH v4 03/20] dt-bindings: arm: hisilicon: add binding for SD5203 SoC Zhen Lei
@ 2020-09-28 19:07 ` Rob Herring
2020-09-29 3:05 ` Leizhen (ThunderTown)
0 siblings, 1 reply; 36+ messages in thread
From: Rob Herring @ 2020-09-28 19:07 UTC (permalink / raw)
To: Zhen Lei
Cc: Wei Xu, Jonathan Cameron, devicetree, linux-arm-kernel,
linux-kernel, Libin, Kefeng Wang
On Mon, Sep 28, 2020 at 11:13:07PM +0800, Zhen Lei wrote:
> Add devicetree binding for Hisilicon SD5203 SoC.
>
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
> Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
> index 6d17309c7c84308..3337eebc61da812 100644
> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
> @@ -59,4 +59,8 @@ properties:
> - description: HiP07 D05 Board
> items:
> - const: hisilicon,hip07-d05
> +
> + - description: SD5203 Board
This should be a board compatible and then a SoC compatible.
> + items:
> + - const: hisilicon,sd5203
> ...
> --
> 1.8.3
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 07/20] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema
2020-09-28 15:13 ` [PATCH v4 07/20] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema Zhen Lei
@ 2020-09-28 19:13 ` Rob Herring
2020-09-29 3:09 ` Leizhen (ThunderTown)
0 siblings, 1 reply; 36+ messages in thread
From: Rob Herring @ 2020-09-28 19:13 UTC (permalink / raw)
To: Zhen Lei
Cc: Wei Xu, Jonathan Cameron, devicetree, linux-arm-kernel,
linux-kernel, Libin, Kefeng Wang
On Mon, Sep 28, 2020 at 11:13:11PM +0800, Zhen Lei wrote:
> Convert the Hisilicon system controller and its variants binding to DT
> schema format using json-schema. All of them are grouped into one yaml
> file, to help users understand differences and avoid repeated
> descriptions.
>
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
> .../controller/hisilicon,hi6220-sysctrl.txt | 19 ----
> .../controller/hisilicon,hip01-sysctrl.txt | 19 ----
> .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 -----
> .../hisilicon/controller/hisilicon,sysctrl.yaml | 115 +++++++++++++++++++++
> .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ---
> 5 files changed, 115 insertions(+), 77 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml
> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
> deleted file mode 100644
> index 07e318eda254f52..000000000000000
> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -Hisilicon Hi6220 system controller
> -
> -Required properties:
> -- compatible : "hisilicon,hi6220-sysctrl"
> -- reg : Register address and size
> -- #clock-cells: should be set to 1, many clock registers are defined
> - under this controller and this property must be present.
> -
> -Hisilicon designs this controller as one of the system controllers,
> -its main functions are the same as Hisilicon system controller, but
> -the register offset of some core modules are different.
> -
> -Example:
> - /*for Hi6220*/
> - sys_ctrl: sys_ctrl@f7030000 {
> - compatible = "hisilicon,hi6220-sysctrl", "syscon";
> - reg = <0x0 0xf7030000 0x0 0x2000>;
> - #clock-cells = <1>;
> - };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
> deleted file mode 100644
> index db2dfdce799db91..000000000000000
> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -Hisilicon HiP01 system controller
> -
> -Required properties:
> -- compatible : "hisilicon,hip01-sysctrl"
> -- reg : Register address and size
> -
> -The HiP01 system controller is mostly compatible with hisilicon
> -system controller,but it has some specific control registers for
> -HIP01 SoC family, such as slave core boot, and also some same
> -registers located at different offset.
> -
> -Example:
> -
> - /* for hip01-ca9x2 */
> - sysctrl: system-controller@10000000 {
> - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
> - reg = <0x10000000 0x1000>;
> - reboot-offset = <0x4>;
> - };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
> deleted file mode 100644
> index 963f7f1ca7a2f0c..000000000000000
> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -Hisilicon system controller
> -
> -Required properties:
> -- compatible : "hisilicon,sysctrl"
> -- reg : Register address and size
> -
> -Optional properties:
> -- smp-offset : offset in sysctrl for notifying slave cpu booting
> - cpu 1, reg;
> - cpu 2, reg + 0x4;
> - cpu 3, reg + 0x8;
> - If reg value is not zero, cpun exit wfi and go
> -- resume-offset : offset in sysctrl for notifying cpu0 when resume
> -- reboot-offset : offset in sysctrl for system reboot
> -
> -Example:
> -
> - /* for Hi3620 */
> - sysctrl: system-controller@fc802000 {
> - compatible = "hisilicon,sysctrl";
> - reg = <0xfc802000 0x1000>;
> - smp-offset = <0x31c>;
> - resume-offset = <0x308>;
> - reboot-offset = <0x4>;
> - };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml
> new file mode 100644
> index 000000000000000..37b214e0a401d7d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,sysctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Hisilicon system controller
> +
> +maintainers:
> + - Wei Xu <xuwei5@hisilicon.com>
> +
> +description: |
> + The Hisilicon system controller is used on many Hisilicon boards, it can be
> + used to assist the slave core startup, reboot the system, etc.
> +
> + There are some variants of the Hisilicon system controller, such as HiP01,
> + Hi3519, Hi6220 system controller, each of them is mostly compatible with the
> + Hisilicon system controller, but some same registers located at different
> + offset. In addition, the HiP01 system controller has some specific control
> + registers for HIP01 SoC family, such as slave core boot.
> +
> + The compatible names of each system controller are as follows:
> + Hisilicon system controller --> hisilicon,sysctrl
> + HiP01 system controller --> hisilicon,hip01-sysctrl
> + Hi6220 system controller --> hisilicon,hi6220-sysctrl
> + Hi3519 system controller --> hisilicon,hi3519-sysctrl
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: hisilicon,hi6220-sysctrl
> + then:
> + required:
> + - '#clock-cells'
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: hisilicon,sysctrl
> + - items:
> + - const: hisilicon,sysctrl
> + - const: syscon
Of these 2, the 1st case should be fixed (add 'syscon' in the dts
files).
> + - items:
> + - const: hisilicon,hip01-sysctrl
> + - const: hisilicon,sysctrl
> + - items:
> + - const: hisilicon,hi6220-sysctrl
> + - const: syscon
> + - items:
> + - const: hisilicon,hi3519-sysctrl
> + - const: syscon
All the cases with 'syscon' can be a single entry. Use 'enum' for the
1st string.
> +
> + reg:
> + description: Register address and size
That's every 'reg' property. Drop it.
> + maxItems: 1
> +
> + smp-offset:
> + description: |
> + offset in sysctrl for notifying slave cpu booting
> + cpu 1, reg;
> + cpu 2, reg + 0x4;
> + cpu 3, reg + 0x8;
> + If reg value is not zero, cpun exit wfi and go
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + resume-offset:
> + description: offset in sysctrl for notifying cpu0 when resume
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + reboot-offset:
> + description: offset in sysctrl for system reboot
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + '#clock-cells':
> + description: the number of cells occupied by one clock ID.
Drop.
> + const: 1
> +
> +required:
> + - compatible
> + - reg
additionalProperties: false
(and in other patches)
> +
> +examples:
> + - |
> + /* Hisilicon system controller */
> + system-controller@fc802000 {
> + compatible = "hisilicon,sysctrl";
> + reg = <0xfc802000 0x1000>;
> + smp-offset = <0x31c>;
> + resume-offset = <0x308>;
> + reboot-offset = <0x4>;
> + };
> +
> + /* HiP01 system controller */
> + system-controller@10000000 {
> + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
> + reg = <0x10000000 0x1000>;
> + reboot-offset = <0x4>;
> + };
> +
> + /* Hi6220 system controller */
> + system-controller@f7030000 {
> + compatible = "hisilicon,hi6220-sysctrl", "syscon";
> + reg = <0xf7030000 0x2000>;
> + #clock-cells = <1>;
> + };
> +
> + /* Hi3519 system controller */
> + system-controller@12010000 {
> + compatible = "hisilicon,hi3519-sysctrl", "syscon";
> + reg = <0x12010000 0x1000>;
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
> deleted file mode 100644
> index 8defacc44dd5b9e..000000000000000
> --- a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -* Hisilicon Hi3519 System Controller Block
> -
> -This bindings use the following binding:
> -Documentation/devicetree/bindings/mfd/syscon.yaml
> -
> -Required properties:
> -- compatible: "hisilicon,hi3519-sysctrl".
> -- reg: the register region of this block
> -
> -Examples:
> -sysctrl: system-controller@12010000 {
> - compatible = "hisilicon,hi3519-sysctrl", "syscon";
> - reg = <0x12010000 0x1000>;
> -};
> --
> 1.8.3
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings to json-schema
2020-09-28 15:13 ` [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl " Zhen Lei
@ 2020-09-28 19:14 ` Rob Herring
2020-09-29 3:18 ` Leizhen (ThunderTown)
0 siblings, 1 reply; 36+ messages in thread
From: Rob Herring @ 2020-09-28 19:14 UTC (permalink / raw)
To: Zhen Lei
Cc: Wei Xu, Jonathan Cameron, devicetree, linux-arm-kernel,
linux-kernel, Libin, Kefeng Wang
On Mon, Sep 28, 2020 at 11:13:16PM +0800, Zhen Lei wrote:
> Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT
> schema format using json-schema.
>
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
> .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ----------
> .../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++++++++++++++++++++++
> 2 files changed, 45 insertions(+), 21 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
> deleted file mode 100644
> index 0d5282f4670658d..000000000000000
> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -Hisilicon Hi3798CV200 Peripheral Controller
> -
> -The Hi3798CV200 Peripheral Controller controls peripherals, queries
> -their status, and configures some functions of peripherals.
> -
> -Required properties:
> -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
> - and "simple-mfd".
> -- reg: Register address and size of Peripheral Controller.
> -- #address-cells: Should be 1.
> -- #size-cells: Should be 1.
> -
> -Examples:
> -
> - perictrl: peripheral-controller@8a20000 {
> - compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
> - "simple-mfd";
> - reg = <0x8a20000 0x1000>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - };
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
> new file mode 100644
> index 000000000000000..4e547017e368393
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Hisilicon Hi3798CV200 Peripheral Controller
> +
> +maintainers:
> + - Wei Xu <xuwei5@hisilicon.com>
> +
> +description: |
> + The Hi3798CV200 Peripheral Controller controls peripherals, queries
> + their status, and configures some functions of peripherals.
> +
> +properties:
> + compatible:
> + items:
> + - const: hisilicon,hi3798cv200-perictrl
> + - const: syscon
> + - const: simple-mfd
> +
> + reg:
> + description: Register address and size
> + maxItems: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 1
That implies child nodes. You need some sort of schema for them.
> +
> +required:
> + - compatible
> + - reg
> +
> +examples:
> + - |
> + perictrl: peripheral-controller@8a20000 {
> + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd";
> + reg = <0x8a20000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +...
> --
> 1.8.3
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 20/20] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema
2020-09-28 15:13 ` [PATCH v4 20/20] dt-bindings: arm: hisilicon: convert LPC controller " Zhen Lei
@ 2020-09-28 19:16 ` Rob Herring
2020-09-29 3:11 ` Leizhen (ThunderTown)
0 siblings, 1 reply; 36+ messages in thread
From: Rob Herring @ 2020-09-28 19:16 UTC (permalink / raw)
To: Zhen Lei
Cc: Wei Xu, Jonathan Cameron, devicetree, linux-arm-kernel,
linux-kernel, Libin, Kefeng Wang
On Mon, Sep 28, 2020 at 11:13:24PM +0800, Zhen Lei wrote:
> Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC)
> controller binding to DT schema format using json-schema.
>
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
> .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------
> .../arm/hisilicon/hisilicon-low-pin-count.yaml | 61 ++++++++++++++++++++++
> 2 files changed, 61 insertions(+), 33 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
> deleted file mode 100644
> index 10bd35f9207f2ee..000000000000000
> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -Hisilicon Hip06 Low Pin Count device
> - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
> - provides I/O access to some legacy ISA devices.
> - Hip06 is based on arm64 architecture where there is no I/O space. So, the
> - I/O ports here are not CPU addresses, and there is no 'ranges' property in
> - LPC device node.
> -
> -Required properties:
> -- compatible: value should be as follows:
> - (a) "hisilicon,hip06-lpc"
> - (b) "hisilicon,hip07-lpc"
> -- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
> -- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
> -- reg: base memory range where the LPC register set is mapped.
> -
> -Note:
> - The node name before '@' must be "isa" to represent the binding stick to the
> - ISA/EISA binding specification.
> -
> -Example:
> -
> -isa@a01b0000 {
> - compatible = "hisilicon,hip06-lpc";
> - #address-cells = <2>;
> - #size-cells = <1>;
> - reg = <0x0 0xa01b0000 0x0 0x1000>;
> -
> - ipmi0: bt@e4 {
> - compatible = "ipmi-bt";
> - device_type = "ipmi";
> - reg = <0x01 0xe4 0x04>;
> - };
> -};
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
> new file mode 100644
> index 000000000000000..83ca10adce71b62
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon-low-pin-count.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Hisilicon Hip06 Low Pin Count device
> +
> +maintainers:
> + - Wei Xu <xuwei5@hisilicon.com>
> +
> +description: |
> + Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
> + provides I/O access to some legacy ISA devices.
> + Hip06 is based on arm64 architecture where there is no I/O space. So, the
> + I/O ports here are not CPU addresses, and there is no 'ranges' property in
> + LPC device node.
> +
> +properties:
> + $nodename:
> + pattern: '^isa@[0-9a-f]+$'
> + description: |
> + The node name before '@' must be "isa" to represent the binding stick
> + to the ISA/EISA binding specification.
> +
> + compatible:
> + enum:
> + - hisilicon,hip06-lpc
> + - hisilicon,hip07-lpc
> +
> + reg:
> + description: base memory range where the LPC register set is mapped.
Drop description.
> + maxItems: 1
> +
> + '#address-cells':
> + description: must be 2 which stick to the ISA/EISA binding doc.
Drop.
> + const: 2
> +
> + '#size-cells':
> + description: must be 1 which stick to the ISA/EISA binding doc.
Drop.
> + const: 1
> +
> +required:
> + - compatible
> + - reg
additionalProperties:
type: object
> +
> +examples:
> + - |
> + isa@a01b0000 {
> + compatible = "hisilicon,hip06-lpc";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + reg = <0xa01b0000 0x1000>;
> +
> + ipmi0: bt@e4 {
> + compatible = "ipmi-bt";
> + device_type = "ipmi";
> + reg = <0x01 0xe4 0x04>;
> + };
> + };
> +...
> --
> 1.8.3
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 01/20] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file
2020-09-28 19:05 ` Rob Herring
@ 2020-09-29 3:05 ` Leizhen (ThunderTown)
0 siblings, 0 replies; 36+ messages in thread
From: Leizhen (ThunderTown) @ 2020-09-29 3:05 UTC (permalink / raw)
To: Rob Herring
Cc: Wei Xu, Jonathan Cameron, devicetree, linux-arm-kernel,
linux-kernel, Libin, Kefeng Wang
On 2020/9/29 3:05, Rob Herring wrote:
> On Mon, Sep 28, 2020 at 11:13:05PM +0800, Zhen Lei wrote:
>> Split the devicetree bindings of each Hisilicon controller from
>> hisilicon.txt into a separate file, the file name is the compatible name
>> attach the .txt file name extension.
>>
>> All Hi6220 dedicated controllers are grouped into subdirectory "hi3620".
>> All HiPxx dedicated controllers are grouped into subdirectory "hipxx"
>>
>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>> ---
>> .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 +
>> .../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 ++
>> .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ++
>> .../controller/hisilicon,hi6220-aoctrl.txt | 18 ++
>> .../controller/hisilicon,hi6220-mediactrl.txt | 18 ++
>> .../controller/hisilicon,hi6220-pmctrl.txt | 18 ++
>> .../controller/hisilicon,hi6220-sramctrl.txt | 16 ++
>> .../controller/hisilicon,hi6220-sysctrl.txt | 19 ++
>> .../controller/hisilicon,hip01-sysctrl.txt | 19 ++
>> .../controller/hisilicon,hip04-bootwrapper.txt | 9 +
>> .../controller/hisilicon,hip04-fabric.txt | 5 +
>> .../controller/hisilicon,pcie-sas-subctrl.txt | 15 ++
>> .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 +
>> .../controller/hisilicon,peri-subctrl.txt | 16 ++
>> .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ++
>> .../bindings/arm/hisilicon/hisilicon.txt | 262 ---------------------
>> 16 files changed, 235 insertions(+), 262 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
>> new file mode 100644
>> index 000000000000000..ceffac537671668
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt
>> @@ -0,0 +1,8 @@
>> +Hisilicon CPU controller
>> +
>> +Required properties:
>> +- compatible : "hisilicon,cpuctrl"
>> +- reg : Register address and size
>> +
>> +The clock registers and power registers of secondary cores are defined
>> +in CPU controller, especially in HIX5HD2 SoC.
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
>> new file mode 100644
>> index 000000000000000..4d1c6abf03f6f97
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt
>> @@ -0,0 +1,15 @@
>> +Hisilicon HiP05/HiP06 DSA sub system controller
>> +
>> +Required properties:
>> +- compatible : "hisilicon,dsa-subctrl", "syscon";
>
> This and others with only 'reg' can just be moved to syscon.yaml.
OK, I will do it.
>
>> +- reg : Register address and size
>> +
>> +The DSA sub system controller is shared by peripheral controllers in
>> +HiP05 or HiP06 Soc to implement some basic configurations.
>> +
>> +Example:
>> + /* for HiP05 dsa sub system */
>> + pcie_sas: system_controller@a0000000 {
>> + compatible = "hisilicon,dsa-subctrl", "syscon";
>> + reg = <0xa0000000 0x10000>;
>> + };
...
>
> .
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 03/20] dt-bindings: arm: hisilicon: add binding for SD5203 SoC
2020-09-28 19:07 ` Rob Herring
@ 2020-09-29 3:05 ` Leizhen (ThunderTown)
0 siblings, 0 replies; 36+ messages in thread
From: Leizhen (ThunderTown) @ 2020-09-29 3:05 UTC (permalink / raw)
To: Rob Herring
Cc: Wei Xu, Jonathan Cameron, devicetree, linux-arm-kernel,
linux-kernel, Libin, Kefeng Wang
On 2020/9/29 3:07, Rob Herring wrote:
> On Mon, Sep 28, 2020 at 11:13:07PM +0800, Zhen Lei wrote:
>> Add devicetree binding for Hisilicon SD5203 SoC.
>>
>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>> ---
>> Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
>> index 6d17309c7c84308..3337eebc61da812 100644
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
>> @@ -59,4 +59,8 @@ properties:
>> - description: HiP07 D05 Board
>> items:
>> - const: hisilicon,hip07-d05
>> +
>> + - description: SD5203 Board
>
> This should be a board compatible and then a SoC compatible.
OK, I will fix it.
>
>> + items:
>> + - const: hisilicon,sd5203
>> ...
>> --
>> 1.8.3
>>
>>
>
> .
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 07/20] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema
2020-09-28 19:13 ` Rob Herring
@ 2020-09-29 3:09 ` Leizhen (ThunderTown)
0 siblings, 0 replies; 36+ messages in thread
From: Leizhen (ThunderTown) @ 2020-09-29 3:09 UTC (permalink / raw)
To: Rob Herring
Cc: Wei Xu, Jonathan Cameron, devicetree, linux-arm-kernel,
linux-kernel, Libin, Kefeng Wang
On 2020/9/29 3:13, Rob Herring wrote:
> On Mon, Sep 28, 2020 at 11:13:11PM +0800, Zhen Lei wrote:
>> Convert the Hisilicon system controller and its variants binding to DT
>> schema format using json-schema. All of them are grouped into one yaml
>> file, to help users understand differences and avoid repeated
>> descriptions.
>>
>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>> ---
>> .../controller/hisilicon,hi6220-sysctrl.txt | 19 ----
>> .../controller/hisilicon,hip01-sysctrl.txt | 19 ----
>> .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 -----
>> .../hisilicon/controller/hisilicon,sysctrl.yaml | 115 +++++++++++++++++++++
>> .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 ---
>> 5 files changed, 115 insertions(+), 77 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
>> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
>> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml
>> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
>> deleted file mode 100644
>> index 07e318eda254f52..000000000000000
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt
>> +++ /dev/null
>> @@ -1,19 +0,0 @@
>> -Hisilicon Hi6220 system controller
>> -
>> -Required properties:
>> -- compatible : "hisilicon,hi6220-sysctrl"
>> -- reg : Register address and size
>> -- #clock-cells: should be set to 1, many clock registers are defined
>> - under this controller and this property must be present.
>> -
>> -Hisilicon designs this controller as one of the system controllers,
>> -its main functions are the same as Hisilicon system controller, but
>> -the register offset of some core modules are different.
>> -
>> -Example:
>> - /*for Hi6220*/
>> - sys_ctrl: sys_ctrl@f7030000 {
>> - compatible = "hisilicon,hi6220-sysctrl", "syscon";
>> - reg = <0x0 0xf7030000 0x0 0x2000>;
>> - #clock-cells = <1>;
>> - };
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
>> deleted file mode 100644
>> index db2dfdce799db91..000000000000000
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt
>> +++ /dev/null
>> @@ -1,19 +0,0 @@
>> -Hisilicon HiP01 system controller
>> -
>> -Required properties:
>> -- compatible : "hisilicon,hip01-sysctrl"
>> -- reg : Register address and size
>> -
>> -The HiP01 system controller is mostly compatible with hisilicon
>> -system controller,but it has some specific control registers for
>> -HIP01 SoC family, such as slave core boot, and also some same
>> -registers located at different offset.
>> -
>> -Example:
>> -
>> - /* for hip01-ca9x2 */
>> - sysctrl: system-controller@10000000 {
>> - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
>> - reg = <0x10000000 0x1000>;
>> - reboot-offset = <0x4>;
>> - };
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
>> deleted file mode 100644
>> index 963f7f1ca7a2f0c..000000000000000
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt
>> +++ /dev/null
>> @@ -1,25 +0,0 @@
>> -Hisilicon system controller
>> -
>> -Required properties:
>> -- compatible : "hisilicon,sysctrl"
>> -- reg : Register address and size
>> -
>> -Optional properties:
>> -- smp-offset : offset in sysctrl for notifying slave cpu booting
>> - cpu 1, reg;
>> - cpu 2, reg + 0x4;
>> - cpu 3, reg + 0x8;
>> - If reg value is not zero, cpun exit wfi and go
>> -- resume-offset : offset in sysctrl for notifying cpu0 when resume
>> -- reboot-offset : offset in sysctrl for system reboot
>> -
>> -Example:
>> -
>> - /* for Hi3620 */
>> - sysctrl: system-controller@fc802000 {
>> - compatible = "hisilicon,sysctrl";
>> - reg = <0xfc802000 0x1000>;
>> - smp-offset = <0x31c>;
>> - resume-offset = <0x308>;
>> - reboot-offset = <0x4>;
>> - };
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml
>> new file mode 100644
>> index 000000000000000..37b214e0a401d7d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml
>> @@ -0,0 +1,115 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,sysctrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Hisilicon system controller
>> +
>> +maintainers:
>> + - Wei Xu <xuwei5@hisilicon.com>
>> +
>> +description: |
>> + The Hisilicon system controller is used on many Hisilicon boards, it can be
>> + used to assist the slave core startup, reboot the system, etc.
>> +
>> + There are some variants of the Hisilicon system controller, such as HiP01,
>> + Hi3519, Hi6220 system controller, each of them is mostly compatible with the
>> + Hisilicon system controller, but some same registers located at different
>> + offset. In addition, the HiP01 system controller has some specific control
>> + registers for HIP01 SoC family, such as slave core boot.
>> +
>> + The compatible names of each system controller are as follows:
>> + Hisilicon system controller --> hisilicon,sysctrl
>> + HiP01 system controller --> hisilicon,hip01-sysctrl
>> + Hi6220 system controller --> hisilicon,hi6220-sysctrl
>> + Hi3519 system controller --> hisilicon,hi3519-sysctrl
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: hisilicon,hi6220-sysctrl
>> + then:
>> + required:
>> + - '#clock-cells'
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - items:
>> + - const: hisilicon,sysctrl
>> + - items:
>> + - const: hisilicon,sysctrl
>> + - const: syscon
>
> Of these 2, the 1st case should be fixed (add 'syscon' in the dts
> files).
OK, I will fix it.
>
>> + - items:
>> + - const: hisilicon,hip01-sysctrl
>> + - const: hisilicon,sysctrl
>> + - items:
>> + - const: hisilicon,hi6220-sysctrl
>> + - const: syscon
>> + - items:
>> + - const: hisilicon,hi3519-sysctrl
>> + - const: syscon
>
> All the cases with 'syscon' can be a single entry. Use 'enum' for the
> 1st string.
OK, I will do it.
>
>> +
>> + reg:
>> + description: Register address and size
>
> That's every 'reg' property. Drop it.
OK, I will drop the description.
>
>> + maxItems: 1
>> +
>> + smp-offset:
>> + description: |
>> + offset in sysctrl for notifying slave cpu booting
>> + cpu 1, reg;
>> + cpu 2, reg + 0x4;
>> + cpu 3, reg + 0x8;
>> + If reg value is not zero, cpun exit wfi and go
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> +
>> + resume-offset:
>> + description: offset in sysctrl for notifying cpu0 when resume
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> +
>> + reboot-offset:
>> + description: offset in sysctrl for system reboot
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> +
>> + '#clock-cells':
>> + description: the number of cells occupied by one clock ID.
>
> Drop.
OK, I will drop the description.
>
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>
> additionalProperties: false
>
> (and in other patches)
OK, I will do it.
>
>> +
>> +examples:
>> + - |
>> + /* Hisilicon system controller */
>> + system-controller@fc802000 {
>> + compatible = "hisilicon,sysctrl";
>> + reg = <0xfc802000 0x1000>;
>> + smp-offset = <0x31c>;
>> + resume-offset = <0x308>;
>> + reboot-offset = <0x4>;
>> + };
>> +
>> + /* HiP01 system controller */
>> + system-controller@10000000 {
>> + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
>> + reg = <0x10000000 0x1000>;
>> + reboot-offset = <0x4>;
>> + };
>> +
>> + /* Hi6220 system controller */
>> + system-controller@f7030000 {
>> + compatible = "hisilicon,hi6220-sysctrl", "syscon";
>> + reg = <0xf7030000 0x2000>;
>> + #clock-cells = <1>;
>> + };
>> +
>> + /* Hi3519 system controller */
>> + system-controller@12010000 {
>> + compatible = "hisilicon,hi3519-sysctrl", "syscon";
>> + reg = <0x12010000 0x1000>;
>> + };
>> +...
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
>> deleted file mode 100644
>> index 8defacc44dd5b9e..000000000000000
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
>> +++ /dev/null
>> @@ -1,14 +0,0 @@
>> -* Hisilicon Hi3519 System Controller Block
>> -
>> -This bindings use the following binding:
>> -Documentation/devicetree/bindings/mfd/syscon.yaml
>> -
>> -Required properties:
>> -- compatible: "hisilicon,hi3519-sysctrl".
>> -- reg: the register region of this block
>> -
>> -Examples:
>> -sysctrl: system-controller@12010000 {
>> - compatible = "hisilicon,hi3519-sysctrl", "syscon";
>> - reg = <0x12010000 0x1000>;
>> -};
>> --
>> 1.8.3
>>
>>
>
> .
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 20/20] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema
2020-09-28 19:16 ` Rob Herring
@ 2020-09-29 3:11 ` Leizhen (ThunderTown)
0 siblings, 0 replies; 36+ messages in thread
From: Leizhen (ThunderTown) @ 2020-09-29 3:11 UTC (permalink / raw)
To: Rob Herring
Cc: Wei Xu, Jonathan Cameron, devicetree, linux-arm-kernel,
linux-kernel, Libin, Kefeng Wang
On 2020/9/29 3:16, Rob Herring wrote:
> On Mon, Sep 28, 2020 at 11:13:24PM +0800, Zhen Lei wrote:
>> Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC)
>> controller binding to DT schema format using json-schema.
>>
>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>> ---
>> .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------
>> .../arm/hisilicon/hisilicon-low-pin-count.yaml | 61 ++++++++++++++++++++++
>> 2 files changed, 61 insertions(+), 33 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
>> deleted file mode 100644
>> index 10bd35f9207f2ee..000000000000000
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
>> +++ /dev/null
>> @@ -1,33 +0,0 @@
>> -Hisilicon Hip06 Low Pin Count device
>> - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
>> - provides I/O access to some legacy ISA devices.
>> - Hip06 is based on arm64 architecture where there is no I/O space. So, the
>> - I/O ports here are not CPU addresses, and there is no 'ranges' property in
>> - LPC device node.
>> -
>> -Required properties:
>> -- compatible: value should be as follows:
>> - (a) "hisilicon,hip06-lpc"
>> - (b) "hisilicon,hip07-lpc"
>> -- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
>> -- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
>> -- reg: base memory range where the LPC register set is mapped.
>> -
>> -Note:
>> - The node name before '@' must be "isa" to represent the binding stick to the
>> - ISA/EISA binding specification.
>> -
>> -Example:
>> -
>> -isa@a01b0000 {
>> - compatible = "hisilicon,hip06-lpc";
>> - #address-cells = <2>;
>> - #size-cells = <1>;
>> - reg = <0x0 0xa01b0000 0x0 0x1000>;
>> -
>> - ipmi0: bt@e4 {
>> - compatible = "ipmi-bt";
>> - device_type = "ipmi";
>> - reg = <0x01 0xe4 0x04>;
>> - };
>> -};
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
>> new file mode 100644
>> index 000000000000000..83ca10adce71b62
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml
>> @@ -0,0 +1,61 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon-low-pin-count.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Hisilicon Hip06 Low Pin Count device
>> +
>> +maintainers:
>> + - Wei Xu <xuwei5@hisilicon.com>
>> +
>> +description: |
>> + Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
>> + provides I/O access to some legacy ISA devices.
>> + Hip06 is based on arm64 architecture where there is no I/O space. So, the
>> + I/O ports here are not CPU addresses, and there is no 'ranges' property in
>> + LPC device node.
>> +
>> +properties:
>> + $nodename:
>> + pattern: '^isa@[0-9a-f]+$'
>> + description: |
>> + The node name before '@' must be "isa" to represent the binding stick
>> + to the ISA/EISA binding specification.
>> +
>> + compatible:
>> + enum:
>> + - hisilicon,hip06-lpc
>> + - hisilicon,hip07-lpc
>> +
>> + reg:
>> + description: base memory range where the LPC register set is mapped.
>
> Drop description.
OK
>
>> + maxItems: 1
>> +
>> + '#address-cells':
>> + description: must be 2 which stick to the ISA/EISA binding doc.
>
> Drop.
OK
>
>> + const: 2
>> +
>> + '#size-cells':
>> + description: must be 1 which stick to the ISA/EISA binding doc.
>
> Drop.
OK
>
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>
> additionalProperties:
> type: object
OK, I will add it.
>
>> +
>> +examples:
>> + - |
>> + isa@a01b0000 {
>> + compatible = "hisilicon,hip06-lpc";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + reg = <0xa01b0000 0x1000>;
>> +
>> + ipmi0: bt@e4 {
>> + compatible = "ipmi-bt";
>> + device_type = "ipmi";
>> + reg = <0x01 0xe4 0x04>;
>> + };
>> + };
>> +...
>> --
>> 1.8.3
>>
>>
>
> .
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings to json-schema
2020-09-28 19:14 ` Rob Herring
@ 2020-09-29 3:18 ` Leizhen (ThunderTown)
2020-09-29 9:21 ` Leizhen (ThunderTown)
0 siblings, 1 reply; 36+ messages in thread
From: Leizhen (ThunderTown) @ 2020-09-29 3:18 UTC (permalink / raw)
To: Rob Herring
Cc: Wei Xu, Jonathan Cameron, devicetree, linux-arm-kernel,
linux-kernel, Libin, Kefeng Wang
On 2020/9/29 3:14, Rob Herring wrote:
> On Mon, Sep 28, 2020 at 11:13:16PM +0800, Zhen Lei wrote:
>> Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT
>> schema format using json-schema.
>>
>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>> ---
>> .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ----------
>> .../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++++++++++++++++++++++
>> 2 files changed, 45 insertions(+), 21 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>> deleted file mode 100644
>> index 0d5282f4670658d..000000000000000
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>> +++ /dev/null
>> @@ -1,21 +0,0 @@
>> -Hisilicon Hi3798CV200 Peripheral Controller
>> -
>> -The Hi3798CV200 Peripheral Controller controls peripherals, queries
>> -their status, and configures some functions of peripherals.
>> -
>> -Required properties:
>> -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
>> - and "simple-mfd".
>> -- reg: Register address and size of Peripheral Controller.
>> -- #address-cells: Should be 1.
>> -- #size-cells: Should be 1.
>> -
>> -Examples:
>> -
>> - perictrl: peripheral-controller@8a20000 {
>> - compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
>> - "simple-mfd";
>> - reg = <0x8a20000 0x1000>;
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> - };
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>> new file mode 100644
>> index 000000000000000..4e547017e368393
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>> @@ -0,0 +1,45 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Hisilicon Hi3798CV200 Peripheral Controller
>> +
>> +maintainers:
>> + - Wei Xu <xuwei5@hisilicon.com>
>> +
>> +description: |
>> + The Hi3798CV200 Peripheral Controller controls peripherals, queries
>> + their status, and configures some functions of peripherals.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - const: hisilicon,hi3798cv200-perictrl
>> + - const: syscon
>> + - const: simple-mfd
>> +
>> + reg:
>> + description: Register address and size
>> + maxItems: 1
>> +
>> + '#address-cells':
>> + const: 1
>> +
>> + '#size-cells':
>> + const: 1
>
> That implies child nodes. You need some sort of schema for them.
OK, I will drop #address-cells and #size-cells in this binding.
>
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +examples:
>> + - |
>> + perictrl: peripheral-controller@8a20000 {
>> + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd";
>> + reg = <0x8a20000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + };
>> +...
>> --
>> 1.8.3
>>
>>
>
> .
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings to json-schema
2020-09-29 3:18 ` Leizhen (ThunderTown)
@ 2020-09-29 9:21 ` Leizhen (ThunderTown)
2020-09-29 13:25 ` Leizhen (ThunderTown)
0 siblings, 1 reply; 36+ messages in thread
From: Leizhen (ThunderTown) @ 2020-09-29 9:21 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Kefeng Wang, linux-kernel, Wei Xu, Libin,
Jonathan Cameron, linux-arm-kernel
On 2020/9/29 11:18, Leizhen (ThunderTown) wrote:
>
>
> On 2020/9/29 3:14, Rob Herring wrote:
>> On Mon, Sep 28, 2020 at 11:13:16PM +0800, Zhen Lei wrote:
>>> Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT
>>> schema format using json-schema.
>>>
>>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>>> ---
>>> .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ----------
>>> .../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++++++++++++++++++++++
>>> 2 files changed, 45 insertions(+), 21 deletions(-)
>>> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>>> deleted file mode 100644
>>> index 0d5282f4670658d..000000000000000
>>> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>>> +++ /dev/null
>>> @@ -1,21 +0,0 @@
>>> -Hisilicon Hi3798CV200 Peripheral Controller
>>> -
>>> -The Hi3798CV200 Peripheral Controller controls peripherals, queries
>>> -their status, and configures some functions of peripherals.
>>> -
>>> -Required properties:
>>> -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
>>> - and "simple-mfd".
>>> -- reg: Register address and size of Peripheral Controller.
>>> -- #address-cells: Should be 1.
>>> -- #size-cells: Should be 1.
>>> -
>>> -Examples:
>>> -
>>> - perictrl: peripheral-controller@8a20000 {
>>> - compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
>>> - "simple-mfd";
>>> - reg = <0x8a20000 0x1000>;
>>> - #address-cells = <1>;
>>> - #size-cells = <1>;
>>> - };
>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>>> new file mode 100644
>>> index 000000000000000..4e547017e368393
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>>> @@ -0,0 +1,45 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Hisilicon Hi3798CV200 Peripheral Controller
>>> +
>>> +maintainers:
>>> + - Wei Xu <xuwei5@hisilicon.com>
>>> +
>>> +description: |
>>> + The Hi3798CV200 Peripheral Controller controls peripherals, queries
>>> + their status, and configures some functions of peripherals.
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - const: hisilicon,hi3798cv200-perictrl
>>> + - const: syscon
>>> + - const: simple-mfd
>>> +
>>> + reg:
>>> + description: Register address and size
>>> + maxItems: 1
>>> +
>>> + '#address-cells':
>>> + const: 1
>>> +
>>> + '#size-cells':
>>> + const: 1
>>
>> That implies child nodes. You need some sort of schema for them.
>
> OK, I will drop #address-cells and #size-cells in this binding.
I think I misunderstood. I shoud describe child nodes here.
It's National Day the day after tomorrow, total eight days off. It's so hurry.
I'll give up this patch! And do it for v5.11
>
>>
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> +
>>> +examples:
>>> + - |
>>> + perictrl: peripheral-controller@8a20000 {
>>> + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd";
>>> + reg = <0x8a20000 0x1000>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + };
>>> +...
>>> --
>>> 1.8.3
>>>
>>>
>>
>> .
>>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> .
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings to json-schema
2020-09-29 9:21 ` Leizhen (ThunderTown)
@ 2020-09-29 13:25 ` Leizhen (ThunderTown)
2020-09-29 13:52 ` Rob Herring
0 siblings, 1 reply; 36+ messages in thread
From: Leizhen (ThunderTown) @ 2020-09-29 13:25 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Kefeng Wang, linux-kernel, Wei Xu, Libin,
Jonathan Cameron, linux-arm-kernel
On 2020/9/29 17:21, Leizhen (ThunderTown) wrote:
>
>
> On 2020/9/29 11:18, Leizhen (ThunderTown) wrote:
>>
>>
>> On 2020/9/29 3:14, Rob Herring wrote:
>>> On Mon, Sep 28, 2020 at 11:13:16PM +0800, Zhen Lei wrote:
>>>> Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT
>>>> schema format using json-schema.
>>>>
>>>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>>>> ---
>>>> .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ----------
>>>> .../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++++++++++++++++++++++
>>>> 2 files changed, 45 insertions(+), 21 deletions(-)
>>>> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>>>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>>>> deleted file mode 100644
>>>> index 0d5282f4670658d..000000000000000
>>>> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>>>> +++ /dev/null
>>>> @@ -1,21 +0,0 @@
>>>> -Hisilicon Hi3798CV200 Peripheral Controller
>>>> -
>>>> -The Hi3798CV200 Peripheral Controller controls peripherals, queries
>>>> -their status, and configures some functions of peripherals.
>>>> -
>>>> -Required properties:
>>>> -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
>>>> - and "simple-mfd".
>>>> -- reg: Register address and size of Peripheral Controller.
>>>> -- #address-cells: Should be 1.
>>>> -- #size-cells: Should be 1.
>>>> -
>>>> -Examples:
>>>> -
>>>> - perictrl: peripheral-controller@8a20000 {
>>>> - compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
>>>> - "simple-mfd";
>>>> - reg = <0x8a20000 0x1000>;
>>>> - #address-cells = <1>;
>>>> - #size-cells = <1>;
>>>> - };
>>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>>>> new file mode 100644
>>>> index 000000000000000..4e547017e368393
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>>>> @@ -0,0 +1,45 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Hisilicon Hi3798CV200 Peripheral Controller
>>>> +
>>>> +maintainers:
>>>> + - Wei Xu <xuwei5@hisilicon.com>
>>>> +
>>>> +description: |
>>>> + The Hi3798CV200 Peripheral Controller controls peripherals, queries
>>>> + their status, and configures some functions of peripherals.
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + items:
>>>> + - const: hisilicon,hi3798cv200-perictrl
>>>> + - const: syscon
>>>> + - const: simple-mfd
>>>> +
>>>> + reg:
>>>> + description: Register address and size
>>>> + maxItems: 1
>>>> +
>>>> + '#address-cells':
>>>> + const: 1
>>>> +
>>>> + '#size-cells':
>>>> + const: 1
>>>
>>> That implies child nodes. You need some sort of schema for them.
>>
>> OK, I will drop #address-cells and #size-cells in this binding.
>
> I think I misunderstood. I shoud describe child nodes here.
>
> It's National Day the day after tomorrow, total eight days off. It's so hurry.
> I'll give up this patch! And do it for v5.11
I searched the dtsi, these two properties are required by property "ranges", so
I will add it.
>
">>
>>>
>>>> +
>>>> +required:
>>>> + - compatible
>>>> + - reg
>>>> +
>>>> +examples:
>>>> + - |
>>>> + perictrl: peripheral-controller@8a20000 {
>>>> + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd";
>>>> + reg = <0x8a20000 0x1000>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + };
>>>> +...
>>>> --
>>>> 1.8.3
>>>>
>>>>
>>>
>>> .
>>>
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>> .
>>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> .
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings to json-schema
2020-09-29 13:25 ` Leizhen (ThunderTown)
@ 2020-09-29 13:52 ` Rob Herring
2020-09-30 1:59 ` Leizhen (ThunderTown)
0 siblings, 1 reply; 36+ messages in thread
From: Rob Herring @ 2020-09-29 13:52 UTC (permalink / raw)
To: Leizhen (ThunderTown)
Cc: devicetree, Kefeng Wang, linux-kernel, Wei Xu, Libin,
Jonathan Cameron, linux-arm-kernel
On Tue, Sep 29, 2020 at 8:25 AM Leizhen (ThunderTown)
<thunder.leizhen@huawei.com> wrote:
>
>
>
> On 2020/9/29 17:21, Leizhen (ThunderTown) wrote:
> >
> >
> > On 2020/9/29 11:18, Leizhen (ThunderTown) wrote:
> >>
> >>
> >> On 2020/9/29 3:14, Rob Herring wrote:
> >>> On Mon, Sep 28, 2020 at 11:13:16PM +0800, Zhen Lei wrote:
> >>>> Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT
> >>>> schema format using json-schema.
> >>>>
> >>>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> >>>> ---
> >>>> .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ----------
> >>>> .../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++++++++++++++++++++++
> >>>> 2 files changed, 45 insertions(+), 21 deletions(-)
> >>>> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
> >>>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
> >>>> deleted file mode 100644
> >>>> index 0d5282f4670658d..000000000000000
> >>>> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
> >>>> +++ /dev/null
> >>>> @@ -1,21 +0,0 @@
> >>>> -Hisilicon Hi3798CV200 Peripheral Controller
> >>>> -
> >>>> -The Hi3798CV200 Peripheral Controller controls peripherals, queries
> >>>> -their status, and configures some functions of peripherals.
> >>>> -
> >>>> -Required properties:
> >>>> -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
> >>>> - and "simple-mfd".
> >>>> -- reg: Register address and size of Peripheral Controller.
> >>>> -- #address-cells: Should be 1.
> >>>> -- #size-cells: Should be 1.
> >>>> -
> >>>> -Examples:
> >>>> -
> >>>> - perictrl: peripheral-controller@8a20000 {
> >>>> - compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
> >>>> - "simple-mfd";
> >>>> - reg = <0x8a20000 0x1000>;
> >>>> - #address-cells = <1>;
> >>>> - #size-cells = <1>;
> >>>> - };
> >>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
> >>>> new file mode 100644
> >>>> index 000000000000000..4e547017e368393
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
> >>>> @@ -0,0 +1,45 @@
> >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>>> +%YAML 1.2
> >>>> +---
> >>>> +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml#
> >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>> +
> >>>> +title: Hisilicon Hi3798CV200 Peripheral Controller
> >>>> +
> >>>> +maintainers:
> >>>> + - Wei Xu <xuwei5@hisilicon.com>
> >>>> +
> >>>> +description: |
> >>>> + The Hi3798CV200 Peripheral Controller controls peripherals, queries
> >>>> + their status, and configures some functions of peripherals.
> >>>> +
> >>>> +properties:
> >>>> + compatible:
> >>>> + items:
> >>>> + - const: hisilicon,hi3798cv200-perictrl
> >>>> + - const: syscon
> >>>> + - const: simple-mfd
> >>>> +
> >>>> + reg:
> >>>> + description: Register address and size
> >>>> + maxItems: 1
> >>>> +
> >>>> + '#address-cells':
> >>>> + const: 1
> >>>> +
> >>>> + '#size-cells':
> >>>> + const: 1
> >>>
> >>> That implies child nodes. You need some sort of schema for them.
> >>
> >> OK, I will drop #address-cells and #size-cells in this binding.
> >
> > I think I misunderstood. I shoud describe child nodes here.
> >
> > It's National Day the day after tomorrow, total eight days off. It's so hurry.
> > I'll give up this patch! And do it for v5.11
>
> I searched the dtsi, these two properties are required by property "ranges", so
> I will add it.
'ranges' also implies there are child nodes as does 'simple-mfd', so
whatever child nodes you have are missing and need to be documented
too. Also, 'ranges' implies the child nodes are memory-mapped, but
'simple-mfd' implies they are not. 'simple-bus' is what should be used
for memory-mapped children.
Rob
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings to json-schema
2020-09-29 13:52 ` Rob Herring
@ 2020-09-30 1:59 ` Leizhen (ThunderTown)
0 siblings, 0 replies; 36+ messages in thread
From: Leizhen (ThunderTown) @ 2020-09-30 1:59 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Kefeng Wang, linux-kernel, Wei Xu, Libin,
Jonathan Cameron, linux-arm-kernel
On 2020/9/29 21:52, Rob Herring wrote:
> On Tue, Sep 29, 2020 at 8:25 AM Leizhen (ThunderTown)
> <thunder.leizhen@huawei.com> wrote:
>>
>>
>>
>> On 2020/9/29 17:21, Leizhen (ThunderTown) wrote:
>>>
>>>
>>> On 2020/9/29 11:18, Leizhen (ThunderTown) wrote:
>>>>
>>>>
>>>> On 2020/9/29 3:14, Rob Herring wrote:
>>>>> On Mon, Sep 28, 2020 at 11:13:16PM +0800, Zhen Lei wrote:
>>>>>> Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT
>>>>>> schema format using json-schema.
>>>>>>
>>>>>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>>>>>> ---
>>>>>> .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ----------
>>>>>> .../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++++++++++++++++++++++
>>>>>> 2 files changed, 45 insertions(+), 21 deletions(-)
>>>>>> delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>>>>>> create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>>>>>> deleted file mode 100644
>>>>>> index 0d5282f4670658d..000000000000000
>>>>>> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt
>>>>>> +++ /dev/null
>>>>>> @@ -1,21 +0,0 @@
>>>>>> -Hisilicon Hi3798CV200 Peripheral Controller
>>>>>> -
>>>>>> -The Hi3798CV200 Peripheral Controller controls peripherals, queries
>>>>>> -their status, and configures some functions of peripherals.
>>>>>> -
>>>>>> -Required properties:
>>>>>> -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
>>>>>> - and "simple-mfd".
>>>>>> -- reg: Register address and size of Peripheral Controller.
>>>>>> -- #address-cells: Should be 1.
>>>>>> -- #size-cells: Should be 1.
>>>>>> -
>>>>>> -Examples:
>>>>>> -
>>>>>> - perictrl: peripheral-controller@8a20000 {
>>>>>> - compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
>>>>>> - "simple-mfd";
>>>>>> - reg = <0x8a20000 0x1000>;
>>>>>> - #address-cells = <1>;
>>>>>> - #size-cells = <1>;
>>>>>> - };
>>>>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>>>>>> new file mode 100644
>>>>>> index 000000000000000..4e547017e368393
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml
>>>>>> @@ -0,0 +1,45 @@
>>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>>> +%YAML 1.2
>>>>>> +---
>>>>>> +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml#
>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>>> +
>>>>>> +title: Hisilicon Hi3798CV200 Peripheral Controller
>>>>>> +
>>>>>> +maintainers:
>>>>>> + - Wei Xu <xuwei5@hisilicon.com>
>>>>>> +
>>>>>> +description: |
>>>>>> + The Hi3798CV200 Peripheral Controller controls peripherals, queries
>>>>>> + their status, and configures some functions of peripherals.
>>>>>> +
>>>>>> +properties:
>>>>>> + compatible:
>>>>>> + items:
>>>>>> + - const: hisilicon,hi3798cv200-perictrl
>>>>>> + - const: syscon
>>>>>> + - const: simple-mfd
>>>>>> +
>>>>>> + reg:
>>>>>> + description: Register address and size
>>>>>> + maxItems: 1
>>>>>> +
>>>>>> + '#address-cells':
>>>>>> + const: 1
>>>>>> +
>>>>>> + '#size-cells':
>>>>>> + const: 1
>>>>>
>>>>> That implies child nodes. You need some sort of schema for them.
>>>>
>>>> OK, I will drop #address-cells and #size-cells in this binding.
>>>
>>> I think I misunderstood. I shoud describe child nodes here.
>>>
>>> It's National Day the day after tomorrow, total eight days off. It's so hurry.
>>> I'll give up this patch! And do it for v5.11
>>
>> I searched the dtsi, these two properties are required by property "ranges", so
>> I will add it.
>
> 'ranges' also implies there are child nodes as does 'simple-mfd', so
> whatever child nodes you have are missing and need to be documented
> too. Also, 'ranges' implies the child nodes are memory-mapped, but
> 'simple-mfd' implies they are not. 'simple-bus' is what should be used
> for memory-mapped children.
Sorry, The reason for the jet lag, I went straight home after I sent the
version 5 of these patches last night after 10 p.m. I saw you had applied
the new one. Thanks for the information you showed me here.
>
> Rob
>
> .
>
^ permalink raw reply [flat|nested] 36+ messages in thread
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2020-09-28 15:13 [PATCH v4 00/20] add support for Hisilicon SD5203 SoC Zhen Lei
2020-09-28 15:13 ` [PATCH v4 01/20] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Zhen Lei
2020-09-28 19:05 ` Rob Herring
2020-09-29 3:05 ` Leizhen (ThunderTown)
2020-09-28 15:13 ` [PATCH v4 02/20] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema Zhen Lei
2020-09-28 19:06 ` Rob Herring
2020-09-28 15:13 ` [PATCH v4 03/20] dt-bindings: arm: hisilicon: add binding for SD5203 SoC Zhen Lei
2020-09-28 19:07 ` Rob Herring
2020-09-29 3:05 ` Leizhen (ThunderTown)
2020-09-28 15:13 ` [PATCH v4 04/20] ARM: hisi: add support " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 05/20] ARM: debug: add UART early console support for SD5203 Zhen Lei
2020-09-28 15:13 ` [PATCH v4 06/20] ARM: dts: add SD5203 dts Zhen Lei
2020-09-28 15:13 ` [PATCH v4 07/20] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema Zhen Lei
2020-09-28 19:13 ` Rob Herring
2020-09-29 3:09 ` Leizhen (ThunderTown)
2020-09-28 15:13 ` [PATCH v4 08/20] dt-bindings: arm: hisilicon: convert hisilicon,peri-subctrl " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 09/20] dt-bindings: arm: hisilicon: convert hisilicon,pcie-sas-subctrl " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 10/20] dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 11/20] dt-bindings: arm: hisilicon: convert hisilicon,pctrl " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl " Zhen Lei
2020-09-28 19:14 ` Rob Herring
2020-09-29 3:18 ` Leizhen (ThunderTown)
2020-09-29 9:21 ` Leizhen (ThunderTown)
2020-09-29 13:25 ` Leizhen (ThunderTown)
2020-09-29 13:52 ` Rob Herring
2020-09-30 1:59 ` Leizhen (ThunderTown)
2020-09-28 15:13 ` [PATCH v4 13/20] dt-bindings: arm: hisilicon: convert hisilicon,dsa-subctrl " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 14/20] dt-bindings: arm: hisilicon: convert hisilicon,hip04-fabric " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 15/20] dt-bindings: arm: hisilicon: convert hisilicon,hip04-bootwrapper " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 16/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-aoctrl " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 17/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-mediactrl " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 18/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-pmctrl " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 19/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-sramctrl " Zhen Lei
2020-09-28 15:13 ` [PATCH v4 20/20] dt-bindings: arm: hisilicon: convert LPC controller " Zhen Lei
2020-09-28 19:16 ` Rob Herring
2020-09-29 3:11 ` Leizhen (ThunderTown)
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