From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA642C4363D for ; Thu, 8 Oct 2020 00:32:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5DF54215A4 for ; Thu, 8 Oct 2020 00:32:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727655AbgJHAcn (ORCPT ); Wed, 7 Oct 2020 20:32:43 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:48954 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726323AbgJHAcn (ORCPT ); Wed, 7 Oct 2020 20:32:43 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kQJrN-000cMt-3I; Thu, 08 Oct 2020 02:32:41 +0200 Date: Thu, 8 Oct 2020 02:32:41 +0200 From: Andrew Lunn To: Vivek Unune Cc: devicetree@vger.kernel.org, Hauke Mehrtens , =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= , linux-kernel@vger.kernel.org, Rob Herring , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7 Message-ID: <20201008003241.GG112961@lunn.ch> References: <20201007210327.GE112961@lunn.ch> <20201007220718.GB1972@ubuntu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201007220718.GB1972@ubuntu> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > This router is currently not enabled in Openwrt You have to be careful here. Not everything runs OpenWRT. You cannot break backwards compatibility in mainline, simple as that. You need to ensure that mainline does not see a change in the CPU port. Andrew