[PATCH v3 0/3] Add board support for HK10 board variants

[PATCH v3 0/3] Add board support for HK10 board variants

[Gokul Sriram Palanisamy]

Added support for HK10-C1 and HK10-C2 board variants based on IPQ8074 SoC.
Both these variants support dual QCN9000 PCIe cards that uses MHI communication
protocol over PCIe. In addition, HK10-C1 support on-chip radio.
Both these variants slightly differ in clock configuation for ethernet.

This series depends on below series:
[V2,0/7] Add PCIe support for IPQ8074
[v7,0/9] remoteproc: qcom: q6v5-wcss: Add support for secure pil

changes since v2:
 - In patch 3, Moved pcie0_rp and pcie1_rp nodes and
   removed unused members and subnodes

Gokul Sriram Palanisamy (3):
  dt-bindings: qcom: Add ipq8074 bindings
  arm64: dts: Add board support for HK10
  arm64: dts: Enabled MHI device over PCIe

 Documentation/devicetree/bindings/arm/qcom.yaml |   4 +
 arch/arm64/boot/dts/qcom/Makefile               |   2 +
 arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts    |  11 +++
 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts    |  14 +++
 arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi      | 123 ++++++++++++++++++++++++
 5 files changed, 154 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi

-- 
2.7.4

[PATCH v3 1/3] dt-bindings: qcom: Add ipq8074 bindings

[Gokul Sriram Palanisamy]

Document the new device-tree bindings for boards
HK10-C1 and HK10-C2 based on ipq8074 SoC.

Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 6031aee..7b294be 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -47,6 +47,8 @@ description: |
         cp01-c1
         dragonboard
         hk01
+        hk10-c1
+        hk10-c2
         idp
         liquid
         mtp
@@ -148,6 +150,8 @@ properties:
       - items:
           - enum:
               - qcom,ipq8074-hk01
+              - qcom,ipq8074-hk10-c1
+              - qcom,ipq8074-hk10-c2
           - const: qcom,ipq8074
 
       - items:
-- 
2.7.4

[PATCH v3 2/3] arm64: dts: Add board support for HK10

[Gokul Sriram Palanisamy]

Add initial support for IPQ8074 SoC based HK10-C1
and HK10-C2 evaluation boards.

Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/Makefile            |  2 +
 arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts | 11 ++++
 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts | 14 +++++
 arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi   | 76 ++++++++++++++++++++++++++++
 4 files changed, 103 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index d8f1466..7e628fe 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -4,6 +4,8 @@ dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-db820c.dtb
 dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-longcheer-l8150.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-a3u-eur.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
new file mode 100644
index 0000000..2bfcf42
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+/dts-v1/;
+
+#include "ipq8074-hk10.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C1";
+	compatible = "qcom,ipq8074-hk10-c1", "qcom,ipq8074";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
new file mode 100644
index 0000000..1897e96
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+#include "ipq8074-hk10.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C2";
+	compatible = "qcom,ipq8074-hk10-c2", "qcom,ipq8074";
+};
+
+&q6v5_wcss {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
new file mode 100644
index 0000000..0827055
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+
+	interrupt-parent = <&intc>;
+
+	aliases {
+		serial0 = &blsp1_uart5;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0x20000000>;
+	};
+};
+
+&blsp1_spi1 {
+	status = "ok";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&blsp1_uart5 {
+	status = "ok";
+};
+
+&pcie0 {
+	status = "ok";
+	perst-gpio = <&tlmm 58 0x1>;
+};
+
+&pcie1 {
+	status = "ok";
+	perst-gpio = <&tlmm 61 0x1>;
+};
+
+&qmp_pcie_phy0 {
+	status = "ok";
+};
+
+&qmp_pcie_phy1 {
+	status = "ok";
+};
+
+&qpic_bam {
+	status = "ok";
+};
+
+&qpic_nand {
+	status = "ok";
+
+	nand@0 {
+		reg = <0>;
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+	};
+};
-- 
2.7.4

[PATCH v3 3/3] arm64: dts: Enabled MHI device over PCIe

[Gokul Sriram Palanisamy]

Enabled MHI device support over PCIe and added memory
reservation required for MHI enabled QCN9000 PCIe card.

Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 47 ++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
index 0827055..e5c1ec0 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -24,6 +24,22 @@
 		device_type = "memory";
 		reg = <0x0 0x40000000 0x0 0x20000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		qcn9000_pcie0: memory@50f00000 {
+			no-map;
+			reg = <0x0 0x50f00000 0x0 0x03700000>;
+		};
+
+		qcn9000_pcie1: memory@54600000 {
+			no-map;
+			reg = <0x0 0x54600000 0x0 0x03700000>;
+		};
+	};
 };
 
 &blsp1_spi1 {
@@ -45,11 +61,42 @@
 &pcie0 {
 	status = "ok";
 	perst-gpio = <&tlmm 58 0x1>;
+
+	pcie0_rp: pcie0_rp {
+		reg = <0 0 0 0 0>;
+
+		status = "ok";
+		mhi_0: qcom,mhi@0 {
+			reg = <0 0 0 0 0 >;
+
+			qrtr_instance_id = <0x20>;
+			base-addr = <0x50f00000>;
+			m3-dump-addr = <0x53c00000>;
+			etr-addr = <0x53d00000>;
+			qcom,caldb-addr = <0x53e00000>;
+		};
+	};
 };
 
 &pcie1 {
 	status = "ok";
 	perst-gpio = <&tlmm 61 0x1>;
+
+	pcie1_rp: pcie1_rp {
+		reg = <0 0 0 0 0>;
+
+		status = "ok";
+		mhi_1: qcom,mhi@1 {
+			reg = <0 0 0 0 0 >;
+
+			qrtr_instance_id = <0x21>;
+			base-addr = <0x54600000>;
+			m3-dump-addr = <0x57300000>;
+			etr-addr = <0x57400000>;
+			qcom,caldb-addr = <0x57500000>;
+			};
+		};
+	};
 };
 
 &qmp_pcie_phy0 {
-- 
2.7.4

Re: [PATCH v3 3/3] arm64: dts: Enabled MHI device over PCIe

[Manivannan Sadhasivam]

Hi,

On Thu, Oct 08, 2020 at 06:02:24PM +0530, Gokul Sriram Palanisamy wrote:
> Enabled MHI device support over PCIe and added memory
> reservation required for MHI enabled QCN9000 PCIe card.
> 
> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 47 ++++++++++++++++++++++++++++++
>  1 file changed, 47 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> index 0827055..e5c1ec0 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> @@ -24,6 +24,22 @@
>  		device_type = "memory";
>  		reg = <0x0 0x40000000 0x0 0x20000000>;
>  	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		qcn9000_pcie0: memory@50f00000 {
> +			no-map;
> +			reg = <0x0 0x50f00000 0x0 0x03700000>;
> +		};
> +
> +		qcn9000_pcie1: memory@54600000 {
> +			no-map;
> +			reg = <0x0 0x54600000 0x0 0x03700000>;
> +		};
> +	};
>  };
>  
>  &blsp1_spi1 {
> @@ -45,11 +61,42 @@
>  &pcie0 {
>  	status = "ok";
>  	perst-gpio = <&tlmm 58 0x1>;
> +
> +	pcie0_rp: pcie0_rp {
> +		reg = <0 0 0 0 0>;
> +
> +		status = "ok";
> +		mhi_0: qcom,mhi@0 {

MHI doesn't support devicetree as of now so how is this supposed to work?
Have you tested this series with mainline?

Thanks,
Mani

> +			reg = <0 0 0 0 0 >;
> +
> +			qrtr_instance_id = <0x20>;
> +			base-addr = <0x50f00000>;
> +			m3-dump-addr = <0x53c00000>;
> +			etr-addr = <0x53d00000>;
> +			qcom,caldb-addr = <0x53e00000>;
> +		};
> +	};
>  };
>  
>  &pcie1 {
>  	status = "ok";
>  	perst-gpio = <&tlmm 61 0x1>;
> +
> +	pcie1_rp: pcie1_rp {
> +		reg = <0 0 0 0 0>;
> +
> +		status = "ok";
> +		mhi_1: qcom,mhi@1 {
> +			reg = <0 0 0 0 0 >;
> +
> +			qrtr_instance_id = <0x21>;
> +			base-addr = <0x54600000>;
> +			m3-dump-addr = <0x57300000>;
> +			etr-addr = <0x57400000>;
> +			qcom,caldb-addr = <0x57500000>;
> +			};
> +		};
> +	};
>  };
>  
>  &qmp_pcie_phy0 {
> -- 
> 2.7.4
> 

Re: [PATCH v3 3/3] arm64: dts: Enabled MHI device over PCIe

[gokulsri]

On 2020-10-08 18:41, Manivannan Sadhasivam wrote:
> Hi,
> 
> On Thu, Oct 08, 2020 at 06:02:24PM +0530, Gokul Sriram Palanisamy 
> wrote:
>> Enabled MHI device support over PCIe and added memory
>> reservation required for MHI enabled QCN9000 PCIe card.
>> 
>> Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 47 
>> ++++++++++++++++++++++++++++++
>>  1 file changed, 47 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi 
>> b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
>> index 0827055..e5c1ec0 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
>> @@ -24,6 +24,22 @@
>>  		device_type = "memory";
>>  		reg = <0x0 0x40000000 0x0 0x20000000>;
>>  	};
>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		qcn9000_pcie0: memory@50f00000 {
>> +			no-map;
>> +			reg = <0x0 0x50f00000 0x0 0x03700000>;
>> +		};
>> +
>> +		qcn9000_pcie1: memory@54600000 {
>> +			no-map;
>> +			reg = <0x0 0x54600000 0x0 0x03700000>;
>> +		};
>> +	};
>>  };
>> 
>>  &blsp1_spi1 {
>> @@ -45,11 +61,42 @@
>>  &pcie0 {
>>  	status = "ok";
>>  	perst-gpio = <&tlmm 58 0x1>;
>> +
>> +	pcie0_rp: pcie0_rp {
>> +		reg = <0 0 0 0 0>;
>> +
>> +		status = "ok";
>> +		mhi_0: qcom,mhi@0 {
> 
> MHI doesn't support devicetree as of now so how is this supposed to 
> work?
> Have you tested this series with mainline?
> 
> Thanks,
> Mani
> 

  Hi Mani,
  This node entries will be consumed by ath11k driver and is not supposed 
to be consumed by mhi driver.
  And yes, it is tested on Mainline.

  Regards,
  Gokul

>> +			reg = <0 0 0 0 0 >;
>> +
>> +			qrtr_instance_id = <0x20>;
>> +			base-addr = <0x50f00000>;
>> +			m3-dump-addr = <0x53c00000>;
>> +			etr-addr = <0x53d00000>;
>> +			qcom,caldb-addr = <0x53e00000>;
>> +		};
>> +	};
>>  };
>> 
>>  &pcie1 {
>>  	status = "ok";
>>  	perst-gpio = <&tlmm 61 0x1>;
>> +
>> +	pcie1_rp: pcie1_rp {
>> +		reg = <0 0 0 0 0>;
>> +
>> +		status = "ok";
>> +		mhi_1: qcom,mhi@1 {
>> +			reg = <0 0 0 0 0 >;
>> +
>> +			qrtr_instance_id = <0x21>;
>> +			base-addr = <0x54600000>;
>> +			m3-dump-addr = <0x57300000>;
>> +			etr-addr = <0x57400000>;
>> +			qcom,caldb-addr = <0x57500000>;
>> +			};
>> +		};
>> +	};
>>  };
>> 
>>  &qmp_pcie_phy0 {
>> --
>> 2.7.4
>> 

Re: [PATCH v3 3/3] arm64: dts: Enabled MHI device over PCIe

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1709 bytes --]

Hi Gokul,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on v5.9-rc8]
[cannot apply to next-20201008]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Gokul-Sriram-Palanisamy/Add-board-support-for-HK10-board-variants/20201008-203356
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r006-20201008 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/d852c07655e85bfc07d8d3543698ce06e2ce62f8
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Gokul-Sriram-Palanisamy/Add-board-support-for-HK10-board-variants/20201008-203356
        git checkout d852c07655e85bfc07d8d3543698ce06e2ce62f8
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi:100.1-2 syntax error
   FATAL ERROR: Unable to parse input tree

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 32402 bytes --]

Re: [PATCH v3 3/3] arm64: dts: Enabled MHI device over PCIe

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1890 bytes --]

Hi Gokul,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on v5.9-rc8]
[cannot apply to next-20201008]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Gokul-Sriram-Palanisamy/Add-board-support-for-HK10-board-variants/20201008-203356
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r015-20201008 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 8da0df3d6dcc0dd42740be60b0da4ec201190904)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/0day-ci/linux/commit/d852c07655e85bfc07d8d3543698ce06e2ce62f8
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Gokul-Sriram-Palanisamy/Add-board-support-for-HK10-board-variants/20201008-203356
        git checkout d852c07655e85bfc07d8d3543698ce06e2ce62f8
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi:100.1-2 syntax error
>> FATAL ERROR: Unable to parse input tree

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 31805 bytes --]

Re: [PATCH v3 3/3] arm64: dts: Enabled MHI device over PCIe

[Manivannan Sadhasivam]

On Thu, Oct 08, 2020 at 11:03:42PM +0530, gokulsri@codeaurora.org wrote:
> On 2020-10-08 18:41, Manivannan Sadhasivam wrote:
> > Hi,
> > 
> > On Thu, Oct 08, 2020 at 06:02:24PM +0530, Gokul Sriram Palanisamy wrote:
> > > Enabled MHI device support over PCIe and added memory
> > > reservation required for MHI enabled QCN9000 PCIe card.
> > > 
> > > Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
> > > ---
> > >  arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 47
> > > ++++++++++++++++++++++++++++++
> > >  1 file changed, 47 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> > > b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> > > index 0827055..e5c1ec0 100644
> > > --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi

[...]

> > > +	pcie0_rp: pcie0_rp {
> > > +		reg = <0 0 0 0 0>;
> > > +
> > > +		status = "ok";
> > > +		mhi_0: qcom,mhi@0 {
> > 
> > MHI doesn't support devicetree as of now so how is this supposed to
> > work?
> > Have you tested this series with mainline?
> > 
> > Thanks,
> > Mani
> > 
> 
>  Hi Mani,
>  This node entries will be consumed by ath11k driver and is not supposed to
> be consumed by mhi driver.
>  And yes, it is tested on Mainline.
> 

Can you please point me to the relevant binding or the code which consumes this
change?

Also please explain what it does! For enabling MHI support over PCIe you don't
need this node at all. You just need to define the PCIe device ID in the ath11k
driver and that's it.

Adding Kalle to this thread...

Thanks,
Mani

>  Regards,
>  Gokul
> 
> > > +			reg = <0 0 0 0 0 >;
> > > +
> > > +			qrtr_instance_id = <0x20>;
> > > +			base-addr = <0x50f00000>;
> > > +			m3-dump-addr = <0x53c00000>;
> > > +			etr-addr = <0x53d00000>;
> > > +			qcom,caldb-addr = <0x53e00000>;
> > > +		};
> > > +	};
> > >  };
> > > 
> > >  &pcie1 {
> > >  	status = "ok";
> > >  	perst-gpio = <&tlmm 61 0x1>;
> > > +
> > > +	pcie1_rp: pcie1_rp {
> > > +		reg = <0 0 0 0 0>;
> > > +
> > > +		status = "ok";
> > > +		mhi_1: qcom,mhi@1 {
> > > +			reg = <0 0 0 0 0 >;
> > > +
> > > +			qrtr_instance_id = <0x21>;
> > > +			base-addr = <0x54600000>;
> > > +			m3-dump-addr = <0x57300000>;
> > > +			etr-addr = <0x57400000>;
> > > +			qcom,caldb-addr = <0x57500000>;
> > > +			};
> > > +		};
> > > +	};
> > >  };
> > > 
> > >  &qmp_pcie_phy0 {
> > > --
> > > 2.7.4
> > > 

Re: [PATCH v3 3/3] arm64: dts: Enabled MHI device over PCIe

[Kalle Valo]

+ ath11k list

Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> writes:

> On Thu, Oct 08, 2020 at 11:03:42PM +0530, gokulsri@codeaurora.org wrote:
>> On 2020-10-08 18:41, Manivannan Sadhasivam wrote:
>> > Hi,
>> > 
>> > On Thu, Oct 08, 2020 at 06:02:24PM +0530, Gokul Sriram Palanisamy wrote:
>> > > Enabled MHI device support over PCIe and added memory
>> > > reservation required for MHI enabled QCN9000 PCIe card.
>> > > 
>> > > Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
>> > > ---
>> > >  arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 47
>> > > ++++++++++++++++++++++++++++++
>> > >  1 file changed, 47 insertions(+)
>> > > 
>> > > diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
>> > > b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
>> > > index 0827055..e5c1ec0 100644
>> > > --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
>> > > +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
>
> [...]
>
>> > > +	pcie0_rp: pcie0_rp {
>> > > +		reg = <0 0 0 0 0>;
>> > > +
>> > > +		status = "ok";
>> > > +		mhi_0: qcom,mhi@0 {
>> > 
>> > MHI doesn't support devicetree as of now so how is this supposed to
>> > work?
>> > Have you tested this series with mainline?
>> > 
>> > Thanks,
>> > Mani
>> > 
>> 
>>  Hi Mani,
>>  This node entries will be consumed by ath11k driver and is not supposed to
>> be consumed by mhi driver.
>>  And yes, it is tested on Mainline.

Upstream ath11k does not yet support QCN9074 so I don't see how this is
tested with mainline ath11k. You must be using some out-of-tree
_unofficial_ ath11k patches.

> Can you please point me to the relevant binding or the code which consumes this
> change?
>
> Also please explain what it does! For enabling MHI support over PCIe you don't
> need this node at all. You just need to define the PCIe device ID in the ath11k
> driver and that's it.
>
> Adding Kalle to this thread...

So currently QCN9074 firmware needs 55 MB of contiguous host memory and
I suspect one reason for these DT entries is an ugly hack to provide
that memory range to the firmware.

We are currently preparing QCN9074 patches for ath11k and finding a
solution how to implement these properly in ath11k. Hopefully there's no
need for hacks like this, we know more once we get the ath11k QCN9074
patches ready. Please drop this patch.

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