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From: Arnd Bergmann <arnd@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Marc Zyngier <maz@kernel.org>, Stephen Boyd <swboyd@chromium.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	stable@vger.kernel.org, Marc Zyngier <marc.zyngier@arm.com>,
	Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
	Steven Price <steven.price@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 1/4] arm64: cpu_errata: fix override-init warnings
Date: Mon, 26 Oct 2020 17:03:28 +0100	[thread overview]
Message-ID: <20201026160342.3705327-1-arnd@kernel.org> (raw)

From: Arnd Bergmann <arnd@arndb.de>

The CPU table causes a handful of warnings because of fields that
have more than one initializer, e.g.

arch/arm64/kernel/cpu_errata.c:127:13: warning: initialized field overwritten [-Woverride-init]
  127 |  .matches = is_affected_midr_range,   \
      |             ^~~~~~~~~~~~~~~~~~~~~~
arch/arm64/kernel/cpu_errata.c:139:2: note: in expansion of macro 'CAP_MIDR_RANGE'
  139 |  CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
      |  ^~~~~~~~~~~~~~
arch/arm64/kernel/cpu_errata.c:151:2: note: in expansion of macro 'ERRATA_MIDR_RANGE'
  151 |  ERRATA_MIDR_RANGE(model, var, rev, var, rev)
      |  ^~~~~~~~~~~~~~~~~
arch/arm64/kernel/cpu_errata.c:317:3: note: in expansion of macro 'ERRATA_MIDR_REV'
  317 |   ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
      |   ^~~~~~~~~~~~~~~

Address all of these by removing the extra initializer that
has no effect on the output.

Fixes: 1cf45b8fdbb8 ("arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 core")
Fixes: bf87bb0881d0 ("arm64: Allow booting of late CPUs affected by erratum 1418040")
Fixes: 93916beb7014 ("arm64: Enable workaround for Cavium TX2 erratum 219 when running SMT")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm64/kernel/cpu_errata.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 24d75af344b1..2321f52e396f 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -307,13 +307,11 @@ static const struct midr_range erratum_845719_list[] = {
 static const struct arm64_cpu_capabilities erratum_843419_list[] = {
 	{
 		/* Cortex-A53 r0p[01234] */
-		.matches = is_affected_midr_range,
 		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
 		MIDR_FIXED(0x4, BIT(8)),
 	},
 	{
 		/* Brahma-B53 r0p[0] */
-		.matches = is_affected_midr_range,
 		ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
 	},
 	{},
@@ -475,7 +473,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 	{
 		.desc = "ARM erratum 1418040",
 		.capability = ARM64_WORKAROUND_1418040,
-		ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
+		CAP_MIDR_RANGE_LIST(erratum_1418040_list),
 		/*
 		 * We need to allow affected CPUs to come in late, but
 		 * also need the non-affected CPUs to be able to come
@@ -504,8 +502,8 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 	{
 		.desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
 		.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
-		ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
 		.matches = needs_tx2_tvm_workaround,
+		.midr_range_list = tx2_family_cpus,
 	},
 	{
 		.desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
-- 
2.27.0


             reply	other threads:[~2020-10-26 16:04 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-26 16:03 Arnd Bergmann [this message]
2020-10-26 16:03 ` [PATCH 2/4] arm64: hide more compat_vdso code Arnd Bergmann
2020-10-26 16:55   ` Mark Rutland
2020-10-29 13:35     ` Arnd Bergmann
2020-10-29 13:54       ` Dmitry Safonov
2020-10-26 16:03 ` [PATCH 3/4] arm64: avoid -Woverride-init warning Arnd Bergmann
2020-10-26 17:01   ` Mark Rutland
2020-10-26 19:30     ` Arnd Bergmann
2020-10-26 16:03 ` [PATCH 4/4] arm64: traps: fix -Woverride-init warnings Arnd Bergmann
2020-10-26 16:23   ` Mark Rutland
2020-10-26 16:31     ` Arnd Bergmann
2020-10-26 17:13     ` Peter Maydell
2020-10-26 17:27       ` Will Deacon
2020-10-26 19:28         ` Arnd Bergmann
2020-10-26 20:45           ` Will Deacon

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