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From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <robh+dt@kernel.org>,
	<bhelgaas@google.com>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <amanharitsh123@gmail.com>,
	<dinghao.liu@zju.edu.cn>, <kw@linux.com>
Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
	<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
	<sagar.tv@gmail.com>
Subject: [PATCH V2 2/4] PCI: tegra: Map configuration space as nGnRnE
Date: Thu, 29 Oct 2020 10:48:37 +0530	[thread overview]
Message-ID: <20201029051839.11245-3-vidyas@nvidia.com> (raw)
In-Reply-To: <20201029051839.11245-1-vidyas@nvidia.com>

As specified in the comment for pci_remap_cfgspace() define in
arch/arm64/include/asm/io.h file, PCIe configuration space should be
mapped as nGnRnE. Hence changing to dev_pci_remap_cfgspace() from
devm_ioremap_resource() for mapping DBI space as that is nothing but
the root port's own configuration space.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* Changed 'Strongly Ordered' to 'nGnRnE'

 drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index b172b1d49713..7a0c64436861 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2108,7 +2108,9 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
 	}
 	pcie->dbi_res = dbi_res;
 
-	pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
+	pci->dbi_base = devm_pci_remap_cfgspace(dev,
+						dbi_res->start,
+						resource_size(dbi_res));
 	if (IS_ERR(pci->dbi_base))
 		return PTR_ERR(pci->dbi_base);
 
-- 
2.17.1


  parent reply	other threads:[~2020-10-29  8:39 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-29  5:18 [PATCH V2 0/4] Enhancements to Tegra194 PCIe driver Vidya Sagar
2020-10-29  5:18 ` [PATCH V2 1/4] PCI: tegra: Fix ASPM-L1SS advertisement disable code Vidya Sagar
2020-10-29  5:18 ` Vidya Sagar [this message]
2020-10-29  5:18 ` [PATCH V2 3/4] PCI: tegra: Set DesignWare IP version Vidya Sagar
2020-10-29  5:18 ` [PATCH V2 4/4] PCI: tegra: Handle error conditions properly Vidya Sagar
2020-11-03 20:48   ` Bjorn Helgaas
2020-11-04  8:51     ` Vidya Sagar

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