From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E7BDC388F9 for ; Tue, 3 Nov 2020 20:50:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E356C22404 for ; Tue, 3 Nov 2020 20:50:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1604436635; bh=jupkchvaZ/iDDls+iNDYRS2ROZr4ujl10oGXnuQWJFg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=nayXvkZXy7314uiF8xc3i+G47qRfG9aWG0fPStU+E/EHOwO9oKIPnMkpY33iUr5zF pFDkZF34zOKsfTS3ZufGmBLmtPC2lhTxMh6AIq/B1eM3eMA3ZxDyhF5LSLAq6x0eqq 7bS+6G+UhNtfKt3rkgtpeu18vvk2FEIAppcqAV7w= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731822AbgKCUue (ORCPT ); Tue, 3 Nov 2020 15:50:34 -0500 Received: from mail.kernel.org ([198.145.29.99]:44510 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731802AbgKCUu3 (ORCPT ); Tue, 3 Nov 2020 15:50:29 -0500 Received: from localhost (83-86-74-64.cable.dynamic.v4.ziggo.nl [83.86.74.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D736822404; Tue, 3 Nov 2020 20:50:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1604436628; bh=jupkchvaZ/iDDls+iNDYRS2ROZr4ujl10oGXnuQWJFg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aqpg+a9563S5AxpM3HfWDJzQY08ZQfH7fqHFLg+XOCZpaV4e/qKhwhjMA2ZY6q8PY GLNLu06y4sEeY59ql3+ljN5kYI6o5vCiX2jYbNYJDLPe2720CIxs8Fm/xxVkBIrCtA uE846En7SFPG1AOWZl7jyE6bHOZS61DDG+/Rm8gc= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Ansuel Smith , Lorenzo Pieralisi , Bjorn Andersson Subject: [PATCH 5.9 332/391] PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0 Date: Tue, 3 Nov 2020 21:36:23 +0100 Message-Id: <20201103203409.524526180@linuxfoundation.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201103203348.153465465@linuxfoundation.org> References: <20201103203348.153465465@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ansuel Smith commit d3d4d028afb785e52c55024d779089654f8302e7 upstream. Qsdk U-Boot can incorrectly leave the PCIe interface in an undefined state if bootm command is used instead of bootipq. This is caused by the not deinit of PCIe when bootm is called. Reset the PCIe before init anyway to fix this U-Boot bug. Link: https://lore.kernel.org/r/20200901124955.137-1-ansuelsmth@gmail.com Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Ansuel Smith Signed-off-by: Lorenzo Pieralisi Reviewed-by: Bjorn Andersson Cc: stable@vger.kernel.org # v4.19+ Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -302,6 +302,9 @@ static void qcom_pcie_deinit_2_1_0(struc reset_control_assert(res->por_reset); reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); + + writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -314,6 +317,16 @@ static int qcom_pcie_init_2_1_0(struct q u32 val; int ret; + /* reset the PCIe interface as uboot can leave it undefined state */ + reset_control_assert(res->pci_reset); + reset_control_assert(res->axi_reset); + reset_control_assert(res->ahb_reset); + reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); + reset_control_assert(res->phy_reset); + + writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); + ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); if (ret < 0) { dev_err(dev, "cannot enable regulators\n");