From: Yuichi Ito <ito-yuichi@fujitsu.com>
To: maz@kernel.org, sumit.garg@linaro.org, tglx@linutronix.de,
jason@lakedaemon.net, catalin.marinas@arm.com, will@kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Yuichi Ito <ito-yuichi@fujitsu.com>
Subject: [PATCH v2 0/3] Enable support IPI_CPU_CRASH_STOP to be pseudo-NMI
Date: Wed, 4 Nov 2020 17:05:36 +0900 [thread overview]
Message-ID: <20201104080539.3205889-1-ito-yuichi@fujitsu.com> (raw)
This patchset enables IPI_CPU_CRASH_STOP IPI to be pseudo-NMI.
This allows kdump to collect system information even when the CPU is in
a HARDLOCKUP state.
Only IPI_CPU_CRASH_STOP uses NMI and the other IPIs remain normal IRQs.
The patch has been tested on FX1000.
It also uses some of Sumit's IPI patch set for NMI.[1]
[1] https://lore.kernel.org/lkml/1603983387-8738-3-git-send-email-sumit.garg@linaro.org/
$ echo 1 > /proc/sys/kernel/panic_on_rcu_stal
$ echo HARDLOCKUP > /sys/kernel/debug/provoke-crash/DIRECT
: kernel panics and crash kernel boot
: makedumpfile saves the system state at HARDLOCKUP in vmcore.
crash utility:
#7 [fffffe00290afd30] lkdtm_HARDLOCKUP at fffffe0010857ee8
#8 [fffffe00290afd40] direct_entry at fffffe0010857c94
#9 [fffffe00290afd90] full_proxy_write at fffffe001055dea0
#10 [fffffe00290afdd0] vfs_write at fffffe001047533c
#11 [fffffe00290afe10] ksys_write at fffffe001047563c
#12 [fffffe00290afe60] __arm64_sys_write at fffffe00104756e8
#13 [fffffe00290afe70] do_el0_svc at fffffe00101590cc
#14 [fffffe00290afea0] el0_svc at fffffe0010147a30
#15 [fffffe00290afeb0] el0_sync_handler at fffffe001014835c
#16 [fffffe00290afff0] el0_sync at fffffe0010142c14
Changes in v1:
- Rebased to head of upstream master.
- Rebased to Sumit's latest IPIs patch-set [1].
[1] https://lore.kernel.org/lkml/1603983387-8738-3-git-send-email-sumit.garg@linaro.org/
- Add conditional branch of local_irq_disable().
Sumit Garg (1):
irqchip/gic-v3: Enable support for SGIs to act as NMIs
Yuichi Ito (2):
arch64: smp: Register IPI_CPU_CRASH_STOP IPI as pseudo-NMI
arch64: smp: Disable priority masking when received NMI on PSR.I section
arch/arm64/kernel/smp.c | 44 +++++++++++++++++++++++++++++++++++---------
drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++--------
2 files changed, 56 insertions(+), 17 deletions(-)
--
1.8.3.1
next reply other threads:[~2020-11-04 8:18 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-04 8:05 Yuichi Ito [this message]
2020-11-04 8:05 ` [PATCH v2 1/3] irqchip/gic-v3: Enable support for SGIs to act as NMIs Yuichi Ito
2020-11-16 16:22 ` Masayoshi Mizuma
2020-11-04 8:05 ` [PATCH v2 2/3] arm64: smp: Register IPI_CPU_CRASH_STOP IPI as pseudo-NMI Yuichi Ito
2020-11-04 8:05 ` [PATCH v2 3/3] arm64: smp: Disable priority masking when NMI is enable on PSR.I section Yuichi Ito
2020-11-16 6:04 ` [PATCH v2 0/3] Enable support IPI_CPU_CRASH_STOP to be pseudo-NMI ito-yuichi
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