* [PATCH 0/3] Remove drivers used by EZChip NPS platform
@ 2020-11-05 21:22 Vineet Gupta
2020-11-05 21:22 ` [PATCH 1/3] drivers/clocksource: Remove EZChip NPS clocksource driver Vineet Gupta
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Vineet Gupta @ 2020-11-05 21:22 UTC (permalink / raw)
To: linux-kernel, Thomas Gleixner; +Cc: linux-snps-arc, Vineet Gupta
This series removes any drivers associated with EZChip NPS platform
which was removed from ARC in 5.10-rc1.
Vineet Gupta (3):
drivers/clocksource: Remove EZChip NPS clocksource driver
drivers/irqchip: Remove EZChip NPS interrupt controller
include/soc: remove headers for EZChip NPS
drivers/clocksource/Kconfig | 10 --
drivers/clocksource/Makefile | 1 -
drivers/clocksource/timer-nps.c | 284 --------------------------------
drivers/irqchip/Kconfig | 7 -
drivers/irqchip/Makefile | 1 -
drivers/irqchip/irq-eznps.c | 165 -------------------
include/soc/nps/common.h | 172 -------------------
include/soc/nps/mtm.h | 59 -------
8 files changed, 699 deletions(-)
delete mode 100644 drivers/clocksource/timer-nps.c
delete mode 100644 drivers/irqchip/irq-eznps.c
delete mode 100644 include/soc/nps/common.h
delete mode 100644 include/soc/nps/mtm.h
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/3] drivers/clocksource: Remove EZChip NPS clocksource driver
2020-11-05 21:22 [PATCH 0/3] Remove drivers used by EZChip NPS platform Vineet Gupta
@ 2020-11-05 21:22 ` Vineet Gupta
2020-11-12 9:49 ` Daniel Lezcano
2020-12-03 23:47 ` [tip: timers/core] clocksource/drivers/nps: " tip-bot2 for Vineet Gupta
2020-11-05 21:22 ` [PATCH 2/3] drivers/irqchip: Remove EZChip NPS interrupt controller Vineet Gupta
` (2 subsequent siblings)
3 siblings, 2 replies; 9+ messages in thread
From: Vineet Gupta @ 2020-11-05 21:22 UTC (permalink / raw)
To: linux-kernel, Thomas Gleixner
Cc: linux-snps-arc, Vineet Gupta, Daniel Lezcano
NPS platform has been removed from ARC port and there are no in-tree
users of it now. So RIP !
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
---
drivers/clocksource/Kconfig | 10 --
drivers/clocksource/Makefile | 1 -
drivers/clocksource/timer-nps.c | 284 --------------------------------
3 files changed, 295 deletions(-)
delete mode 100644 drivers/clocksource/timer-nps.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 68b087bff59c..390c27cd926d 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -275,16 +275,6 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
-config CLKSRC_NPS
- bool "NPS400 clocksource driver" if COMPILE_TEST
- depends on !PHYS_ADDR_T_64BIT
- select CLKSRC_MMIO
- select TIMER_OF if OF
- help
- NPS400 clocksource support.
- It has a 64-bit counter with update rate up to 1000MHz.
- This counter is accessed via couple of 32-bit memory-mapped registers.
-
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 1c444cc3bb44..3c75cbbf8533 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -56,7 +56,6 @@ obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o
obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
-obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
obj-$(CONFIG_OWL_TIMER) += timer-owl.o
obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
deleted file mode 100644
index 7b6bb0df96ae..000000000000
--- a/drivers/clocksource/timer-nps.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the
- * OpenIB.org BSD license below:
- *
- * Redistribution and use in source and binary forms, with or
- * without modification, are permitted provided that the following
- * conditions are met:
- *
- * - Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the following
- * disclaimer.
- *
- * - Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials
- * provided with the distribution.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#include <linux/interrupt.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/cpu.h>
-#include <soc/nps/common.h>
-
-#define NPS_MSU_TICK_LOW 0xC8
-#define NPS_CLUSTER_OFFSET 8
-#define NPS_CLUSTER_NUM 16
-
-/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
-static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
-
-static int __init nps_get_timer_clk(struct device_node *node,
- unsigned long *timer_freq,
- struct clk **clk)
-{
- int ret;
-
- *clk = of_clk_get(node, 0);
- ret = PTR_ERR_OR_ZERO(*clk);
- if (ret) {
- pr_err("timer missing clk\n");
- return ret;
- }
-
- ret = clk_prepare_enable(*clk);
- if (ret) {
- pr_err("Couldn't enable parent clk\n");
- clk_put(*clk);
- return ret;
- }
-
- *timer_freq = clk_get_rate(*clk);
- if (!(*timer_freq)) {
- pr_err("Couldn't get clk rate\n");
- clk_disable_unprepare(*clk);
- clk_put(*clk);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static u64 nps_clksrc_read(struct clocksource *clksrc)
-{
- int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
-
- return (u64)ioread32be(nps_msu_reg_low_addr[cluster]);
-}
-
-static int __init nps_setup_clocksource(struct device_node *node)
-{
- int ret, cluster;
- struct clk *clk;
- unsigned long nps_timer1_freq;
-
-
- for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
- nps_msu_reg_low_addr[cluster] =
- nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
- NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
-
- ret = nps_get_timer_clk(node, &nps_timer1_freq, &clk);
- if (ret)
- return ret;
-
- ret = clocksource_mmio_init(nps_msu_reg_low_addr, "nps-tick",
- nps_timer1_freq, 300, 32, nps_clksrc_read);
- if (ret) {
- pr_err("Couldn't register clock source.\n");
- clk_disable_unprepare(clk);
- }
-
- return ret;
-}
-
-TIMER_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
- nps_setup_clocksource);
-TIMER_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
- nps_setup_clocksource);
-
-#ifdef CONFIG_EZNPS_MTM_EXT
-#include <soc/nps/mtm.h>
-
-/* Timer related Aux registers */
-#define NPS_REG_TIMER0_TSI 0xFFFFF850
-#define NPS_REG_TIMER0_LIMIT 0x23
-#define NPS_REG_TIMER0_CTRL 0x22
-#define NPS_REG_TIMER0_CNT 0x21
-
-/*
- * Interrupt Enabled (IE) - re-arm the timer
- * Not Halted (NH) - is cleared when working with JTAG (for debug)
- */
-#define TIMER0_CTRL_IE BIT(0)
-#define TIMER0_CTRL_NH BIT(1)
-
-static unsigned long nps_timer0_freq;
-static unsigned long nps_timer0_irq;
-
-static void nps_clkevent_rm_thread(void)
-{
- int thread;
- unsigned int cflags, enabled_threads;
-
- hw_schd_save(&cflags);
-
- enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
-
- /* remove thread from TSI1 */
- thread = read_aux_reg(CTOP_AUX_THREAD_ID);
- enabled_threads &= ~(1 << thread);
- write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
-
- /* Acknowledge and if needed re-arm the timer */
- if (!enabled_threads)
- write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_NH);
- else
- write_aux_reg(NPS_REG_TIMER0_CTRL,
- TIMER0_CTRL_IE | TIMER0_CTRL_NH);
-
- hw_schd_restore(cflags);
-}
-
-static void nps_clkevent_add_thread(unsigned long delta)
-{
- int thread;
- unsigned int cflags, enabled_threads;
-
- hw_schd_save(&cflags);
-
- /* add thread to TSI1 */
- thread = read_aux_reg(CTOP_AUX_THREAD_ID);
- enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
- enabled_threads |= (1 << thread);
- write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
-
- /* set next timer event */
- write_aux_reg(NPS_REG_TIMER0_LIMIT, delta);
- write_aux_reg(NPS_REG_TIMER0_CNT, 0);
- write_aux_reg(NPS_REG_TIMER0_CTRL,
- TIMER0_CTRL_IE | TIMER0_CTRL_NH);
-
- hw_schd_restore(cflags);
-}
-
-/*
- * Whenever anyone tries to change modes, we just mask interrupts
- * and wait for the next event to get set.
- */
-static int nps_clkevent_set_state(struct clock_event_device *dev)
-{
- nps_clkevent_rm_thread();
- disable_percpu_irq(nps_timer0_irq);
-
- return 0;
-}
-
-static int nps_clkevent_set_next_event(unsigned long delta,
- struct clock_event_device *dev)
-{
- nps_clkevent_add_thread(delta);
- enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);
-
- return 0;
-}
-
-static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
- .name = "NPS Timer0",
- .features = CLOCK_EVT_FEAT_ONESHOT,
- .rating = 300,
- .set_next_event = nps_clkevent_set_next_event,
- .set_state_oneshot = nps_clkevent_set_state,
- .set_state_oneshot_stopped = nps_clkevent_set_state,
- .set_state_shutdown = nps_clkevent_set_state,
- .tick_resume = nps_clkevent_set_state,
-};
-
-static irqreturn_t timer_irq_handler(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
-
- nps_clkevent_rm_thread();
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static int nps_timer_starting_cpu(unsigned int cpu)
-{
- struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
-
- evt->cpumask = cpumask_of(smp_processor_id());
-
- clockevents_config_and_register(evt, nps_timer0_freq, 0, ULONG_MAX);
- enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);
-
- return 0;
-}
-
-static int nps_timer_dying_cpu(unsigned int cpu)
-{
- disable_percpu_irq(nps_timer0_irq);
- return 0;
-}
-
-static int __init nps_setup_clockevent(struct device_node *node)
-{
- struct clk *clk;
- int ret;
-
- nps_timer0_irq = irq_of_parse_and_map(node, 0);
- if (nps_timer0_irq <= 0) {
- pr_err("clockevent: missing irq\n");
- return -EINVAL;
- }
-
- ret = nps_get_timer_clk(node, &nps_timer0_freq, &clk);
- if (ret)
- return ret;
-
- /* Needs apriori irq_set_percpu_devid() done in intc map function */
- ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler,
- "Timer0 (per-cpu-tick)",
- &nps_clockevent_device);
- if (ret) {
- pr_err("Couldn't request irq\n");
- clk_disable_unprepare(clk);
- return ret;
- }
-
- ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
- "clockevents/nps:starting",
- nps_timer_starting_cpu,
- nps_timer_dying_cpu);
- if (ret) {
- pr_err("Failed to setup hotplug state\n");
- clk_disable_unprepare(clk);
- free_percpu_irq(nps_timer0_irq, &nps_clockevent_device);
- return ret;
- }
-
- return 0;
-}
-
-TIMER_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
- nps_setup_clockevent);
-#endif /* CONFIG_EZNPS_MTM_EXT */
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] drivers/irqchip: Remove EZChip NPS interrupt controller
2020-11-05 21:22 [PATCH 0/3] Remove drivers used by EZChip NPS platform Vineet Gupta
2020-11-05 21:22 ` [PATCH 1/3] drivers/clocksource: Remove EZChip NPS clocksource driver Vineet Gupta
@ 2020-11-05 21:22 ` Vineet Gupta
2020-12-04 0:30 ` Vineet Gupta
2020-12-11 14:58 ` [irqchip: irq/irqchip-next] " irqchip-bot for Vineet Gupta
2020-11-05 21:22 ` [PATCH 3/3] include/soc: remove headers for EZChip NPS Vineet Gupta
2020-12-11 15:01 ` [PATCH 0/3] Remove drivers used by EZChip NPS platform Marc Zyngier
3 siblings, 2 replies; 9+ messages in thread
From: Vineet Gupta @ 2020-11-05 21:22 UTC (permalink / raw)
To: linux-kernel, Thomas Gleixner
Cc: linux-snps-arc, Vineet Gupta, Jason Cooper, Marc Zyngier
NPS platform has been removed from ARC port and there are no in-tree
users of it now. So RIP !
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
---
drivers/irqchip/Kconfig | 7 --
drivers/irqchip/Makefile | 1 -
drivers/irqchip/irq-eznps.c | 165 ------------------------------------
3 files changed, 173 deletions(-)
delete mode 100644 drivers/irqchip/irq-eznps.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c6098eee0c7c..7920c3a3017d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -389,13 +389,6 @@ config LS_SCFG_MSI
config PARTITION_PERCPU
bool
-config EZNPS_GIC
- bool "NPS400 Global Interrupt Manager (GIM)"
- depends on ARC || (COMPILE_TEST && !64BIT)
- select IRQ_DOMAIN
- help
- Support the EZchip NPS400 global interrupt controller
-
config STM32_EXTI
bool
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 94c2885882ee..0ac93bfaec61 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -86,7 +86,6 @@ obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
-obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
deleted file mode 100644
index 2a7a38830a8d..000000000000
--- a/drivers/irqchip/irq-eznps.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the
- * OpenIB.org BSD license below:
- *
- * Redistribution and use in source and binary forms, with or
- * without modification, are permitted provided that the following
- * conditions are met:
- *
- * - Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the following
- * disclaimer.
- *
- * - Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials
- * provided with the distribution.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip.h>
-#include <soc/nps/common.h>
-
-#define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
-#define NPS_TIMER0_IRQ 3
-
-/*
- * NPS400 core includes an Interrupt Controller (IC) support.
- * All cores can deactivate level irqs at first level control
- * at cores mesh layer called MTM.
- * For devices out side chip e.g. uart, network there is another
- * level called Global Interrupt Manager (GIM).
- * This second level can control level and edge interrupt.
- *
- * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
- * with private HW copy per CPU.
- */
-
-static void nps400_irq_mask(struct irq_data *irqd)
-{
- unsigned int ienb;
- unsigned int irq = irqd_to_hwirq(irqd);
-
- ienb = read_aux_reg(AUX_IENABLE);
- ienb &= ~(1 << irq);
- write_aux_reg(AUX_IENABLE, ienb);
-}
-
-static void nps400_irq_unmask(struct irq_data *irqd)
-{
- unsigned int ienb;
- unsigned int irq = irqd_to_hwirq(irqd);
-
- ienb = read_aux_reg(AUX_IENABLE);
- ienb |= (1 << irq);
- write_aux_reg(AUX_IENABLE, ienb);
-}
-
-static void nps400_irq_eoi_global(struct irq_data *irqd)
-{
- unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
-
- write_aux_reg(CTOP_AUX_IACK, 1 << irq);
-
- /* Don't ack GIC before all device access attempts are done */
- mb();
-
- nps_ack_gic();
-}
-
-static void nps400_irq_ack(struct irq_data *irqd)
-{
- unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
-
- write_aux_reg(CTOP_AUX_IACK, 1 << irq);
-}
-
-static struct irq_chip nps400_irq_chip_fasteoi = {
- .name = "NPS400 IC Global",
- .irq_mask = nps400_irq_mask,
- .irq_unmask = nps400_irq_unmask,
- .irq_eoi = nps400_irq_eoi_global,
-};
-
-static struct irq_chip nps400_irq_chip_percpu = {
- .name = "NPS400 IC",
- .irq_mask = nps400_irq_mask,
- .irq_unmask = nps400_irq_unmask,
- .irq_ack = nps400_irq_ack,
-};
-
-static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
- irq_hw_number_t hw)
-{
- switch (hw) {
- case NPS_TIMER0_IRQ:
-#ifdef CONFIG_SMP
- case NPS_IPI_IRQ:
-#endif
- irq_set_percpu_devid(virq);
- irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
- handle_percpu_devid_irq);
- break;
- default:
- irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
- handle_fasteoi_irq);
- break;
- }
-
- return 0;
-}
-
-static const struct irq_domain_ops nps400_irq_ops = {
- .xlate = irq_domain_xlate_onecell,
- .map = nps400_irq_map,
-};
-
-static int __init nps400_of_init(struct device_node *node,
- struct device_node *parent)
-{
- struct irq_domain *nps400_root_domain;
-
- if (parent) {
- pr_err("DeviceTree incore ic not a root irq controller\n");
- return -EINVAL;
- }
-
- nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
- &nps400_irq_ops, NULL);
-
- if (!nps400_root_domain) {
- pr_err("nps400 root irq domain not avail\n");
- return -ENOMEM;
- }
-
- /*
- * Needed for primary domain lookup to succeed
- * This is a primary irqchip, and can never have a parent
- */
- irq_set_default_host(nps400_root_domain);
-
-#ifdef CONFIG_SMP
- irq_create_mapping(nps400_root_domain, NPS_IPI_IRQ);
-#endif
-
- return 0;
-}
-IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] include/soc: remove headers for EZChip NPS
2020-11-05 21:22 [PATCH 0/3] Remove drivers used by EZChip NPS platform Vineet Gupta
2020-11-05 21:22 ` [PATCH 1/3] drivers/clocksource: Remove EZChip NPS clocksource driver Vineet Gupta
2020-11-05 21:22 ` [PATCH 2/3] drivers/irqchip: Remove EZChip NPS interrupt controller Vineet Gupta
@ 2020-11-05 21:22 ` Vineet Gupta
2020-12-11 15:01 ` [PATCH 0/3] Remove drivers used by EZChip NPS platform Marc Zyngier
3 siblings, 0 replies; 9+ messages in thread
From: Vineet Gupta @ 2020-11-05 21:22 UTC (permalink / raw)
To: linux-kernel, Thomas Gleixner; +Cc: linux-snps-arc, Vineet Gupta
NPS platform has been removed from ARC port and there are no in-tree
user of it now . So RIP !
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
---
include/soc/nps/common.h | 172 ---------------------------------------
include/soc/nps/mtm.h | 59 --------------
2 files changed, 231 deletions(-)
delete mode 100644 include/soc/nps/common.h
delete mode 100644 include/soc/nps/mtm.h
diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
deleted file mode 100644
index 8c18dc6d3fde..000000000000
--- a/include/soc/nps/common.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the
- * OpenIB.org BSD license below:
- *
- * Redistribution and use in source and binary forms, with or
- * without modification, are permitted provided that the following
- * conditions are met:
- *
- * - Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the following
- * disclaimer.
- *
- * - Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials
- * provided with the distribution.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef SOC_NPS_COMMON_H
-#define SOC_NPS_COMMON_H
-
-#ifdef CONFIG_SMP
-#define NPS_IPI_IRQ 5
-#endif
-
-#define NPS_HOST_REG_BASE 0xF6000000
-
-#define NPS_MSU_BLKID 0x018
-
-#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
-#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
-#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
-
-#ifndef AUX_IENABLE
-#define AUX_IENABLE 0x40c
-#endif
-
-#define CTOP_AUX_IACK (0xFFFFF800 + 0x088)
-
-#ifndef __ASSEMBLY__
-
-/* In order to increase compilation test coverage */
-#ifdef CONFIG_ARC
-static inline void nps_ack_gic(void)
-{
- __asm__ __volatile__ (
- " .word %0\n"
- :
- : "i"(CTOP_INST_RSPI_GIC_0_R12)
- : "memory");
-}
-#else
-static inline void nps_ack_gic(void) { }
-#define write_aux_reg(r, v)
-#define read_aux_reg(r) 0
-#endif
-
-/* CPU global ID */
-struct global_id {
- union {
- struct {
-#ifdef CONFIG_EZNPS_MTM_EXT
- u32 __reserved:20, cluster:4, core:4, thread:4;
-#else
- u32 __reserved:24, cluster:4, core:4;
-#endif
- };
- u32 value;
- };
-};
-
-/*
- * Convert logical to physical CPU IDs
- *
- * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
- * Now quad of logical clusters id's are adjacent physically,
- * and not like the id's physically came with each cluster.
- * Below table is 4x4 mesh of core clusters as it layout on chip.
- * Cluster ids are in format: logical (physical)
- *
- * ----------------- ------------------
- * 3 | 5 (3) 7 (7) | | 13 (11) 15 (15)|
- *
- * 2 | 4 (2) 6 (6) | | 12 (10) 14 (14)|
- * ----------------- ------------------
- * 1 | 1 (1) 3 (5) | | 9 (9) 11 (13)|
- *
- * 0 | 0 (0) 2 (4) | | 8 (8) 10 (12)|
- * ----------------- ------------------
- * 0 1 2 3
- */
-static inline int nps_cluster_logic_to_phys(int cluster)
-{
-#ifdef __arc__
- __asm__ __volatile__(
- " mov r3,%0\n"
- " .short %1\n"
- " .word %2\n"
- " mov %0,r3\n"
- : "+r"(cluster)
- : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
- "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
- : "r3");
-#endif
-
- return cluster;
-}
-
-#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
- ({ struct global_id gid; gid.value = cpu; \
- nps_cluster_logic_to_phys(gid.cluster); })
-
-struct nps_host_reg_address {
- union {
- struct {
- u32 base:8, cl_x:4, cl_y:4,
- blkid:6, reg:8, __reserved:2;
- };
- u32 value;
- };
-};
-
-struct nps_host_reg_address_non_cl {
- union {
- struct {
- u32 base:7, blkid:11, reg:12, __reserved:2;
- };
- u32 value;
- };
-};
-
-static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
-{
- struct nps_host_reg_address_non_cl reg_address;
-
- reg_address.value = NPS_HOST_REG_BASE;
- reg_address.blkid = blkid;
- reg_address.reg = reg;
-
- return (void *)reg_address.value;
-}
-
-static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
-{
- struct nps_host_reg_address reg_address;
- u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
-
- reg_address.value = NPS_HOST_REG_BASE;
- reg_address.cl_x = (cl >> 2) & 0x3;
- reg_address.cl_y = cl & 0x3;
- reg_address.blkid = blkid;
- reg_address.reg = reg;
-
- return (void *)reg_address.value;
-}
-#endif /* __ASSEMBLY__ */
-
-#endif /* SOC_NPS_COMMON_H */
diff --git a/include/soc/nps/mtm.h b/include/soc/nps/mtm.h
deleted file mode 100644
index d2f5e7e3703e..000000000000
--- a/include/soc/nps/mtm.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the
- * OpenIB.org BSD license below:
- *
- * Redistribution and use in source and binary forms, with or
- * without modification, are permitted provided that the following
- * conditions are met:
- *
- * - Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the following
- * disclaimer.
- *
- * - Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials
- * provided with the distribution.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef SOC_NPS_MTM_H
-#define SOC_NPS_MTM_H
-
-#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
-#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
-
-static inline void hw_schd_save(unsigned int *flags)
-{
- __asm__ __volatile__(
- " .word %1\n"
- " st r3,[%0]\n"
- :
- : "r"(flags), "i"(CTOP_INST_HWSCHD_OFF_R3)
- : "r3", "memory");
-}
-
-static inline void hw_schd_restore(unsigned int flags)
-{
- __asm__ __volatile__(
- " mov r3, %0\n"
- " .word %1\n"
- :
- : "r"(flags), "i"(CTOP_INST_HWSCHD_RESTORE_R3)
- : "r3");
-}
-
-#endif /* SOC_NPS_MTM_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] drivers/clocksource: Remove EZChip NPS clocksource driver
2020-11-05 21:22 ` [PATCH 1/3] drivers/clocksource: Remove EZChip NPS clocksource driver Vineet Gupta
@ 2020-11-12 9:49 ` Daniel Lezcano
2020-12-03 23:47 ` [tip: timers/core] clocksource/drivers/nps: " tip-bot2 for Vineet Gupta
1 sibling, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2020-11-12 9:49 UTC (permalink / raw)
To: Vineet Gupta, linux-kernel, Thomas Gleixner; +Cc: linux-snps-arc
On 05/11/2020 22:22, Vineet Gupta wrote:
> NPS platform has been removed from ARC port and there are no in-tree
> users of it now. So RIP !
>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
> ---
Applied, thanks!
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 9+ messages in thread
* [tip: timers/core] clocksource/drivers/nps: Remove EZChip NPS clocksource driver
2020-11-05 21:22 ` [PATCH 1/3] drivers/clocksource: Remove EZChip NPS clocksource driver Vineet Gupta
2020-11-12 9:49 ` Daniel Lezcano
@ 2020-12-03 23:47 ` tip-bot2 for Vineet Gupta
1 sibling, 0 replies; 9+ messages in thread
From: tip-bot2 for Vineet Gupta @ 2020-12-03 23:47 UTC (permalink / raw)
To: linux-tip-commits
Cc: Daniel Lezcano, Thomas Gleixner, linux-kernel, Vineet Gupta, x86
The following commit has been merged into the timers/core branch of tip:
Commit-ID: b6ea209ef124dad4045772a759e2aecd191534c0
Gitweb: https://git.kernel.org/tip/b6ea209ef124dad4045772a759e2aecd191534c0
Author: Vineet Gupta <Vineet.Gupta1@synopsys.com>
AuthorDate: Thu, 05 Nov 2020 13:22:08 -08:00
Committer: Daniel Lezcano <daniel.lezcano@linaro.org>
CommitterDate: Thu, 03 Dec 2020 19:16:18 +01:00
clocksource/drivers/nps: Remove EZChip NPS clocksource driver
NPS platform has been removed from ARC port and there are no in-tree
users of it now. So RIP !
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20201105212210.1891598-2-vgupta@synopsys.com
---
drivers/clocksource/Kconfig | 10 +-
drivers/clocksource/Makefile | 1 +-
drivers/clocksource/timer-nps.c | 284 +-------------------------------
3 files changed, 295 deletions(-)
delete mode 100644 drivers/clocksource/timer-nps.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 68b087b..390c27c 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -275,16 +275,6 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
-config CLKSRC_NPS
- bool "NPS400 clocksource driver" if COMPILE_TEST
- depends on !PHYS_ADDR_T_64BIT
- select CLKSRC_MMIO
- select TIMER_OF if OF
- help
- NPS400 clocksource support.
- It has a 64-bit counter with update rate up to 1000MHz.
- This counter is accessed via couple of 32-bit memory-mapped registers.
-
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 1c444cc..3c75cbb 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -56,7 +56,6 @@ obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o
obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
-obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
obj-$(CONFIG_OWL_TIMER) += timer-owl.o
obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
deleted file mode 100644
index 7b6bb0d..0000000
--- a/drivers/clocksource/timer-nps.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the
- * OpenIB.org BSD license below:
- *
- * Redistribution and use in source and binary forms, with or
- * without modification, are permitted provided that the following
- * conditions are met:
- *
- * - Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the following
- * disclaimer.
- *
- * - Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials
- * provided with the distribution.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#include <linux/interrupt.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/cpu.h>
-#include <soc/nps/common.h>
-
-#define NPS_MSU_TICK_LOW 0xC8
-#define NPS_CLUSTER_OFFSET 8
-#define NPS_CLUSTER_NUM 16
-
-/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
-static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
-
-static int __init nps_get_timer_clk(struct device_node *node,
- unsigned long *timer_freq,
- struct clk **clk)
-{
- int ret;
-
- *clk = of_clk_get(node, 0);
- ret = PTR_ERR_OR_ZERO(*clk);
- if (ret) {
- pr_err("timer missing clk\n");
- return ret;
- }
-
- ret = clk_prepare_enable(*clk);
- if (ret) {
- pr_err("Couldn't enable parent clk\n");
- clk_put(*clk);
- return ret;
- }
-
- *timer_freq = clk_get_rate(*clk);
- if (!(*timer_freq)) {
- pr_err("Couldn't get clk rate\n");
- clk_disable_unprepare(*clk);
- clk_put(*clk);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static u64 nps_clksrc_read(struct clocksource *clksrc)
-{
- int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
-
- return (u64)ioread32be(nps_msu_reg_low_addr[cluster]);
-}
-
-static int __init nps_setup_clocksource(struct device_node *node)
-{
- int ret, cluster;
- struct clk *clk;
- unsigned long nps_timer1_freq;
-
-
- for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
- nps_msu_reg_low_addr[cluster] =
- nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
- NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
-
- ret = nps_get_timer_clk(node, &nps_timer1_freq, &clk);
- if (ret)
- return ret;
-
- ret = clocksource_mmio_init(nps_msu_reg_low_addr, "nps-tick",
- nps_timer1_freq, 300, 32, nps_clksrc_read);
- if (ret) {
- pr_err("Couldn't register clock source.\n");
- clk_disable_unprepare(clk);
- }
-
- return ret;
-}
-
-TIMER_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
- nps_setup_clocksource);
-TIMER_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
- nps_setup_clocksource);
-
-#ifdef CONFIG_EZNPS_MTM_EXT
-#include <soc/nps/mtm.h>
-
-/* Timer related Aux registers */
-#define NPS_REG_TIMER0_TSI 0xFFFFF850
-#define NPS_REG_TIMER0_LIMIT 0x23
-#define NPS_REG_TIMER0_CTRL 0x22
-#define NPS_REG_TIMER0_CNT 0x21
-
-/*
- * Interrupt Enabled (IE) - re-arm the timer
- * Not Halted (NH) - is cleared when working with JTAG (for debug)
- */
-#define TIMER0_CTRL_IE BIT(0)
-#define TIMER0_CTRL_NH BIT(1)
-
-static unsigned long nps_timer0_freq;
-static unsigned long nps_timer0_irq;
-
-static void nps_clkevent_rm_thread(void)
-{
- int thread;
- unsigned int cflags, enabled_threads;
-
- hw_schd_save(&cflags);
-
- enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
-
- /* remove thread from TSI1 */
- thread = read_aux_reg(CTOP_AUX_THREAD_ID);
- enabled_threads &= ~(1 << thread);
- write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
-
- /* Acknowledge and if needed re-arm the timer */
- if (!enabled_threads)
- write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_NH);
- else
- write_aux_reg(NPS_REG_TIMER0_CTRL,
- TIMER0_CTRL_IE | TIMER0_CTRL_NH);
-
- hw_schd_restore(cflags);
-}
-
-static void nps_clkevent_add_thread(unsigned long delta)
-{
- int thread;
- unsigned int cflags, enabled_threads;
-
- hw_schd_save(&cflags);
-
- /* add thread to TSI1 */
- thread = read_aux_reg(CTOP_AUX_THREAD_ID);
- enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
- enabled_threads |= (1 << thread);
- write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
-
- /* set next timer event */
- write_aux_reg(NPS_REG_TIMER0_LIMIT, delta);
- write_aux_reg(NPS_REG_TIMER0_CNT, 0);
- write_aux_reg(NPS_REG_TIMER0_CTRL,
- TIMER0_CTRL_IE | TIMER0_CTRL_NH);
-
- hw_schd_restore(cflags);
-}
-
-/*
- * Whenever anyone tries to change modes, we just mask interrupts
- * and wait for the next event to get set.
- */
-static int nps_clkevent_set_state(struct clock_event_device *dev)
-{
- nps_clkevent_rm_thread();
- disable_percpu_irq(nps_timer0_irq);
-
- return 0;
-}
-
-static int nps_clkevent_set_next_event(unsigned long delta,
- struct clock_event_device *dev)
-{
- nps_clkevent_add_thread(delta);
- enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);
-
- return 0;
-}
-
-static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
- .name = "NPS Timer0",
- .features = CLOCK_EVT_FEAT_ONESHOT,
- .rating = 300,
- .set_next_event = nps_clkevent_set_next_event,
- .set_state_oneshot = nps_clkevent_set_state,
- .set_state_oneshot_stopped = nps_clkevent_set_state,
- .set_state_shutdown = nps_clkevent_set_state,
- .tick_resume = nps_clkevent_set_state,
-};
-
-static irqreturn_t timer_irq_handler(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
-
- nps_clkevent_rm_thread();
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static int nps_timer_starting_cpu(unsigned int cpu)
-{
- struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
-
- evt->cpumask = cpumask_of(smp_processor_id());
-
- clockevents_config_and_register(evt, nps_timer0_freq, 0, ULONG_MAX);
- enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);
-
- return 0;
-}
-
-static int nps_timer_dying_cpu(unsigned int cpu)
-{
- disable_percpu_irq(nps_timer0_irq);
- return 0;
-}
-
-static int __init nps_setup_clockevent(struct device_node *node)
-{
- struct clk *clk;
- int ret;
-
- nps_timer0_irq = irq_of_parse_and_map(node, 0);
- if (nps_timer0_irq <= 0) {
- pr_err("clockevent: missing irq\n");
- return -EINVAL;
- }
-
- ret = nps_get_timer_clk(node, &nps_timer0_freq, &clk);
- if (ret)
- return ret;
-
- /* Needs apriori irq_set_percpu_devid() done in intc map function */
- ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler,
- "Timer0 (per-cpu-tick)",
- &nps_clockevent_device);
- if (ret) {
- pr_err("Couldn't request irq\n");
- clk_disable_unprepare(clk);
- return ret;
- }
-
- ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
- "clockevents/nps:starting",
- nps_timer_starting_cpu,
- nps_timer_dying_cpu);
- if (ret) {
- pr_err("Failed to setup hotplug state\n");
- clk_disable_unprepare(clk);
- free_percpu_irq(nps_timer0_irq, &nps_clockevent_device);
- return ret;
- }
-
- return 0;
-}
-
-TIMER_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
- nps_setup_clockevent);
-#endif /* CONFIG_EZNPS_MTM_EXT */
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] drivers/irqchip: Remove EZChip NPS interrupt controller
2020-11-05 21:22 ` [PATCH 2/3] drivers/irqchip: Remove EZChip NPS interrupt controller Vineet Gupta
@ 2020-12-04 0:30 ` Vineet Gupta
2020-12-11 14:58 ` [irqchip: irq/irqchip-next] " irqchip-bot for Vineet Gupta
1 sibling, 0 replies; 9+ messages in thread
From: Vineet Gupta @ 2020-12-04 0:30 UTC (permalink / raw)
To: linux-kernel, Thomas Gleixner
Cc: linux-snps-arc, Jason Cooper, Marc Zyngier, Jason Cooper
On 11/5/20 1:22 PM, Vineet Gupta wrote:
> NPS platform has been removed from ARC port and there are no in-tree
> users of it now. So RIP !
>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Ping !
> ---
> drivers/irqchip/Kconfig | 7 --
> drivers/irqchip/Makefile | 1 -
> drivers/irqchip/irq-eznps.c | 165 ------------------------------------
> 3 files changed, 173 deletions(-)
> delete mode 100644 drivers/irqchip/irq-eznps.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index c6098eee0c7c..7920c3a3017d 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -389,13 +389,6 @@ config LS_SCFG_MSI
> config PARTITION_PERCPU
> bool
>
> -config EZNPS_GIC
> - bool "NPS400 Global Interrupt Manager (GIM)"
> - depends on ARC || (COMPILE_TEST && !64BIT)
> - select IRQ_DOMAIN
> - help
> - Support the EZchip NPS400 global interrupt controller
> -
> config STM32_EXTI
> bool
> select IRQ_DOMAIN
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 94c2885882ee..0ac93bfaec61 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -86,7 +86,6 @@ obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
> obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
> obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
> obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
> -obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
> obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
> obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
> obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
> diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
> deleted file mode 100644
> index 2a7a38830a8d..000000000000
> --- a/drivers/irqchip/irq-eznps.c
> +++ /dev/null
> @@ -1,165 +0,0 @@
> -/*
> - * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
> - *
> - * This software is available to you under a choice of one of two
> - * licenses. You may choose to be licensed under the terms of the GNU
> - * General Public License (GPL) Version 2, available from the file
> - * COPYING in the main directory of this source tree, or the
> - * OpenIB.org BSD license below:
> - *
> - * Redistribution and use in source and binary forms, with or
> - * without modification, are permitted provided that the following
> - * conditions are met:
> - *
> - * - Redistributions of source code must retain the above
> - * copyright notice, this list of conditions and the following
> - * disclaimer.
> - *
> - * - Redistributions in binary form must reproduce the above
> - * copyright notice, this list of conditions and the following
> - * disclaimer in the documentation and/or other materials
> - * provided with the distribution.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
> - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
> - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> - * SOFTWARE.
> - */
> -
> -#include <linux/interrupt.h>
> -#include <linux/module.h>
> -#include <linux/of.h>
> -#include <linux/irq.h>
> -#include <linux/irqdomain.h>
> -#include <linux/irqchip.h>
> -#include <soc/nps/common.h>
> -
> -#define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
> -#define NPS_TIMER0_IRQ 3
> -
> -/*
> - * NPS400 core includes an Interrupt Controller (IC) support.
> - * All cores can deactivate level irqs at first level control
> - * at cores mesh layer called MTM.
> - * For devices out side chip e.g. uart, network there is another
> - * level called Global Interrupt Manager (GIM).
> - * This second level can control level and edge interrupt.
> - *
> - * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
> - * with private HW copy per CPU.
> - */
> -
> -static void nps400_irq_mask(struct irq_data *irqd)
> -{
> - unsigned int ienb;
> - unsigned int irq = irqd_to_hwirq(irqd);
> -
> - ienb = read_aux_reg(AUX_IENABLE);
> - ienb &= ~(1 << irq);
> - write_aux_reg(AUX_IENABLE, ienb);
> -}
> -
> -static void nps400_irq_unmask(struct irq_data *irqd)
> -{
> - unsigned int ienb;
> - unsigned int irq = irqd_to_hwirq(irqd);
> -
> - ienb = read_aux_reg(AUX_IENABLE);
> - ienb |= (1 << irq);
> - write_aux_reg(AUX_IENABLE, ienb);
> -}
> -
> -static void nps400_irq_eoi_global(struct irq_data *irqd)
> -{
> - unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
> -
> - write_aux_reg(CTOP_AUX_IACK, 1 << irq);
> -
> - /* Don't ack GIC before all device access attempts are done */
> - mb();
> -
> - nps_ack_gic();
> -}
> -
> -static void nps400_irq_ack(struct irq_data *irqd)
> -{
> - unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
> -
> - write_aux_reg(CTOP_AUX_IACK, 1 << irq);
> -}
> -
> -static struct irq_chip nps400_irq_chip_fasteoi = {
> - .name = "NPS400 IC Global",
> - .irq_mask = nps400_irq_mask,
> - .irq_unmask = nps400_irq_unmask,
> - .irq_eoi = nps400_irq_eoi_global,
> -};
> -
> -static struct irq_chip nps400_irq_chip_percpu = {
> - .name = "NPS400 IC",
> - .irq_mask = nps400_irq_mask,
> - .irq_unmask = nps400_irq_unmask,
> - .irq_ack = nps400_irq_ack,
> -};
> -
> -static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
> - irq_hw_number_t hw)
> -{
> - switch (hw) {
> - case NPS_TIMER0_IRQ:
> -#ifdef CONFIG_SMP
> - case NPS_IPI_IRQ:
> -#endif
> - irq_set_percpu_devid(virq);
> - irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
> - handle_percpu_devid_irq);
> - break;
> - default:
> - irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
> - handle_fasteoi_irq);
> - break;
> - }
> -
> - return 0;
> -}
> -
> -static const struct irq_domain_ops nps400_irq_ops = {
> - .xlate = irq_domain_xlate_onecell,
> - .map = nps400_irq_map,
> -};
> -
> -static int __init nps400_of_init(struct device_node *node,
> - struct device_node *parent)
> -{
> - struct irq_domain *nps400_root_domain;
> -
> - if (parent) {
> - pr_err("DeviceTree incore ic not a root irq controller\n");
> - return -EINVAL;
> - }
> -
> - nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
> - &nps400_irq_ops, NULL);
> -
> - if (!nps400_root_domain) {
> - pr_err("nps400 root irq domain not avail\n");
> - return -ENOMEM;
> - }
> -
> - /*
> - * Needed for primary domain lookup to succeed
> - * This is a primary irqchip, and can never have a parent
> - */
> - irq_set_default_host(nps400_root_domain);
> -
> -#ifdef CONFIG_SMP
> - irq_create_mapping(nps400_root_domain, NPS_IPI_IRQ);
> -#endif
> -
> - return 0;
> -}
> -IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [irqchip: irq/irqchip-next] drivers/irqchip: Remove EZChip NPS interrupt controller
2020-11-05 21:22 ` [PATCH 2/3] drivers/irqchip: Remove EZChip NPS interrupt controller Vineet Gupta
2020-12-04 0:30 ` Vineet Gupta
@ 2020-12-11 14:58 ` irqchip-bot for Vineet Gupta
1 sibling, 0 replies; 9+ messages in thread
From: irqchip-bot for Vineet Gupta @ 2020-12-11 14:58 UTC (permalink / raw)
To: linux-kernel
Cc: Vineet Gupta, Marc Zyngier, Thomas Gleixner, Jason Cooper, linux-kernel
The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: 04e7f423f4a96ad492fd51bf2234b8982400ab5f
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/04e7f423f4a96ad492fd51bf2234b8982400ab5f
Author: Vineet Gupta <Vineet.Gupta1@synopsys.com>
AuthorDate: Thu, 05 Nov 2020 13:22:09 -08:00
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Fri, 11 Dec 2020 14:47:50
drivers/irqchip: Remove EZChip NPS interrupt controller
NPS platform has been removed from ARC port and there are no in-tree
users of it now. So RIP !
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: linux-kernel@vger.kernel.org
Link: https://lore.kernel.org/r/20201105212210.1891598-3-vgupta@synopsys.com
---
drivers/irqchip/Kconfig | 7 +-
drivers/irqchip/Makefile | 1 +-
drivers/irqchip/irq-eznps.c | 165 +-----------------------------------
3 files changed, 173 deletions(-)
delete mode 100644 drivers/irqchip/irq-eznps.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 2aa79c3..94920a5 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -387,13 +387,6 @@ config LS_SCFG_MSI
config PARTITION_PERCPU
bool
-config EZNPS_GIC
- bool "NPS400 Global Interrupt Manager (GIM)"
- depends on ARC || (COMPILE_TEST && !64BIT)
- select IRQ_DOMAIN
- help
- Support the EZchip NPS400 global interrupt controller
-
config STM32_EXTI
bool
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 94c2885..0ac93bf 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -86,7 +86,6 @@ obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
-obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
deleted file mode 100644
index 2a7a388..0000000
--- a/drivers/irqchip/irq-eznps.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses. You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the
- * OpenIB.org BSD license below:
- *
- * Redistribution and use in source and binary forms, with or
- * without modification, are permitted provided that the following
- * conditions are met:
- *
- * - Redistributions of source code must retain the above
- * copyright notice, this list of conditions and the following
- * disclaimer.
- *
- * - Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials
- * provided with the distribution.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip.h>
-#include <soc/nps/common.h>
-
-#define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
-#define NPS_TIMER0_IRQ 3
-
-/*
- * NPS400 core includes an Interrupt Controller (IC) support.
- * All cores can deactivate level irqs at first level control
- * at cores mesh layer called MTM.
- * For devices out side chip e.g. uart, network there is another
- * level called Global Interrupt Manager (GIM).
- * This second level can control level and edge interrupt.
- *
- * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
- * with private HW copy per CPU.
- */
-
-static void nps400_irq_mask(struct irq_data *irqd)
-{
- unsigned int ienb;
- unsigned int irq = irqd_to_hwirq(irqd);
-
- ienb = read_aux_reg(AUX_IENABLE);
- ienb &= ~(1 << irq);
- write_aux_reg(AUX_IENABLE, ienb);
-}
-
-static void nps400_irq_unmask(struct irq_data *irqd)
-{
- unsigned int ienb;
- unsigned int irq = irqd_to_hwirq(irqd);
-
- ienb = read_aux_reg(AUX_IENABLE);
- ienb |= (1 << irq);
- write_aux_reg(AUX_IENABLE, ienb);
-}
-
-static void nps400_irq_eoi_global(struct irq_data *irqd)
-{
- unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
-
- write_aux_reg(CTOP_AUX_IACK, 1 << irq);
-
- /* Don't ack GIC before all device access attempts are done */
- mb();
-
- nps_ack_gic();
-}
-
-static void nps400_irq_ack(struct irq_data *irqd)
-{
- unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
-
- write_aux_reg(CTOP_AUX_IACK, 1 << irq);
-}
-
-static struct irq_chip nps400_irq_chip_fasteoi = {
- .name = "NPS400 IC Global",
- .irq_mask = nps400_irq_mask,
- .irq_unmask = nps400_irq_unmask,
- .irq_eoi = nps400_irq_eoi_global,
-};
-
-static struct irq_chip nps400_irq_chip_percpu = {
- .name = "NPS400 IC",
- .irq_mask = nps400_irq_mask,
- .irq_unmask = nps400_irq_unmask,
- .irq_ack = nps400_irq_ack,
-};
-
-static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
- irq_hw_number_t hw)
-{
- switch (hw) {
- case NPS_TIMER0_IRQ:
-#ifdef CONFIG_SMP
- case NPS_IPI_IRQ:
-#endif
- irq_set_percpu_devid(virq);
- irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
- handle_percpu_devid_irq);
- break;
- default:
- irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
- handle_fasteoi_irq);
- break;
- }
-
- return 0;
-}
-
-static const struct irq_domain_ops nps400_irq_ops = {
- .xlate = irq_domain_xlate_onecell,
- .map = nps400_irq_map,
-};
-
-static int __init nps400_of_init(struct device_node *node,
- struct device_node *parent)
-{
- struct irq_domain *nps400_root_domain;
-
- if (parent) {
- pr_err("DeviceTree incore ic not a root irq controller\n");
- return -EINVAL;
- }
-
- nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
- &nps400_irq_ops, NULL);
-
- if (!nps400_root_domain) {
- pr_err("nps400 root irq domain not avail\n");
- return -ENOMEM;
- }
-
- /*
- * Needed for primary domain lookup to succeed
- * This is a primary irqchip, and can never have a parent
- */
- irq_set_default_host(nps400_root_domain);
-
-#ifdef CONFIG_SMP
- irq_create_mapping(nps400_root_domain, NPS_IPI_IRQ);
-#endif
-
- return 0;
-}
-IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] Remove drivers used by EZChip NPS platform
2020-11-05 21:22 [PATCH 0/3] Remove drivers used by EZChip NPS platform Vineet Gupta
` (2 preceding siblings ...)
2020-11-05 21:22 ` [PATCH 3/3] include/soc: remove headers for EZChip NPS Vineet Gupta
@ 2020-12-11 15:01 ` Marc Zyngier
3 siblings, 0 replies; 9+ messages in thread
From: Marc Zyngier @ 2020-12-11 15:01 UTC (permalink / raw)
To: shawnguo, linux, leoyang.li, mark.rutland, zhiqiang.hou,
Biwen Li, robh+dt, tglx, Vineet Gupta, linux-kernel
Cc: xiaobo.xie, Hou Zhiqiang, devicetree, linux-arm-kernel, Biwen Li,
jiafei.pan, linux-snps-arc
On Thu, 5 Nov 2020 13:22:07 -0800, Vineet Gupta wrote:
> This series removes any drivers associated with EZChip NPS platform
> which was removed from ARC in 5.10-rc1.
>
> Vineet Gupta (3):
> drivers/clocksource: Remove EZChip NPS clocksource driver
> drivers/irqchip: Remove EZChip NPS interrupt controller
> include/soc: remove headers for EZChip NPS
>
> [...]
Applied to irq/irqchip-next, thanks!
[2/3] drivers/irqchip: Remove EZChip NPS interrupt controller
commit: 04e7f423f4a96ad492fd51bf2234b8982400ab5f
Please route the two other patches via their respective trees.
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-12-11 16:09 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-05 21:22 [PATCH 0/3] Remove drivers used by EZChip NPS platform Vineet Gupta
2020-11-05 21:22 ` [PATCH 1/3] drivers/clocksource: Remove EZChip NPS clocksource driver Vineet Gupta
2020-11-12 9:49 ` Daniel Lezcano
2020-12-03 23:47 ` [tip: timers/core] clocksource/drivers/nps: " tip-bot2 for Vineet Gupta
2020-11-05 21:22 ` [PATCH 2/3] drivers/irqchip: Remove EZChip NPS interrupt controller Vineet Gupta
2020-12-04 0:30 ` Vineet Gupta
2020-12-11 14:58 ` [irqchip: irq/irqchip-next] " irqchip-bot for Vineet Gupta
2020-11-05 21:22 ` [PATCH 3/3] include/soc: remove headers for EZChip NPS Vineet Gupta
2020-12-11 15:01 ` [PATCH 0/3] Remove drivers used by EZChip NPS platform Marc Zyngier
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