[PATCH v2 0/6] Allwinner V3 SL631 Action Camera Support and Related Fixes

[PATCH v2 0/6] Allwinner V3 SL631 Action Camera Support and Related Fixes

[Paul Kocialkowski]

This series adds support for the Allwinner V3-based SL631 family of
Action Cameras, starting with the IMX179 fashion.

A few fixes to V3 support are added along the way, most notably support
for the NMI IRQ controller which is necessary for the AXP209 IRQ.

Note that some patches in this series may have already been submitted
(but not yet merged) by others and are included for the series to build.

Changes since v1:
- Rework commit log messages as requested;
- Fixed v3s nmi controller compatible order in dt bindings doc;
- Changed SL631 compatible vendor to allwinner;
- Fixed LRADC button node names;
- Removed unused LDO4 regulator node;
- Removed merged patches.

Happy reviewing!

Paul Kocialkowski (6):
  dt-bindings: irq: sun7i-nmi: Add binding documentation for the V3s NMI
  irqchip/sunxi-nmi: Add support for the V3s NMI
  ARM: dts: sun8i-v3s: Add the V3s NMI IRQ controller
  ARM: dts: sun8i: Cleanup the Pinecube AXP209 node
  dt-bindings: arm: sunxi: Add SL631 with IMX179 bindings
  ARM: dts: sun8i-v3: Add support for the SL631 Action Camera with
    IMX179

 .../devicetree/bindings/arm/sunxi.yaml        |   6 +
 .../allwinner,sun7i-a20-sc-nmi.yaml           |   1 +
 arch/arm/boot/dts/Makefile                    |   1 +
 arch/arm/boot/dts/sun8i-s3-pinecube.dts       |   8 +-
 arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts   |  12 ++
 arch/arm/boot/dts/sun8i-v3-sl631.dtsi         | 138 ++++++++++++++++++
 arch/arm/boot/dts/sun8i-v3s.dtsi              |  10 +-
 drivers/irqchip/irq-sunxi-nmi.c               |  18 ++-
 8 files changed, 186 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts
 create mode 100644 arch/arm/boot/dts/sun8i-v3-sl631.dtsi

-- 
2.29.1

[PATCH v2 1/6] dt-bindings: irq: sun7i-nmi: Add binding documentation for the V3s NMI

[Paul Kocialkowski]

Due to a register layout that's different from any other supported
Allwinner SoC, the NMI interrupt controller takes a specific compatible
for the V3s. Add it to the device-tree bindings documentation.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
index 8acca0ae3129..077803277b34 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
@@ -29,6 +29,7 @@ properties:
       - items:
           - const: allwinner,sun8i-a83t-r-intc
           - const: allwinner,sun6i-a31-r-intc
+      - const: allwinner,sun8i-v3s-sc-nmi
       - const: allwinner,sun9i-a80-nmi
       - items:
           - const: allwinner,sun50i-a64-r-intc
-- 
2.29.1

[PATCH v2 2/6] irqchip/sunxi-nmi: Add support for the V3s NMI

[Paul Kocialkowski]

The V3s/V3 has a NMI IRQ controller, which is mainly used for the AXP209
interrupt. In great wisdom, Allwinner decided to invert the enable and
pending register offsets, compared to the A20.

As a result, a specific compatible and register description is required
for the V3s. This was tested with an AXP209 on a V3 board.

Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 drivers/irqchip/irq-sunxi-nmi.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index a412b5d5d0fa..59e0e4612ef7 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -44,6 +44,10 @@
 #define SUN7I_NMI_PENDING	0x04
 #define SUN7I_NMI_ENABLE	0x08
 
+#define SUN8I_V3S_NMI_CTRL	0x00
+#define SUN8I_V3S_NMI_ENABLE	0x04
+#define SUN8I_V3S_NMI_PENDING	0x08
+
 #define SUN9I_NMI_CTRL		0x00
 #define SUN9I_NMI_ENABLE	0x04
 #define SUN9I_NMI_PENDING	0x08
@@ -79,6 +83,12 @@ static const struct sunxi_sc_nmi_reg_offs sun7i_reg_offs __initconst = {
 	.enable	= SUN7I_NMI_ENABLE,
 };
 
+static const struct sunxi_sc_nmi_reg_offs sun8i_v3s_reg_offs __initconst = {
+	.ctrl	= SUN8I_V3S_NMI_CTRL,
+	.pend	= SUN8I_V3S_NMI_PENDING,
+	.enable	= SUN8I_V3S_NMI_ENABLE,
+};
+
 static const struct sunxi_sc_nmi_reg_offs sun9i_reg_offs __initconst = {
 	.ctrl	= SUN9I_NMI_CTRL,
 	.pend	= SUN9I_NMI_PENDING,
@@ -165,7 +175,6 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
 	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 	int ret;
 
-
 	domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
 	if (!domain) {
 		pr_err("Could not register interrupt domain.\n");
@@ -254,6 +263,13 @@ static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
 }
 IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
 
+static int __init sun8i_v3s_sc_nmi_irq_init(struct device_node *node,
+					    struct device_node *parent)
+{
+	return sunxi_sc_nmi_irq_init(node, &sun8i_v3s_reg_offs);
+}
+IRQCHIP_DECLARE(sun8i_v3s_sc_nmi, "allwinner,sun8i-v3s-sc-nmi", sun8i_v3s_sc_nmi_irq_init);
+
 static int __init sun9i_nmi_irq_init(struct device_node *node,
 				     struct device_node *parent)
 {
-- 
2.29.1

[PATCH v2 3/6] ARM: dts: sun8i-v3s: Add the V3s NMI IRQ controller

[Paul Kocialkowski]

The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209.
Its address follows the system controller block, which was previously
incorrectly described as spanning over 0x1000 address bytes.
Even though this is what the Allwinner documentation indicates,
precedence from other SoCs such as the R40 suggests that this is not
actually the case.

This reduces the system controller address span up to the NMI
controller and adds a node for the controller, with its dedicated
compatible.

While the interrupt number was found in Allwinner's documentation,
the address for the controller is specified in any Allwinner SDK
supporting sun8iw8 (V3/V3s) at:
drivers/power/axp_power/axp20/axp20-board.c

It was tested to work on a V3 board with an AXP209 connected to the
NMI interrupt line.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 7b2d684aeb97..d2e2abd3869a 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -157,12 +157,20 @@ mixer0_out_tcon0: endpoint {
 		syscon: system-control@1c00000 {
 			compatible = "allwinner,sun8i-v3s-system-control",
 				     "allwinner,sun8i-h3-system-control";
-			reg = <0x01c00000 0x1000>;
+			reg = <0x01c00000 0xd0>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
 		};
 
+		nmi_intc: interrupt-controller@1c000d0 {
+			compatible = "allwinner,sun8i-v3s-sc-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01c000d0 0x0c>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		tcon0: lcd-controller@1c0c000 {
 			compatible = "allwinner,sun8i-v3s-tcon";
 			reg = <0x01c0c000 0x1000>;
-- 
2.29.1

[PATCH v2 4/6] ARM: dts: sun8i: Cleanup the Pinecube AXP209 node

[Paul Kocialkowski]

This fixes a few things with the Pinecube AXP209 node:
- No compatible is required since it is using an AXP209 (not AXP203)
  according to the schematics and this is what the included axp209.dtsi
  already has;
- The interrupt-controller and #interrupt-cells properties are already
  described in the included axp209.dtsi;
- The interrupt comes through the NMI controller, not directly through
  the GIC.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/boot/dts/sun8i-s3-pinecube.dts | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
index 9bab6b7f4014..ed6b4e94088d 100644
--- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts
+++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
@@ -88,13 +88,9 @@ &i2c0 {
 	status = "okay";
 
 	axp209: pmic@34 {
-		compatible = "x-powers,axp203",
-			     "x-powers,axp209";
 		reg = <0x34>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 	};
 };
 
-- 
2.29.1

[PATCH v2 5/6] dt-bindings: arm: sunxi: Add SL631 with IMX179 bindings

[Paul Kocialkowski]

This adds documentation for the compatible strings of the
SL631 Action Camera with IMX179.

Note that the device is sold under various different names, such as the
SJCAM SJ4000 Air or F60 Action Camera. This is a similar situation to
the Q8 tablets and just like them, the allwinner vendor is used as
fallback.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index afa00268c7db..8500ad61e7e2 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -754,6 +754,12 @@ properties:
           - const: sinlinx,sina33
           - const: allwinner,sun8i-a33
 
+      - description: SL631 Action Camera with IMX179
+        items:
+          - const: allwinner,sl631-imx179
+          - const: allwinner,sl631
+          - const: allwinner,sun8i-v3
+
       - description: Tanix TX6
         items:
           - const: oranth,tanix-tx6
-- 
2.29.1

[PATCH v2 6/6] ARM: dts: sun8i-v3: Add support for the SL631 Action Camera with IMX179

[Paul Kocialkowski]

The SL631 is a family of Allwinner V3 action cameras sold under
various names, such as SJCAM SJ4000 Air or F60 Action Camera.

Devices in this family share a common board design but can be found
with different image sensors, including the IMX179 and the OV4689.

This adds support for a common dtsi for the SL631 family as well as
a specific dts for the IMX179 fashion, which will later be populated
with an IMX179 node when a driver is available.

Features that were tested on the device include:
- UART debug
- MMC
- USB peripheral (e.g. g_ether)
- Buttons
- SPI NOR flash

Note that the exact designer/vendor of these boards is unknown.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/boot/dts/Makefile                  |   1 +
 arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts |  12 ++
 arch/arm/boot/dts/sun8i-v3-sl631.dtsi       | 138 ++++++++++++++++++++
 3 files changed, 151 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts
 create mode 100644 arch/arm/boot/dts/sun8i-v3-sl631.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4363ba564bb4..b76bcda9a9df 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1196,6 +1196,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-s3-lichee-zero-plus.dtb \
 	sun8i-s3-pinecube.dtb \
 	sun8i-t3-cqa3t-bv3.dtb \
+	sun8i-v3-sl631-imx179.dtb \
 	sun8i-v3s-licheepi-zero.dtb \
 	sun8i-v3s-licheepi-zero-dock.dtb \
 	sun8i-v40-bananapi-m2-berry.dtb
diff --git a/arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts b/arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts
new file mode 100644
index 000000000000..117aeece4e55
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v3-sl631-imx179.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2020 Paul Kocialkowski <contact@paulk.fr>
+ */
+
+#include "sun8i-v3-sl631.dtsi"
+
+/ {
+	model = "SL631 Action Camera with IMX179";
+	compatible = "allwinner,sl631-imx179", "allwinner,sl631",
+		     "allwinner,sun8i-v3";
+};
diff --git a/arch/arm/boot/dts/sun8i-v3-sl631.dtsi b/arch/arm/boot/dts/sun8i-v3-sl631.dtsi
new file mode 100644
index 000000000000..26648ab909bf
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v3-sl631.dtsi
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2020 Paul Kocialkowski <contact@paulk.fr>
+ */
+
+/dts-v1/;
+
+#include "sun8i-v3.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "SL631 Action Camera";
+	compatible = "allwinner,sl631", "allwinner,sun8i-v3";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	axp209: pmic@34 {
+		reg = <0x34>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pb_pins>;
+	status = "okay";
+};
+
+&lradc {
+	vref-supply = <&reg_ldo2>;
+	status = "okay";
+
+	button-174 {
+		label = "Volume Down";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <174603>;
+	};
+
+	button-384 {
+		label = "Volume Up";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <384126>;
+	};
+
+	button-593 {
+		label = "Home";
+		linux,code = <KEY_HOME>;
+		channel = <0>;
+		voltage = <593650>;
+	};
+};
+
+&mmc0 {
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+	bus-width = <4>;
+	vmmc-supply = <&reg_dcdc3>;
+	status = "okay";
+};
+
+&pio {
+	vcc-pd-supply = <&reg_dcdc3>;
+	vcc-pe-supply = <&reg_dcdc3>;
+};
+
+#include "axp209.dtsi"
+
+&ac_power_supply {
+	status = "okay";
+};
+
+&battery_power_supply {
+	status = "okay";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1250000>;
+	regulator-max-microvolt = <1250000>;
+	regulator-name = "vdd-sys-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vdd-3v3";
+};
+
+&reg_ldo1 {
+	regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&spi0 {
+	status = "okay";
+
+	spi-flash@0 {
+		reg = <0>;
+		compatible = "macronix,mx25l6436f", "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_pg_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};
-- 
2.29.1

Re: [PATCH v2 2/6] irqchip/sunxi-nmi: Add support for the V3s NMI

[Samuel Holland]

On 11/3/20 2:50 PM, Paul Kocialkowski wrote:
> The V3s/V3 has a NMI IRQ controller, which is mainly used for the AXP209
> interrupt. In great wisdom, Allwinner decided to invert the enable and
> pending register offsets, compared to the A20.
> 
> As a result, a specific compatible and register description is required
> for the V3s. This was tested with an AXP209 on a V3 board.
> 
> Acked-by: Maxime Ripard <mripard@kernel.org>
> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> ---
>  drivers/irqchip/irq-sunxi-nmi.c | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
> index a412b5d5d0fa..59e0e4612ef7 100644
> --- a/drivers/irqchip/irq-sunxi-nmi.c
> +++ b/drivers/irqchip/irq-sunxi-nmi.c
> @@ -44,6 +44,10 @@
>  #define SUN7I_NMI_PENDING	0x04
>  #define SUN7I_NMI_ENABLE	0x08
>  
> +#define SUN8I_V3S_NMI_CTRL	0x00
> +#define SUN8I_V3S_NMI_ENABLE	0x04
> +#define SUN8I_V3S_NMI_PENDING	0x08
> +
>  #define SUN9I_NMI_CTRL		0x00
>  #define SUN9I_NMI_ENABLE	0x04
>  #define SUN9I_NMI_PENDING	0x08

These two sets of definitions are the same. So it would make sense for
V3S and sun9i to share a configuration, instead of creating a copy.

> @@ -79,6 +83,12 @@ static const struct sunxi_sc_nmi_reg_offs sun7i_reg_offs __initconst = {
>  	.enable	= SUN7I_NMI_ENABLE,
>  };
>  
> +static const struct sunxi_sc_nmi_reg_offs sun8i_v3s_reg_offs __initconst = {
> +	.ctrl	= SUN8I_V3S_NMI_CTRL,
> +	.pend	= SUN8I_V3S_NMI_PENDING,
> +	.enable	= SUN8I_V3S_NMI_ENABLE,
> +};
> +
>  static const struct sunxi_sc_nmi_reg_offs sun9i_reg_offs __initconst = {
>  	.ctrl	= SUN9I_NMI_CTRL,
>  	.pend	= SUN9I_NMI_PENDING,
> @@ -165,7 +175,6 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
>  	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
>  	int ret;
>  
> -
>  	domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
>  	if (!domain) {
>  		pr_err("Could not register interrupt domain.\n");
> @@ -254,6 +263,13 @@ static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
>  }
>  IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
>  
> +static int __init sun8i_v3s_sc_nmi_irq_init(struct device_node *node,
> +					    struct device_node *parent)
> +{
> +	return sunxi_sc_nmi_irq_init(node, &sun8i_v3s_reg_offs);
> +}
> +IRQCHIP_DECLARE(sun8i_v3s_sc_nmi, "allwinner,sun8i-v3s-sc-nmi", sun8i_v3s_sc_nmi_irq_init);
> +
>  static int __init sun9i_nmi_irq_init(struct device_node *node,
>  				     struct device_node *parent)
>  {
> 

Re: [PATCH v2 2/6] irqchip/sunxi-nmi: Add support for the V3s NMI

[Paul Kocialkowski]

[-- Attachment #1: Type: text/plain, Size: 3301 bytes --]

Hi Samuel,

On Wed 04 Nov 20, 22:14, Samuel Holland wrote:
> On 11/3/20 2:50 PM, Paul Kocialkowski wrote:
> > The V3s/V3 has a NMI IRQ controller, which is mainly used for the AXP209
> > interrupt. In great wisdom, Allwinner decided to invert the enable and
> > pending register offsets, compared to the A20.
> > 
> > As a result, a specific compatible and register description is required
> > for the V3s. This was tested with an AXP209 on a V3 board.
> > 
> > Acked-by: Maxime Ripard <mripard@kernel.org>
> > Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> > ---
> >  drivers/irqchip/irq-sunxi-nmi.c | 18 +++++++++++++++++-
> >  1 file changed, 17 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
> > index a412b5d5d0fa..59e0e4612ef7 100644
> > --- a/drivers/irqchip/irq-sunxi-nmi.c
> > +++ b/drivers/irqchip/irq-sunxi-nmi.c
> > @@ -44,6 +44,10 @@
> >  #define SUN7I_NMI_PENDING	0x04
> >  #define SUN7I_NMI_ENABLE	0x08
> >  
> > +#define SUN8I_V3S_NMI_CTRL	0x00
> > +#define SUN8I_V3S_NMI_ENABLE	0x04
> > +#define SUN8I_V3S_NMI_PENDING	0x08
> > +
> >  #define SUN9I_NMI_CTRL		0x00
> >  #define SUN9I_NMI_ENABLE	0x04
> >  #define SUN9I_NMI_PENDING	0x08
> 
> These two sets of definitions are the same. So it would make sense for
> V3S and sun9i to share a configuration, instead of creating a copy.

Oh but that's true! I initially though it was the same as sun7i, found that it
wasn't but didn't notice about sun9i.

So I think we can just use the sun9i compatible after all.

Thanks!

Paul

> > @@ -79,6 +83,12 @@ static const struct sunxi_sc_nmi_reg_offs sun7i_reg_offs __initconst = {
> >  	.enable	= SUN7I_NMI_ENABLE,
> >  };
> >  
> > +static const struct sunxi_sc_nmi_reg_offs sun8i_v3s_reg_offs __initconst = {
> > +	.ctrl	= SUN8I_V3S_NMI_CTRL,
> > +	.pend	= SUN8I_V3S_NMI_PENDING,
> > +	.enable	= SUN8I_V3S_NMI_ENABLE,
> > +};
> > +
> >  static const struct sunxi_sc_nmi_reg_offs sun9i_reg_offs __initconst = {
> >  	.ctrl	= SUN9I_NMI_CTRL,
> >  	.pend	= SUN9I_NMI_PENDING,
> > @@ -165,7 +175,6 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
> >  	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
> >  	int ret;
> >  
> > -
> >  	domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
> >  	if (!domain) {
> >  		pr_err("Could not register interrupt domain.\n");
> > @@ -254,6 +263,13 @@ static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
> >  }
> >  IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
> >  
> > +static int __init sun8i_v3s_sc_nmi_irq_init(struct device_node *node,
> > +					    struct device_node *parent)
> > +{
> > +	return sunxi_sc_nmi_irq_init(node, &sun8i_v3s_reg_offs);
> > +}
> > +IRQCHIP_DECLARE(sun8i_v3s_sc_nmi, "allwinner,sun8i-v3s-sc-nmi", sun8i_v3s_sc_nmi_irq_init);
> > +
> >  static int __init sun9i_nmi_irq_init(struct device_node *node,
> >  				     struct device_node *parent)
> >  {
> > 
> 

-- 
Developer of free digital technology and hardware support.

Website: https://www.paulk.fr/
Coding blog: https://code.paulk.fr/
Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/

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Re: [PATCH v2 1/6] dt-bindings: irq: sun7i-nmi: Add binding documentation for the V3s NMI

[Rob Herring]

On Tue, 03 Nov 2020 21:50:53 +0100, Paul Kocialkowski wrote:
> Due to a register layout that's different from any other supported
> Allwinner SoC, the NMI interrupt controller takes a specific compatible
> for the V3s. Add it to the device-tree bindings documentation.
> 
> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> ---
>  .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml         | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 5/6] dt-bindings: arm: sunxi: Add SL631 with IMX179 bindings

[Rob Herring]

On Tue, 03 Nov 2020 21:50:57 +0100, Paul Kocialkowski wrote:
> This adds documentation for the compatible strings of the
> SL631 Action Camera with IMX179.
> 
> Note that the device is sold under various different names, such as the
> SJCAM SJ4000 Air or F60 Action Camera. This is a similar situation to
> the Q8 tablets and just like them, the allwinner vendor is used as
> fallback.
> 
> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> ---
>  Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>