From: Christoph Hellwig <hch@infradead.org>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
"Kelley, Sean V" <sean.v.kelley@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>
Subject: Re: [RFC PATCH 1/9] cxl/acpi: Add an acpi_cxl module for the CXL interconnect
Date: Wed, 11 Nov 2020 07:10:06 +0000 [thread overview]
Message-ID: <20201111071006.GB7829@infradead.org> (raw)
In-Reply-To: <20201111054356.793390-2-ben.widawsky@intel.com>
On Tue, Nov 10, 2020 at 09:43:48PM -0800, Ben Widawsky wrote:
> +menuconfig CXL_BUS
> + tristate "CXL (Compute Express Link) Devices Support"
> + help
> + CXL is a bus that is electrically compatible with PCI-E, but layers
> + three protocols on that signalling (CXL.io, CXL.cache, and CXL.mem). The
> + CXL.cache protocol allows devices to hold cachelines locally, the
> + CXL.mem protocol allows devices to be fully coherent memory targets, the
> + CXL.io protocol is equivalent to PCI-E. Say 'y' to enable support for
> + the configuration and management of devices supporting these protocols.
> +
Please fix the overly long lines.
> +static void acpi_cxl_desc_init(struct acpi_cxl_desc *acpi_desc, struct device *dev)
Another overly long line.
> +{
> + dev_set_drvdata(dev, acpi_desc);
> + acpi_desc->dev = dev;
> +}
But this helper seems pretty pointless to start with.
> +static int acpi_cxl_remove(struct acpi_device *adev)
> +{
> + return 0;
> +}
The emptry remove callback is not needed.
> +/*
> + * If/when CXL support is defined by other platform firmware the kernel
> + * will need a mechanism to select between the platform specific version
> + * of this routine, until then, hard-code ACPI assumptions
> + */
> +int cxl_bus_prepared(struct pci_dev *pdev)
> +{
> + struct acpi_device *adev;
> + struct pci_dev *root_port;
> + struct device *root;
> +
> + root_port = pcie_find_root_port(pdev);
> + if (!root_port)
> + return -ENXIO;
> +
> + root = root_port->dev.parent;
> + if (!root)
> + return -ENXIO;
> +
> + adev = ACPI_COMPANION(root);
> + if (!adev)
> + return -ENXIO;
> +
> + /* TODO: OSC enabling */
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(cxl_bus_prepared);
What is the point of this function? I doesn't realy do anything,
not even a CXL specific check.
>
> +/*******************************************************************************
> + *
> + * CEDT - CXL Early Discovery Table (ACPI 6.4)
> + * Version 1
> + *
> + ******************************************************************************/
> +
Pleae use the normal Linux comment style.
> +#define ACPI_CEDT_CHBS_VERSION_CXL11 (0)
> +#define ACPI_CEDT_CHBS_VERSION_CXL20 (1)
> +
> +/* Values for length field above */
> +
> +#define ACPI_CEDT_CHBS_LENGTH_CXL11 (0x2000)
> +#define ACPI_CEDT_CHBS_LENGTH_CXL20 (0x10000)
No need for the braces.
next prev parent reply other threads:[~2020-11-11 7:10 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-11 5:43 [RFC PATCH 0/9] CXL 2.0 Support Ben Widawsky
2020-11-11 5:43 ` [RFC PATCH 1/9] cxl/acpi: Add an acpi_cxl module for the CXL interconnect Ben Widawsky
2020-11-11 6:17 ` Randy Dunlap
2020-11-11 7:10 ` Christoph Hellwig [this message]
2020-11-11 7:30 ` Verma, Vishal L
2020-11-11 7:34 ` hch
2020-11-11 7:36 ` Verma, Vishal L
2020-11-11 23:03 ` Bjorn Helgaas
2020-11-16 17:59 ` Jonathan Cameron
2020-11-16 18:23 ` Verma, Vishal L
2020-11-17 14:32 ` Rafael J. Wysocki
2020-11-17 21:45 ` Dan Williams
2020-11-18 11:14 ` Rafael J. Wysocki
2020-11-11 5:43 ` [RFC PATCH 2/9] cxl/acpi: add OSC support Ben Widawsky
2020-11-16 17:59 ` Jonathan Cameron
2020-11-16 23:25 ` Dan Williams
2020-11-18 12:25 ` Rafael J. Wysocki
2020-11-18 17:58 ` Dan Williams
2020-11-11 5:43 ` [RFC PATCH 3/9] cxl/mem: Add a driver for the type-3 mailbox Ben Widawsky
2020-11-11 6:17 ` Randy Dunlap
2020-11-11 7:12 ` Christoph Hellwig
2020-11-11 17:17 ` Dan Williams
2020-11-11 18:27 ` Dan Williams
2020-11-11 21:41 ` Randy Dunlap
2020-11-11 22:40 ` Dan Williams
2020-11-16 16:56 ` Christoph Hellwig
2020-11-13 18:17 ` Bjorn Helgaas
2020-11-14 1:08 ` Ben Widawsky
2020-11-15 0:23 ` Dan Williams
2020-11-17 14:49 ` Jonathan Cameron
2020-12-04 7:22 ` Dan Williams
2020-12-04 7:27 ` Dan Williams
2020-12-04 17:39 ` Jonathan Cameron
2020-11-11 5:43 ` [RFC PATCH 4/9] cxl/mem: Map memory device registers Ben Widawsky
2020-11-13 18:17 ` Bjorn Helgaas
2020-11-14 1:12 ` Ben Widawsky
2020-11-16 23:19 ` Dan Williams
2020-11-17 0:23 ` Bjorn Helgaas
2020-11-23 19:20 ` Ben Widawsky
2020-11-23 19:32 ` Dan Williams
2020-11-23 19:58 ` Ben Widawsky
2020-11-17 15:00 ` Jonathan Cameron
2020-11-11 5:43 ` [RFC PATCH 5/9] cxl/mem: Find device capabilities Ben Widawsky
2020-11-13 18:26 ` Bjorn Helgaas
2020-11-14 1:36 ` Ben Widawsky
2020-11-17 15:15 ` Jonathan Cameron
2020-11-24 0:17 ` Ben Widawsky
2020-11-26 6:05 ` Jon Masters
2020-11-26 18:18 ` Ben Widawsky
2020-12-04 7:35 ` Dan Williams
2020-12-04 7:41 ` Dan Williams
2020-12-07 6:12 ` Ben Widawsky
2020-11-11 5:43 ` [RFC PATCH 6/9] cxl/mem: Initialize the mailbox interface Ben Widawsky
2020-11-17 15:22 ` Jonathan Cameron
2020-11-11 5:43 ` [RFC PATCH 7/9] cxl/mem: Implement polled mode mailbox Ben Widawsky
2020-11-13 23:14 ` Bjorn Helgaas
2020-11-17 15:31 ` Jonathan Cameron
2020-11-17 16:34 ` Ben Widawsky
2020-11-17 18:06 ` Jonathan Cameron
2020-11-17 18:38 ` Dan Williams
2020-11-11 5:43 ` [RFC PATCH 8/9] cxl/mem: Register CXL memX devices Ben Widawsky
2020-11-17 15:56 ` Jonathan Cameron
2020-11-20 2:16 ` Dan Williams
2020-11-20 15:20 ` Jonathan Cameron
2020-11-11 5:43 ` [RFC PATCH 9/9] MAINTAINERS: Add maintainers of the CXL driver Ben Widawsky
2020-11-11 22:06 ` [RFC PATCH 0/9] CXL 2.0 Support Ben Widawsky
2020-11-11 22:43 ` Bjorn Helgaas
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