From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: mturquette@baylibre.com
Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de,
john@phrozen.org, gregkh@linuxfoundation.org,
gch981213@gmail.com, hackpascal@gmail.com,
jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mips@vger.kernel.org, devel@driverdev.osuosl.org,
neil@brown.name
Subject: [PATCH v2 1/5] dt-bindings: clock: add dt binding header for mt7621 clocks
Date: Fri, 13 Nov 2020 10:10:42 +0100 [thread overview]
Message-ID: <20201113091046.30964-2-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20201113091046.30964-1-sergio.paracuellos@gmail.com>
Adds dt binding header for 'mediatek,mt7621-clk' clocks.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
include/dt-bindings/clock/mt7621-clk.h | 41 ++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index 000000000000..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL 0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M 4
+#define MT7621_CLK_150M 5
+#define MT7621_CLK_250M 6
+#define MT7621_CLK_270M 7
+
+#define MT7621_CLK_HSDMA 8
+#define MT7621_CLK_FE 9
+#define MT7621_CLK_SP_DIVTX 10
+#define MT7621_CLK_TIMER 11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA 14
+#define MT7621_CLK_NAND 15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1 19
+#define MT7621_CLK_UART2 20
+#define MT7621_CLK_UART3 21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0 23
+#define MT7621_CLK_PCIE1 24
+#define MT7621_CLK_PCIE2 25
+#define MT7621_CLK_CRYPTO 26
+#define MT7621_CLK_SHXC 27
+
+#define MT7621_CLK_MAX 28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
--
2.25.1
next prev parent reply other threads:[~2020-11-13 9:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-13 9:10 [PATCH v2 0/5] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621 Sergio Paracuellos
2020-11-13 9:10 ` Sergio Paracuellos [this message]
2020-11-13 9:10 ` [PATCH v2 2/5] dt: bindings: add mt7621-clk device tree binding documentation Sergio Paracuellos
2020-11-13 9:10 ` [PATCH v2 3/5] clk: ralink: add clock driver for mt7621 SoC Sergio Paracuellos
2020-11-13 9:10 ` [PATCH v2 4/5] staging: mt7621-dts: make use of new 'mt7621-clk' Sergio Paracuellos
2020-11-13 9:10 ` [PATCH v2 5/5] MAINTAINERS: add MT7621 CLOCK maintainer Sergio Paracuellos
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