From: Vinod Koul <vkoul@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Swapnil Kashinath Jakhade <sjakhade@cadence.com>,
Milind Parab <mparab@cadence.com>,
Yuti Suresh Amonkar <yamonkar@cadence.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 5/9] phy: cadence: Sierra: Fix PHY power_on sequence
Date: Mon, 16 Nov 2020 13:02:39 +0530 [thread overview]
Message-ID: <20201116073239.GJ7499@vkoul-mobl> (raw)
In-Reply-To: <20201103035556.21260-6-kishon@ti.com>
On 03-11-20, 09:25, Kishon Vijay Abraham I wrote:
> Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
> de-asserts PHY_RESET even before the configurations are loaded in
> phy_init(). However PHY_RESET should be de-asserted only after
> all the configurations has been initialized, instead of de-asserting
> in probe. Fix it here.
Move this up in series..? Also I think we should apply this to fixes and
perhaps cc stable..?
>
> Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/phy/cadence/phy-cadence-sierra.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
> index 4429f41a8f58..e08548417bce 100644
> --- a/drivers/phy/cadence/phy-cadence-sierra.c
> +++ b/drivers/phy/cadence/phy-cadence-sierra.c
> @@ -319,6 +319,12 @@ static int cdns_sierra_phy_on(struct phy *gphy)
> u32 val;
> int ret;
>
> + ret = reset_control_deassert(sp->phy_rst);
> + if (ret) {
> + dev_err(dev, "Failed to take the PHY out of reset\n");
> + return ret;
> + }
> +
> /* Take the PHY lane group out of reset */
> ret = reset_control_deassert(ins->lnk_rst);
> if (ret) {
> @@ -621,7 +627,6 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
>
> pm_runtime_enable(dev);
> phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> - reset_control_deassert(sp->phy_rst);
> return PTR_ERR_OR_ZERO(phy_provider);
>
> put_child:
> --
> 2.17.1
--
~Vinod
next prev parent reply other threads:[~2020-11-16 7:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-03 3:55 [PATCH 0/9] PHY: Enhance Sierra SERDES Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 1/9] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Kishon Vijay Abraham I
2020-11-05 18:03 ` Rob Herring
2020-12-21 3:10 ` Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 2/9] phy: ti: j721e-wiz: Get PHY properties only for "phy" subnode Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 3/9] phy: ti: j721e-wiz: Don't configure wiz if its already configured Kishon Vijay Abraham I
2020-11-16 7:30 ` Vinod Koul
2021-03-09 12:13 ` Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 4/9] phy: cadence: cadence-sierra: Create PHY only for "phy" sub-nodes Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 5/9] phy: cadence: Sierra: Fix PHY power_on sequence Kishon Vijay Abraham I
2020-11-16 7:32 ` Vinod Koul [this message]
2020-11-03 3:55 ` [PATCH 6/9] phy: cadence: sierra: Don't configure if any plls are already locked Kishon Vijay Abraham I
2020-11-09 8:39 ` Philipp Zabel
2020-11-03 3:55 ` [PATCH 7/9] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 8/9] phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 9/9] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Kishon Vijay Abraham I
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