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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id t6sm4816069ooo.22.2020.11.16.07.27.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 07:27:19 -0800 (PST) Received: (nullmailer pid 1678651 invoked by uid 1000); Mon, 16 Nov 2020 15:27:18 -0000 Date: Mon, 16 Nov 2020 09:27:18 -0600 From: Rob Herring To: Dongjiu Geng Cc: vkoul@kernel.org, dan.j.williams@intel.com, p.zabel@pengutronix.de, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] dt: bindings: dma: Add DT bindings for HiSilicon Hiedma Controller Message-ID: <20201116152718.GA1646380@bogus> References: <20201114003440.36458-1-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201114003440.36458-1-gengdongjiu@huawei.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Nov 14, 2020 at 12:34:39AM +0000, Dongjiu Geng wrote: > The Hiedma Controller v310 Provides eight DMA channels, each > channel can be configured for one-way transfer. The data can > be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This > documentation describes DT bindings of this controller. > > Signed-off-by: Dongjiu Geng > --- > .../bindings/dma/hisilicon,hiedmacv310.yaml | 80 +++++++++++++++++++ > 1 file changed, 80 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml > > diff --git a/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml b/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml > new file mode 100644 > index 000000000000..c04603316b40 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml > @@ -0,0 +1,80 @@ > +# SPDX-License-Identifier: GPL-2.0-only Dual license new bindings. GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/hisilicon,hiedmacv310.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: HiSilicon Hiedma Controller v310 Device Tree Bindings > + > +description: | > + These bindings describe the DMA engine included in the HiSilicon Hiedma > + Controller v310 Device. > + > +maintainers: > + - Dongjiu Geng > + > +allOf: > + - $ref: "dma-controller.yaml#" > + > +properties: > + "#dma-cells": > + const: 2 > + > + compatible: > + const: hisilicon,hiedmacv310_n s/_/-/ > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: apb clock > + - description: axi clock > + > + clock-names: > + items: > + - const: apb_pclk > + - const: axi_aclk > + > +required: > + - "#dma-cells" > + - "#clock-cells" > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - resets > + - reset-names Not documented. > + - dma-requests > + - dma-channels > + - devid What's this? It's not defined. If a device index, we don't do device indices in DT. > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + dma: dma-controller@10040000 { > + compatible = "hisilicon,hiedmacv310_n"; > + reg = <0x10040000 0x1000>; > + misc_regmap = <&misc_ctrl>; > + misc_ctrl_base = <0x144>; > + interrupts = <0 82 4>; > + clocks = <&clock HI3559AV100_EDMAC1_CLK>, <&clock HI3559AV100_EDMAC1_AXICLK>; > + clock-names = "apb_pclk", "axi_aclk"; > + #clock-cells = <2>; > + resets = <&clock 0x16c 7>; > + reset-names = "dma-reset"; > + dma-requests = <32>; > + dma-channels = <8>; > + devid = <1>; > + #dma-cells = <2>; > + }; > + > +... > -- > 2.17.1 >