From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1152C63798 for ; Mon, 16 Nov 2020 23:38:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F99124198 for ; Mon, 16 Nov 2020 23:38:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="sJ+vgHji" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730758AbgKPXiM (ORCPT ); Mon, 16 Nov 2020 18:38:12 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:46893 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729977AbgKPXiM (ORCPT ); Mon, 16 Nov 2020 18:38:12 -0500 X-Greylist: delayed 5940 seconds by postgrey-1.27 at vger.kernel.org; Mon, 16 Nov 2020 18:38:10 EST Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id BD383806A8; Tue, 17 Nov 2020 12:38:08 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1605569888; bh=PCTZxln1VKZDYtPBvimsiWg1lsnUSwv12kxkUAuwmrI=; h=From:To:Cc:Subject:Date; b=sJ+vgHjiIMKVl78mx6OaExKYrZRu0+9ffhe4d7d5hqJc98A0vHtZB1Pw5vqME7+9a f8X/bgg6QditR1aHGK+rFJeKxEmSkIkSTtnNOTnQaVd4jrB7UX5n3ESbFD2KYGN/i0 d3CAp7KiD7YSXdWCWWmF8dw9MAQbdkDXQtJtPUOx5tfRutr6oPYLMtVW1qlxdUw/Kc ryj2J05oDRiWJU+Nwnl4czHP6NJY646xJzrih/LsgJsnAOnFoZ66Zn2cQ9fvadj5J8 WG8AkzGdl8OAS162cSj8vVNxyCugJsS/8UQ12wvhrmVMXen0gfOll0OqBmlHPgudMj ecESL+D6tvj3A== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Tue, 17 Nov 2020 12:38:07 +1300 Received: from markto-dl.ws.atlnz.lc (markto-dl.ws.atlnz.lc [10.33.23.25]) by smtp (Postfix) with ESMTP id D572E13ED56; Tue, 17 Nov 2020 12:38:03 +1300 (NZDT) Received: by markto-dl.ws.atlnz.lc (Postfix, from userid 1155) id 14032340FC9; Tue, 17 Nov 2020 12:38:04 +1300 (NZDT) From: Mark Tomlinson To: rjui@broadcom.com, sbranden@broadcom.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Tomlinson Subject: [PATCH] pinctrl: bcm: pinctrl-nsp-gpio: Fix setting GPIO as output Date: Tue, 17 Nov 2020 12:37:57 +1300 Message-Id: <20201116233757.15409-1-mark.tomlinson@alliedtelesis.co.nz> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When setting a GPIO pin to an output, it is important to set the value correctly before enabling the output so that a glitch is not seen on the pin. This glitch may be very short, but can be important if this is a reset signal. Fixes: 8bfcbbbcabe0 ("pinctrl: nsp: add gpio-a driver support for Broadco= m NSP SoC") Signed-off-by: Mark Tomlinson --- drivers/pinctrl/bcm/pinctrl-nsp-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm= /pinctrl-nsp-gpio.c index a00a42a61a90..942f04ca4868 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -289,8 +289,8 @@ static int nsp_gpio_direction_output(struct gpio_chip= *gc, unsigned gpio, unsigned long flags; =20 raw_spin_lock_irqsave(&chip->lock, flags); - nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true); nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); + nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true); raw_spin_unlock_irqrestore(&chip->lock, flags); =20 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); --=20 2.29.2