From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E983EC6369E for ; Tue, 17 Nov 2020 02:39:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B6D292469D for ; Tue, 17 Nov 2020 02:39:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727608AbgKQCjZ (ORCPT ); Mon, 16 Nov 2020 21:39:25 -0500 Received: from mga04.intel.com ([192.55.52.120]:52576 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727482AbgKQCjX (ORCPT ); Mon, 16 Nov 2020 21:39:23 -0500 IronPort-SDR: rI1IP4Nmlgs9G9NHAKTJV0lOd7RwtgMHKBMKn2OZu8dqzCLnGnNh2o70KU6knzljgCdM1IWu1b TFBApSpZJsSw== X-IronPort-AV: E=McAfee;i="6000,8403,9807"; a="168274117" X-IronPort-AV: E=Sophos;i="5.77,484,1596524400"; d="scan'208";a="168274117" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2020 18:39:23 -0800 IronPort-SDR: pnQnnQoUht6oCx03o1gFgST3/vExmvYCidK67wZqAoN72d+Av75JUVeJZ727/XlEb+KICfusIC /Au0COsKUwGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,484,1596524400"; d="scan'208";a="358706155" Received: from jsia-hp-z620-workstation.png.intel.com ([10.221.118.135]) by fmsmga004.fm.intel.com with ESMTP; 16 Nov 2020 18:39:21 -0800 From: Sia Jee Heng To: vkoul@kernel.org, Eugeniy.Paltsev@synopsys.com, robh+dt@kernel.org Cc: andriy.shevchenko@linux.intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 15/15] dmaengine: dw-axi-dmac: Set constraint to the Max segment size Date: Tue, 17 Nov 2020 10:22:15 +0800 Message-Id: <20201117022215.2461-16-jee.heng.sia@intel.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201117022215.2461-1-jee.heng.sia@intel.com> References: <20201117022215.2461-1-jee.heng.sia@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can handle the AxiDMA limitation. Without supporting DMA constraint the default Max segment size reported by dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA. Reviewed-by: Andy Shevchenko Signed-off-by: Sia Jee Heng --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 ++++++++ drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index cc05f66c7a4f..e20d8d4b1dff 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1347,6 +1348,13 @@ static int dw_probe(struct platform_device *pdev) dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg; dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic; + /* + * Synopsis DesignWare AxiDMA datasheet mentioned Maximum + * supported blocks is 1024. Device register width is 4 bytes. + * Therefore, set constraint to 1024 * 4. + */ + dw->dma.dev->dma_parms = &dw->dma_parms; + dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE); platform_set_drvdata(pdev, chip); pm_runtime_enable(chip->dev); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index f64e8d33b127..67669049cead 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -54,6 +54,7 @@ struct axi_dma_chan { struct dw_axi_dma { struct dma_device dma; struct dw_axi_dma_hcfg *hdata; + struct device_dma_parameters dma_parms; /* channels */ struct axi_dma_chan *chan; -- 2.18.0