From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDC71C388F9 for ; Thu, 19 Nov 2020 05:56:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6C81E246F1 for ; Thu, 19 Nov 2020 05:56:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726249AbgKSF4A (ORCPT ); Thu, 19 Nov 2020 00:56:00 -0500 Received: from mga02.intel.com ([134.134.136.20]:15558 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725802AbgKSF4A (ORCPT ); Thu, 19 Nov 2020 00:56:00 -0500 IronPort-SDR: 5RUsDhwvmNKemmHVOsKttUWtekwayyv5XUe1n37yaMvFbZna9SkAUSOQClSiOaI/d5KWvgH5Q0 OQX16A9gTjYQ== X-IronPort-AV: E=McAfee;i="6000,8403,9809"; a="158271207" X-IronPort-AV: E=Sophos;i="5.77,489,1596524400"; d="scan'208";a="158271207" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2020 21:55:59 -0800 IronPort-SDR: qhCoXBTzx2RuVGZpT419s2GlRQj2B8oe99XSfRrEo6ipEeTIBJQHj8BdwfdjV3R0P0F6iOrXWk /KA41RtV5BvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,489,1596524400"; d="scan'208";a="330800049" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga006.jf.intel.com with ESMTP; 18 Nov 2020 21:55:57 -0800 From: "Ramuthevar,Vadivel MuruganX" To: broonie@kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: linux-mtd@lists.infradead.org, vigneshr@ti.com, p.yadav@ti.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, "Ramuthevar,Vadivel MuruganX" Subject: [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Date: Thu, 19 Nov 2020 13:55:48 +0800 Message-Id: <20201119055551.26493-1-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add QSPI controller support for Intel LGM SoC. Note from Vignesh(mtd subsystem maintainer): This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX that intended to move cadence-quadspi driver to spi-mem framework Those patches were trying to accomplish too many things in a single set of patches and need to split into smaller patches. This is reduced version of above series. Changes that are intended to make migration easy are split into separate patches. Patches 1 to 3 drop features that cannot be supported under spi-mem at the moment (backward compatibility is maintained). Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to spi-mem and patch 7 moves the driver to drivers/spi folder. I have tested both INDAC mode (used by non TI platforms like Altera SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs. Patches to move move bindings over to "Documentation/devicetree/bindings/spi/" directory and also conversion of bindig doc to YAML will be posted separately. Support for Intel platform would follow that. Reference: https://lkml.org/lkml/2020/6/1/50 --- v8: - As Mark suggested to add the dt-bindings documentation patches end of the series , so dropped. v7: - Rob's review comments address and fixed dt-schema warning - Pratyush review comments address and update - DAC bit reset to 0 and 1 (enable/disable) - tested QSI-NOR flash mx25l12805d on LGM soc, it's working after disable DAC - Linus suggested to use 'num-cs' prperty instead of 'num-chipselect' v6: - Rob's review comments update - add compatible string in properly aligned - remove cadence-qspi extra comaptible string in example v5: - Rob's review comments update - const with single compatible string kept v4: - Rob's review comments update - remove '|' no formatting to preserve - child node attributes follows under 'properties' under '@[0-9a-f]+$'. v3: - Pratyush review comments update - CQSPI_SUPPORTS_MULTI_CHIPSELECT macro used instead of cqspi->use_direct_mode - disable DAC support placed in end of controller_init v2: - Rob's review comments update for dt-bindings - add 'oneOf' for compatible selection - drop un-neccessary descriptions - add the cdns,is-decoded-cs and cdns,rclk-en properties as schema - remove 'allOf' in not required place - add AdditionalProperties false - add minItems/maxItems for qspi reset attributes resend-v1: - As per Mark's suggestion , reorder the patch series 1-3 driver support patches, series 4-6 dt-bindings patches. v1: - initial version Ramuthevar Vadivel Murugan (6): spi: cadence-quadspi: Add QSPI support for Intel LGM SoC spi: cadence-quadspi: Disable the DAC for Intel LGM SoC spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml dt-bindings: spi: Add compatible for Intel LGM SoC .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 ---------- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 148 +++++++++++++++++++++ drivers/spi/Kconfig | 2 +- drivers/spi/spi-cadence-quadspi.c | 33 ++++- 4 files changed, 178 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml -- 2.11.0