* [PATCH v8 1/6] spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
2020-11-19 5:55 [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
@ 2020-11-19 5:55 ` Ramuthevar,Vadivel MuruganX
2020-11-19 5:55 ` [PATCH v8 2/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-11-19 5:55 UTC (permalink / raw)
To: broonie, linux-kernel, linux-spi
Cc: linux-mtd, vigneshr, p.yadav, cheol.yong.kim, qi-ming.wu,
Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Add QSPI controller support for Intel LGM SoC.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
drivers/spi/Kconfig | 2 +-
drivers/spi/spi-cadence-quadspi.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index d2c976e55b8b..926da61eee5a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -203,7 +203,7 @@ config SPI_CADENCE
config SPI_CADENCE_QUADSPI
tristate "Cadence Quad SPI controller"
- depends on OF && (ARM || ARM64 || COMPILE_TEST)
+ depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
help
Enable support for the Cadence Quad SPI Flash controller.
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 40938cf3806d..d7b10c46fa70 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1401,6 +1401,9 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "ti,am654-ospi",
.data = &am654_ospi,
},
+ {
+ .compatible = "intel,lgm-qspi",
+ },
{ /* end of table */ }
};
--
2.11.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v8 2/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
2020-11-19 5:55 [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-11-19 5:55 ` [PATCH v8 1/6] spi: cadence-quadspi: Add QSPI " Ramuthevar,Vadivel MuruganX
@ 2020-11-19 5:55 ` Ramuthevar,Vadivel MuruganX
2020-11-19 5:55 ` [PATCH v8 3/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-11-19 5:55 UTC (permalink / raw)
To: broonie, linux-kernel, linux-spi
Cc: linux-mtd, vigneshr, p.yadav, cheol.yong.kim, qi-ming.wu,
Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).
This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfe
DAC bit resets to 1 so there is no need to explicitly set it.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
drivers/spi/spi-cadence-quadspi.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index d7b10c46fa70..d12b765e87be 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1101,10 +1101,12 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
- /* Enable Direct Access Controller */
- reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
- reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
- writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+ /* Disable direct access controller */
+ if (!cqspi->use_direct_mode) {
+ reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+ reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
+ writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+ }
cqspi_controller_enable(cqspi, 1);
}
@@ -1388,6 +1390,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
.quirks = CQSPI_NEEDS_WR_DELAY,
};
+static const struct cqspi_driver_platdata intel_lgm_qspi = {
+ .quirks = CQSPI_DISABLE_DAC_MODE,
+};
+
static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
@@ -1403,6 +1409,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
},
{
.compatible = "intel,lgm-qspi",
+ .data = &intel_lgm_qspi,
},
{ /* end of table */ }
};
--
2.11.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v8 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
2020-11-19 5:55 [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-11-19 5:55 ` [PATCH v8 1/6] spi: cadence-quadspi: Add QSPI " Ramuthevar,Vadivel MuruganX
2020-11-19 5:55 ` [PATCH v8 2/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
@ 2020-11-19 5:55 ` Ramuthevar,Vadivel MuruganX
2020-11-19 12:57 ` Vignesh Raghavendra
2020-11-19 12:36 ` [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller " Vignesh Raghavendra
2020-11-19 13:06 ` Vignesh Raghavendra
4 siblings, 1 reply; 10+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-11-19 5:55 UTC (permalink / raw)
To: broonie, linux-kernel, linux-spi
Cc: linux-mtd, vigneshr, p.yadav, cheol.yong.kim, qi-ming.wu,
Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
drivers/spi/spi-cadence-quadspi.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index d12b765e87be..337778f75d5d 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -38,6 +38,7 @@
/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0)
+#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1)
struct cqspi_st;
@@ -75,6 +76,7 @@ struct cqspi_st {
bool is_decoded_cs;
u32 fifo_depth;
u32 fifo_width;
+ u32 num_chipselect;
bool rclk_en;
u32 trigger_address;
u32 wr_delay;
@@ -1049,6 +1051,7 @@ static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
{
+ const struct cqspi_driver_platdata *ddata;
struct device *dev = &cqspi->pdev->dev;
struct device_node *np = dev->of_node;
@@ -1070,6 +1073,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
return -ENXIO;
}
+ ddata = of_device_get_match_data(dev);
+ if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) {
+ if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) {
+ dev_err(dev, "couldn't determine number of cs\n");
+ return -ENXIO;
+ }
+ }
+
cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
return 0;
@@ -1302,6 +1313,9 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->current_cs = -1;
cqspi->sclk = 0;
+ if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
+ master->num_chipselect = cqspi->num_chipselect;
+
ret = cqspi_setup_flash(cqspi);
if (ret) {
dev_err(dev, "failed to setup flash parameters %d\n", ret);
@@ -1391,6 +1405,7 @@ static const struct cqspi_driver_platdata am654_ospi = {
};
static const struct cqspi_driver_platdata intel_lgm_qspi = {
+ .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT,
.quirks = CQSPI_DISABLE_DAC_MODE,
};
--
2.11.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v8 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
2020-11-19 5:55 ` [PATCH v8 3/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
@ 2020-11-19 12:57 ` Vignesh Raghavendra
2020-11-20 0:29 ` Ramuthevar, Vadivel MuruganX
0 siblings, 1 reply; 10+ messages in thread
From: Vignesh Raghavendra @ 2020-11-19 12:57 UTC (permalink / raw)
To: Ramuthevar,Vadivel MuruganX, broonie, linux-kernel, linux-spi
Cc: linux-mtd, p.yadav, cheol.yong.kim, qi-ming.wu
On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>
> Add multiple chipselect support for Intel LGM SoCs,
> currently QSPI-NOR and QSPI-NAND supported.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> ---
> drivers/spi/spi-cadence-quadspi.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
> index d12b765e87be..337778f75d5d 100644
> --- a/drivers/spi/spi-cadence-quadspi.c
> +++ b/drivers/spi/spi-cadence-quadspi.c
> @@ -38,6 +38,7 @@
>
> /* Capabilities */
> #define CQSPI_SUPPORTS_OCTAL BIT(0)
> +#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1)
>
> struct cqspi_st;
>
> @@ -75,6 +76,7 @@ struct cqspi_st {
> bool is_decoded_cs;
> u32 fifo_depth;
> u32 fifo_width;
> + u32 num_chipselect;
> bool rclk_en;
> u32 trigger_address;
> u32 wr_delay;
> @@ -1049,6 +1051,7 @@ static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
>
> static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
> {
> + const struct cqspi_driver_platdata *ddata;
Unused variable?
> struct device *dev = &cqspi->pdev->dev;
> struct device_node *np = dev->of_node;
>
> @@ -1070,6 +1073,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
> return -ENXIO;
> }
>
> + ddata = of_device_get_match_data(dev);
> + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) {
I don't see a need for this flag... Controller by default supports
multiple CS.
> + if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) {
> + dev_err(dev, "couldn't determine number of cs\n");
> + return -ENXIO;
> + }
> + }
> +
Entire hunk can be replaced with:
if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
> cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
>
> return 0;
> @@ -1302,6 +1313,9 @@ static int cqspi_probe(struct platform_device *pdev)
> cqspi->current_cs = -1;
> cqspi->sclk = 0;
>
> + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
> + master->num_chipselect = cqspi->num_chipselect;
> +
And then this becomes:
master->num_chipselect = cqspi->num_chipselect;
> ret = cqspi_setup_flash(cqspi);
> if (ret) {
> dev_err(dev, "failed to setup flash parameters %d\n", ret);
> @@ -1391,6 +1405,7 @@ static const struct cqspi_driver_platdata am654_ospi = {
> };
>
> static const struct cqspi_driver_platdata intel_lgm_qspi = {
> + .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT,
> .quirks = CQSPI_DISABLE_DAC_MODE,
> };
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
2020-11-19 12:57 ` Vignesh Raghavendra
@ 2020-11-20 0:29 ` Ramuthevar, Vadivel MuruganX
0 siblings, 0 replies; 10+ messages in thread
From: Ramuthevar, Vadivel MuruganX @ 2020-11-20 0:29 UTC (permalink / raw)
To: Vignesh Raghavendra, broonie, linux-kernel, linux-spi
Cc: linux-mtd, p.yadav, cheol.yong.kim, qi-ming.wu
Hi Vignesh,
Thank you very much for the review comments...
On 19/11/2020 8:57 pm, Vignesh Raghavendra wrote:
>
>
> On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>
>> Add multiple chipselect support for Intel LGM SoCs,
>> currently QSPI-NOR and QSPI-NAND supported.
>>
>> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>> ---
>> drivers/spi/spi-cadence-quadspi.c | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
>> index d12b765e87be..337778f75d5d 100644
>> --- a/drivers/spi/spi-cadence-quadspi.c
>> +++ b/drivers/spi/spi-cadence-quadspi.c
>> @@ -38,6 +38,7 @@
>>
>> /* Capabilities */
>> #define CQSPI_SUPPORTS_OCTAL BIT(0)
>> +#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1)
>>
>> struct cqspi_st;
>>
>> @@ -75,6 +76,7 @@ struct cqspi_st {
>> bool is_decoded_cs;
>> u32 fifo_depth;
>> u32 fifo_width;
>> + u32 num_chipselect;
>> bool rclk_en;
>> u32 trigger_address;
>> u32 wr_delay;
>> @@ -1049,6 +1051,7 @@ static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
>>
>> static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
>> {
>> + const struct cqspi_driver_platdata *ddata;
>
> Unused variable?
currently used for this check
if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) {
next patch will drop it, because the above check to be removed.
>
>> struct device *dev = &cqspi->pdev->dev;
>> struct device_node *np = dev->of_node;
>>
>> @@ -1070,6 +1073,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
>> return -ENXIO;
>> }
>>
>> + ddata = of_device_get_match_data(dev);
>> + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) {
>
> I don't see a need for this flag... Controller by default supports
> multiple CS.
Ok.
>
>> + if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) {
>> + dev_err(dev, "couldn't determine number of cs\n");
>> + return -ENXIO;
>> + }
>> + }
>> +
>
>
> Entire hunk can be replaced with:
>
> if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
> cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
Noted, thanks!
>
>
>> cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
>>
>> return 0;
>> @@ -1302,6 +1313,9 @@ static int cqspi_probe(struct platform_device *pdev)
>> cqspi->current_cs = -1;
>> cqspi->sclk = 0;
>>
>> + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
>> + master->num_chipselect = cqspi->num_chipselect;
>> +
>
> And then this becomes:
> master->num_chipselect = cqspi->num_chipselect;
Ok, Noted.
>
>> ret = cqspi_setup_flash(cqspi);
>> if (ret) {
>> dev_err(dev, "failed to setup flash parameters %d\n", ret);
>> @@ -1391,6 +1405,7 @@ static const struct cqspi_driver_platdata am654_ospi = {
>> };
>>
>> static const struct cqspi_driver_platdata intel_lgm_qspi = {
>> + .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT,
>> .quirks = CQSPI_DISABLE_DAC_MODE,
>> };
>>
>>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC
2020-11-19 5:55 [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
` (2 preceding siblings ...)
2020-11-19 5:55 ` [PATCH v8 3/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
@ 2020-11-19 12:36 ` Vignesh Raghavendra
2020-11-20 0:06 ` Ramuthevar, Vadivel MuruganX
2020-11-19 13:06 ` Vignesh Raghavendra
4 siblings, 1 reply; 10+ messages in thread
From: Vignesh Raghavendra @ 2020-11-19 12:36 UTC (permalink / raw)
To: Ramuthevar,Vadivel MuruganX, broonie, linux-kernel, linux-spi
Cc: linux-mtd, p.yadav, cheol.yong.kim, qi-ming.wu
On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
> Add QSPI controller support for Intel LGM SoC.
>
> Note from Vignesh(mtd subsystem maintainer):
> This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
> support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
> <vadivel.muruganx.ramuthevar@linux.intel.com> that intended to move
> cadence-quadspi driver to spi-mem framework
>
> Those patches were trying to accomplish too many things in a single set
> of patches and need to split into smaller patches. This is reduced
> version of above series.
>
> Changes that are intended to make migration easy are split into separate
> patches. Patches 1 to 3 drop features that cannot be supported under
> spi-mem at the moment (backward compatibility is maintained).
> Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to
> spi-mem and patch 7 moves the driver to drivers/spi folder.
>
> I have tested both INDAC mode (used by non TI platforms like Altera
> SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs.
>
> Patches to move move bindings over to
> "Documentation/devicetree/bindings/spi/" directory and also conversion
> of bindig doc to YAML will be posted separately. Support for Intel
> platform would follow that.
>
> Reference:
> https://lkml.org/lkml/2020/6/1/50
>
> ---
> v8:
> - As Mark suggested to add the dt-bindings documentation patches
> end of the series , so dropped.
Suggestion was to drop patches converting legacy binding doc to YAML schema.
You still need to include a patch documenting new compatible
"intel,lgm-qspi" in the existing (legacy) binding doc.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC
2020-11-19 12:36 ` [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller " Vignesh Raghavendra
@ 2020-11-20 0:06 ` Ramuthevar, Vadivel MuruganX
0 siblings, 0 replies; 10+ messages in thread
From: Ramuthevar, Vadivel MuruganX @ 2020-11-20 0:06 UTC (permalink / raw)
To: Vignesh Raghavendra, broonie, linux-kernel, linux-spi
Cc: linux-mtd, p.yadav, cheol.yong.kim, qi-ming.wu
Hi Vignesh,
Thank you very much for the review comments...
On 19/11/2020 8:36 pm, Vignesh Raghavendra wrote:
>
>
> On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
>> Add QSPI controller support for Intel LGM SoC.
>>
>> Note from Vignesh(mtd subsystem maintainer):H
>> This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
>> support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
>> <vadivel.muruganx.ramuthevar@linux.intel.com> that intended to move
>> cadence-quadspi driver to spi-mem framework
>>
>> Those patches were trying to accomplish too many things in a single set
>> of patches and need to split into smaller patches. This is reduced
>> version of above series.
>>
>> Changes that are intended to make migration easy are split into separate
>> patches. Patches 1 to 3 drop features that cannot be supported under
>> spi-mem at the moment (backward compatibility is maintained).
>> Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to
>> spi-mem and patch 7 moves the driver to drivers/spi folder.
>>
>> I have tested both INDAC mode (used by non TI platforms like Altera
>> SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs.
>>
>> Patches to move move bindings over to
>> "Documentation/devicetree/bindings/spi/" directory and also conversion
>> of bindig doc to YAML will be posted separately. Support for Intel
>> platform would follow that.
>>
>> Reference:
>> https://lkml.org/lkml/2020/6/1/50
>>
>> ---
>> v8:
>> - As Mark suggested to add the dt-bindings documentation patches
>> end of the series , so dropped.
>
> Suggestion was to drop patches converting legacy binding doc to YAML schema.
> You still need to include a patch documenting new compatible
> "intel,lgm-qspi" in the existing (legacy) binding doc.
Noted, will do that.
Regards
Vadivel
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC
2020-11-19 5:55 [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
` (3 preceding siblings ...)
2020-11-19 12:36 ` [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller " Vignesh Raghavendra
@ 2020-11-19 13:06 ` Vignesh Raghavendra
2020-11-20 0:34 ` Ramuthevar, Vadivel MuruganX
4 siblings, 1 reply; 10+ messages in thread
From: Vignesh Raghavendra @ 2020-11-19 13:06 UTC (permalink / raw)
To: Ramuthevar,Vadivel MuruganX, broonie, linux-kernel, linux-spi
Cc: linux-mtd, p.yadav, cheol.yong.kim, qi-ming.wu
On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
> Add QSPI controller support for Intel LGM SoC.
>
> Note from Vignesh(mtd subsystem maintainer):
> This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
> support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
> <vadivel.muruganx.ramuthevar@linux.intel.com> that intended to move
> cadence-quadspi driver to spi-mem framework
>
> Those patches were trying to accomplish too many things in a single set
> of patches and need to split into smaller patches. This is reduced
> version of above series.
>
> Changes that are intended to make migration easy are split into separate
> patches. Patches 1 to 3 drop features that cannot be supported under
> spi-mem at the moment (backward compatibility is maintained).
> Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to
> spi-mem and patch 7 moves the driver to drivers/spi folder.
>
This text no longer makes sense anymore with few patches dropped and
others reordered
> I have tested both INDAC mode (used by non TI platforms like Altera
> SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs.
>
> Patches to move move bindings over to
> "Documentation/devicetree/bindings/spi/" directory and also conversion
> of bindig doc to YAML will be posted separately. Support for Intel
> platform would follow that.
>
> Reference:
> https://lkml.org/lkml/2020/6/1/50
>
> ---
> v8:
> - As Mark suggested to add the dt-bindings documentation patches
> end of the series , so dropped.
>
> Ramuthevar Vadivel Murugan (6):
> spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
> spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
> spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
> spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
> dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml
> dt-bindings: spi: Add compatible for Intel LGM SoC
>
This is quite confusing... Summary/diffstat still shows patches 4 to 6
and so does the patch numbering in $subject while changelog says
otherwise and I received only 3 patches in my Inbox?
> .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 ----------
> .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 148 +++++++++++++++++++++
> drivers/spi/Kconfig | 2 +-
> drivers/spi/spi-cadence-quadspi.c | 33 ++++-
> 4 files changed, 178 insertions(+), 72 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>
So does the diffstat...
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v8 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC
2020-11-19 13:06 ` Vignesh Raghavendra
@ 2020-11-20 0:34 ` Ramuthevar, Vadivel MuruganX
0 siblings, 0 replies; 10+ messages in thread
From: Ramuthevar, Vadivel MuruganX @ 2020-11-20 0:34 UTC (permalink / raw)
To: Vignesh Raghavendra, broonie, linux-kernel, linux-spi
Cc: linux-mtd, p.yadav, cheol.yong.kim, qi-ming.wu
Hi Vignesh,
Thank you for the review comments...
On 19/11/2020 9:06 pm, Vignesh Raghavendra wrote:
>
>
> On 11/19/20 11:25 AM, Ramuthevar,Vadivel MuruganX wrote:
>> Add QSPI controller support for Intel LGM SoC.
>>
>> Note from Vignesh(mtd subsystem maintainer):
>> This series is a subset of "[PATCH v12 0/4] spi: cadence-quadspi: Add
>> support for the Cadence QSPI controller" by Ramuthevar,Vadivel MuruganX
>> <vadivel.muruganx.ramuthevar@linux.intel.com> that intended to move
>> cadence-quadspi driver to spi-mem framework
>>
>> Those patches were trying to accomplish too many things in a single set
>> of patches and need to split into smaller patches. This is reduced
>> version of above series.
>>
>> Changes that are intended to make migration easy are split into separate
>> patches. Patches 1 to 3 drop features that cannot be supported under
>> spi-mem at the moment (backward compatibility is maintained).
>> Patch 4-5 are trivial cleanups. Patch 6 does the actual conversion to
>> spi-mem and patch 7 moves the driver to drivers/spi folder.
>>
>
> This text no longer makes sense anymore with few patches dropped and
> others reordered
Just for reference added, will drop it.
>
>> I have tested both INDAC mode (used by non TI platforms like Altera
>> SoCFPGA) and DAC mode (used by TI platforms) on TI EVMs.
>>
>> Patches to move move bindings over to
>> "Documentation/devicetree/bindings/spi/" directory and also conversion
>> of bindig doc to YAML will be posted separately. Support for Intel
>> platform would follow that.
>>
>> Reference:
>> https://lkml.org/lkml/2020/6/1/50
>>
>> ---
>> v8:
>> - As Mark suggested to add the dt-bindings documentation patches
>> end of the series , so dropped.
>
>
>>
>> Ramuthevar Vadivel Murugan (6):
>> spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
>> spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
>> spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
>> spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
>> dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml
>> dt-bindings: spi: Add compatible for Intel LGM SoC
>>
>
> This is quite confusing... Summary/diffstat still shows patches 4 to 6
> and so does the patch numbering in $subject while changelog says
> otherwise and I received only 3 patches in my Inbox?
oh my bad, while patch creation wrongly added, will correct it, thanks!
Regards
Vadivel
>
>
>> .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 ----------
>> .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 148 +++++++++++++++++++++
>> drivers/spi/Kconfig | 2 +-
>> drivers/spi/spi-cadence-quadspi.c | 33 ++++-
>> 4 files changed, 178 insertions(+), 72 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
>> create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>>
>
> So does the diffstat...
>
^ permalink raw reply [flat|nested] 10+ messages in thread