From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Ben Widawsky <ben.widawsky@intel.com>,
<linux-cxl@vger.kernel.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
Linux PCI <linux-pci@vger.kernel.org>,
Linux ACPI <linux-acpi@vger.kernel.org>,
"Ira Weiny" <ira.weiny@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
"Kelley, Sean V" <sean.v.kelley@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>
Subject: Re: [RFC PATCH 8/9] cxl/mem: Register CXL memX devices
Date: Fri, 20 Nov 2020 15:20:18 +0000 [thread overview]
Message-ID: <20201120152018.00006121@Huawei.com> (raw)
In-Reply-To: <CAPcyv4ifDfzN=NTNZTh+xU_-b5Rm4jNOLiakQv-DPQa+6hfRaQ@mail.gmail.com>
On Thu, 19 Nov 2020 18:16:19 -0800
Dan Williams <dan.j.williams@intel.com> wrote:
> On Tue, Nov 17, 2020 at 7:57 AM Jonathan Cameron
> <Jonathan.Cameron@huawei.com> wrote:
> >
> > On Tue, 10 Nov 2020 21:43:55 -0800
> > Ben Widawsky <ben.widawsky@intel.com> wrote:
> >
> > > From: Dan Williams <dan.j.williams@intel.com>
> > >
> > > Create the /sys/bus/cxl hierarchy to enumerate memory devices
> > > (per-endpoint control devices), memory address space devices (platform
> > > address ranges with interleaving, performance, and persistence
> > > attributes), and memory regions (active provisioned memory from an
> > > address space device that is in use as System RAM or delegated to
> > > libnvdimm as Persistent Memory regions).
> > >
> > > For now, only the per-endpoint control devices are registered on the
> > > 'cxl' bus.
> >
> > Reviewing ABI without documentation is challenging even when it's simple
> > so please add that for v2.
> >
> > This patch feels somewhat unpolished, but I guess it is mainly here to
> > give an illustration of how stuff might fit together rather than
> > any expectation of detailed review.
>
> Yeah, this is definitely an early look in the spirit of "Release early
> / release often".
>
Definitely a good idea.
...
> >
> > > static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> > > {
> > > struct cxl_mem *cxlm = ERR_PTR(-ENXIO);
> > > struct device *dev = &pdev->dev;
> > > + struct cxl_memdev *cxlmd;
> > > int rc, regloc, i;
> > >
> > > rc = cxl_bus_prepared(pdev);
> > > @@ -319,20 +545,31 @@ static int cxl_mem_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> > > if (rc)
> > > return rc;
> > >
> > > - /* Check that hardware "looks" okay. */
> > > - rc = cxl_mem_mbox_get(cxlm);
> > > + rc = cxl_mem_identify(cxlm);
> > > if (rc)
> > > return rc;
> > > -
> > > - cxl_mem_mbox_put(cxlm);
> >
> > It was kind of nice to see the flow earlier, but I'm also thinking it made
> > a slightly harder to read patch. Hmm. Maybe just drop the version earlier
> > in favour of a todo comment that you then do here?
>
> Not sure I follow, but I think you're saying don't bother with an
> initial patch introducing just doing the raw cxl_mem_mbox_get() in
> this path, jump straight to cxl_mem_identify()?
Exactly.
>
> >
> > > dev_dbg(&pdev->dev, "CXL Memory Device Interface Up\n");
> > > +
> >
> > Nice to tidy that up by moving to earlier patch.
>
> Sure.
>
> >
> > > pci_set_drvdata(pdev, cxlm);
> > >
> > > + cxlmd = cxl_mem_add_memdev(cxlm);
> > > + if (IS_ERR(cxlmd))
> > > + return PTR_ERR(cxlmd);
> >
> > Given we don't actually use cxlmd perhaps a simple return value
> > of 0 or error would be better from cxl_mem_add_memdev()
> >
> > (I guess you may have follow up patches that do something with it
> > here, though it feels wrong to ever do so given it is now registered
> > and hence exposed to the system).
>
> It's not added if IS_ERR() is true, but it would be simpler to just
> have cxl_mem_add_memdev() return an int since ->probe() doesn't use
> it.
Agreed.
>
> >
> > > +
> > > return 0;
> > > }
> > >
...
next prev parent reply other threads:[~2020-11-20 15:20 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-11 5:43 [RFC PATCH 0/9] CXL 2.0 Support Ben Widawsky
2020-11-11 5:43 ` [RFC PATCH 1/9] cxl/acpi: Add an acpi_cxl module for the CXL interconnect Ben Widawsky
2020-11-11 6:17 ` Randy Dunlap
2020-11-11 7:10 ` Christoph Hellwig
2020-11-11 7:30 ` Verma, Vishal L
2020-11-11 7:34 ` hch
2020-11-11 7:36 ` Verma, Vishal L
2020-11-11 23:03 ` Bjorn Helgaas
2020-11-16 17:59 ` Jonathan Cameron
2020-11-16 18:23 ` Verma, Vishal L
2020-11-17 14:32 ` Rafael J. Wysocki
2020-11-17 21:45 ` Dan Williams
2020-11-18 11:14 ` Rafael J. Wysocki
2020-11-11 5:43 ` [RFC PATCH 2/9] cxl/acpi: add OSC support Ben Widawsky
2020-11-16 17:59 ` Jonathan Cameron
2020-11-16 23:25 ` Dan Williams
2020-11-18 12:25 ` Rafael J. Wysocki
2020-11-18 17:58 ` Dan Williams
2020-11-11 5:43 ` [RFC PATCH 3/9] cxl/mem: Add a driver for the type-3 mailbox Ben Widawsky
2020-11-11 6:17 ` Randy Dunlap
2020-11-11 7:12 ` Christoph Hellwig
2020-11-11 17:17 ` Dan Williams
2020-11-11 18:27 ` Dan Williams
2020-11-11 21:41 ` Randy Dunlap
2020-11-11 22:40 ` Dan Williams
2020-11-16 16:56 ` Christoph Hellwig
2020-11-13 18:17 ` Bjorn Helgaas
2020-11-14 1:08 ` Ben Widawsky
2020-11-15 0:23 ` Dan Williams
2020-11-17 14:49 ` Jonathan Cameron
2020-12-04 7:22 ` Dan Williams
2020-12-04 7:27 ` Dan Williams
2020-12-04 17:39 ` Jonathan Cameron
2020-11-11 5:43 ` [RFC PATCH 4/9] cxl/mem: Map memory device registers Ben Widawsky
2020-11-13 18:17 ` Bjorn Helgaas
2020-11-14 1:12 ` Ben Widawsky
2020-11-16 23:19 ` Dan Williams
2020-11-17 0:23 ` Bjorn Helgaas
2020-11-23 19:20 ` Ben Widawsky
2020-11-23 19:32 ` Dan Williams
2020-11-23 19:58 ` Ben Widawsky
2020-11-17 15:00 ` Jonathan Cameron
2020-11-11 5:43 ` [RFC PATCH 5/9] cxl/mem: Find device capabilities Ben Widawsky
2020-11-13 18:26 ` Bjorn Helgaas
2020-11-14 1:36 ` Ben Widawsky
2020-11-17 15:15 ` Jonathan Cameron
2020-11-24 0:17 ` Ben Widawsky
2020-11-26 6:05 ` Jon Masters
2020-11-26 18:18 ` Ben Widawsky
2020-12-04 7:35 ` Dan Williams
2020-12-04 7:41 ` Dan Williams
2020-12-07 6:12 ` Ben Widawsky
2020-11-11 5:43 ` [RFC PATCH 6/9] cxl/mem: Initialize the mailbox interface Ben Widawsky
2020-11-17 15:22 ` Jonathan Cameron
2020-11-11 5:43 ` [RFC PATCH 7/9] cxl/mem: Implement polled mode mailbox Ben Widawsky
2020-11-13 23:14 ` Bjorn Helgaas
2020-11-17 15:31 ` Jonathan Cameron
2020-11-17 16:34 ` Ben Widawsky
2020-11-17 18:06 ` Jonathan Cameron
2020-11-17 18:38 ` Dan Williams
2020-11-11 5:43 ` [RFC PATCH 8/9] cxl/mem: Register CXL memX devices Ben Widawsky
2020-11-17 15:56 ` Jonathan Cameron
2020-11-20 2:16 ` Dan Williams
2020-11-20 15:20 ` Jonathan Cameron [this message]
2020-11-11 5:43 ` [RFC PATCH 9/9] MAINTAINERS: Add maintainers of the CXL driver Ben Widawsky
2020-11-11 22:06 ` [RFC PATCH 0/9] CXL 2.0 Support Ben Widawsky
2020-11-11 22:43 ` Bjorn Helgaas
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