From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Steen Hegelund <steen.hegelund@microchip.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Device Tree List <devicetree@vger.kernel.org>,
Lars Povlsen <lars.povlsen@microchip.com>,
Bjarni Jonasson <bjarni.jonasson@microchip.com>,
Microsemi List <microsemi@lists.bootlin.com>,
Microchip UNG Driver List <UNGLinuxDriver@microchip.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 1/4] dt-bindings: phy: Add sparx5-serdes bindings
Date: Fri, 20 Nov 2020 17:09:01 +0100 [thread overview]
Message-ID: <20201120160901.GA348979@piout.net> (raw)
In-Reply-To: <20201120150359.2041940-2-steen.hegelund@microchip.com>
Hi,
On 20/11/2020 16:03:56+0100, Steen Hegelund wrote:
> Document the Sparx5 ethernet serdes phy driver bindings.
>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
> ---
> .../bindings/phy/microchip,sparx5-serdes.yaml | 296 ++++++++++++++++++
> 1 file changed, 296 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
> new file mode 100644
> index 000000000000..0bfb752e7686
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
> @@ -0,0 +1,296 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip Sparx5 Serdes controller
> +
> +maintainers:
> + - Steen Hegelund <steen.hegelund@microchip.com>
> +
> +description: |
> + The Sparx5 SERDES interfaces share the same basic functionality, but
> + support different operating modes and line rates.
> +
> + The following list lists the SERDES features:
> +
> + * RX Adaptive Decision Feedback Equalizer (DFE)
> + * Programmable continuous time linear equalizer (CTLE)
> + * Rx variable gain control
> + * Rx built-in fault detector (loss-of-lock/loss-of-signal)
> + * Adjustable tx de-emphasis (FFE)
> + * Tx output amplitude control
> + * Supports rx eye monitor
> + * Multiple loopback modes
> + * Prbs generator and checker
> + * Polarity inversion control
> +
> + SERDES6G:
> +
> + The SERDES6G is a high-speed SERDES interface, which can operate at
> + the following data rates:
> +
> + * 100 Mbps (100BASE-FX)
> + * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
> + * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
> + * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
> +
> + SERDES10G
> +
> + The SERDES10G is a high-speed SERDES interface, which can operate at
> + the following data rates:
> +
> + * 100 Mbps (100BASE-FX)
> + * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
> + * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
> + * 5 Gbps (QSGMII/USGMII)
> + * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
> + * 10 Gbps (10G-USGMII)
> + * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
> +
> + SERDES25G
> +
> + The SERDES25G is a high-speed SERDES interface, which can operate at
> + the following data rates:
> +
> + * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
> + * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
> + * 5 Gbps (QSGMII/USGMII)
> + * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
> + * 10 Gbps (10G-USGMII)
> + * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
> + * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
> +
> +properties:
> + $nodename:
> + pattern: "^serdes@[0-9a-f]+$"
> +
> + compatible:
> + const: microchip,sparx5-serdes.yaml
This has a spurious .yaml suffix ;)
> +
> + reg:
> + description: Address and length of the register set for the device
You don't actually have to describe this property a sit comes from the
generic schema. But maybe you could set maxItems
> +
> + reg-names:
> + description: |
> + Names for each of the address spaces defined in
> + the 'reg' property. Expects the names in the same order as the
> + corresponding memory region in the that property.
> +
Same comment, even better, I tink you could list the expected names in
an enum or a const list
> + '#phy-cells':
> + const: 1
> + description: |
> + - The main serdes input port
> +
> + clocks:
> + description:
> + A list containing the phandle to the core clock of the Sparx5 device.
You can drop the description and simply have maxItems: 1
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
next prev parent reply other threads:[~2020-11-20 16:09 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-20 15:03 [PATCH v4 0/4] Adding the Sparx5 Serdes driver Steen Hegelund
2020-11-20 15:03 ` [PATCH v4 1/4] dt-bindings: phy: Add sparx5-serdes bindings Steen Hegelund
2020-11-20 16:09 ` Alexandre Belloni [this message]
2020-11-23 8:11 ` Steen Hegelund
2020-11-20 15:03 ` [PATCH v4 2/4] phy: Add ethernet serdes configuration option Steen Hegelund
2020-11-20 18:39 ` kernel test robot
2020-11-20 15:03 ` [PATCH v4 3/4] phy: Add Sparx5 ethernet serdes PHY driver Steen Hegelund
2020-11-20 15:03 ` [PATCH v4 4/4] arm64: dts: sparx5: Add Sparx5 serdes driver node Steen Hegelund
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