From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Lars Povlsen <lars.povlsen@microchip.com>,
<Steen.Hegelund@microchip.com>,
Gregory CLEMENT <gregory.clement@bootlin.com>
Subject: [PATCH v4 1/6] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema
Date: Fri, 20 Nov 2020 17:41:03 +0100 [thread overview]
Message-ID: <20201120164108.2096359-2-gregory.clement@bootlin.com> (raw)
In-Reply-To: <20201120164108.2096359-1-gregory.clement@bootlin.com>
Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
Controller to YAML format
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
.../mscc,ocelot-icpu-intr.txt | 21 -------
.../mscc,ocelot-icpu-intr.yaml | 60 +++++++++++++++++++
2 files changed, 60 insertions(+), 21 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
deleted file mode 100644
index f5baeccb689f..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Microsemi Ocelot SoC ICPU Interrupt Controller
-
-Required properties:
-
-- compatible : should be "mscc,ocelot-icpu-intr"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value shall be 1.
-- interrupts : Specifies the CPU interrupt the controller is connected to.
-
-Example:
-
- intc: interrupt-controller@70000070 {
- compatible = "mscc,ocelot-icpu-intr";
- reg = <0x70000070 0x70>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupt-parent = <&cpuintc>;
- interrupts = <2>;
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
new file mode 100644
index 000000000000..f34b319c7874
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microsemi Ocelot SoC ICPU Interrupt Controller
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ the Microsemi Ocelot interrupt controller that is part of the
+ ICPU. It is connected directly to the MIPS core interrupt
+ controller.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mscc,ocelot-icpu-intr
+
+ '#interrupt-cells':
+ const: 1
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+...
--
2.29.2
next prev parent reply other threads:[~2020-11-20 16:41 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-20 16:41 [PATCH v4 0/6] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT
2020-11-20 16:41 ` Gregory CLEMENT [this message]
2020-11-20 21:03 ` [PATCH v4 1/6] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema Rob Herring
2020-11-20 16:41 ` [PATCH v4 2/6] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers Gregory CLEMENT
2020-11-20 16:41 ` [PATCH v4 3/6] irqchip: ocelot: prepare to support more SoC Gregory CLEMENT
2020-11-23 8:04 ` Alexandre Belloni
2020-11-20 16:41 ` [PATCH v4 4/6] irqchip: ocelot: Add support for Luton platforms Gregory CLEMENT
2020-11-23 8:04 ` Alexandre Belloni
2020-11-20 16:41 ` [PATCH v4 5/6] irqchip: ocelot: Add support for Serval platforms Gregory CLEMENT
2020-11-20 16:41 ` [PATCH v4 6/6] irqchip: ocelot: Add support for Jaguar2 platforms Gregory CLEMENT
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