* [PATCH 0/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock
@ 2020-11-23 16:38 Neil Armstrong
2020-11-23 16:38 ` [PATCH 1/2] dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings Neil Armstrong
2020-11-23 16:38 ` [PATCH 2/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock Neil Armstrong
0 siblings, 2 replies; 5+ messages in thread
From: Neil Armstrong @ 2020-11-23 16:38 UTC (permalink / raw)
To: jbrunet
Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel, Neil Armstrong
This serie adss the MIPI DSI Host Pixel Clock used to feed the DSI pixel
clock to the DSI Host controller.
Unlike the AXG SoC, the DSI Pixel Clock has a supplementary mux, divider and gate
stage before feeding the pixel clock to the MIPI DSI Host controller.
Neil Armstrong (2):
dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings
clk: meson: g12a: add MIPI DSI Host Pixel Clock
drivers/clk/meson/g12a.c | 72 +++++++++++++++++++++++++++
drivers/clk/meson/g12a.h | 3 +-
include/dt-bindings/clock/g12a-clkc.h | 2 +
3 files changed, 76 insertions(+), 1 deletion(-)
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings
2020-11-23 16:38 [PATCH 0/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock Neil Armstrong
@ 2020-11-23 16:38 ` Neil Armstrong
2020-11-23 16:38 ` [PATCH 2/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock Neil Armstrong
1 sibling, 0 replies; 5+ messages in thread
From: Neil Armstrong @ 2020-11-23 16:38 UTC (permalink / raw)
To: jbrunet
Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel,
Neil Armstrong, devicetree
This adds the MIPI DSI Host Pixel Clock bindings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
include/dt-bindings/clock/g12a-clkc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 40d49940d8a8..a93b58c5e18e 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -147,5 +147,7 @@
#define CLKID_SPICC1_SCLK 261
#define CLKID_NNA_AXI_CLK 264
#define CLKID_NNA_CORE_CLK 267
+#define CLKID_MIPI_DSI_PXCLK_SEL 269
+#define CLKID_MIPI_DSI_PXCLK 270
#endif /* __G12A_CLKC_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock
2020-11-23 16:38 [PATCH 0/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock Neil Armstrong
2020-11-23 16:38 ` [PATCH 1/2] dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings Neil Armstrong
@ 2020-11-23 16:38 ` Neil Armstrong
2020-11-25 17:32 ` Jerome Brunet
1 sibling, 1 reply; 5+ messages in thread
From: Neil Armstrong @ 2020-11-23 16:38 UTC (permalink / raw)
To: jbrunet
Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel, Neil Armstrong
This adds the MIPI DSI Host Pixel Clock, unlike AXG, the pixel clock can be different
from the VPU ENCL output clock to feed the DSI Host controller with a different clock rate.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/g12a.c | 72 ++++++++++++++++++++++++++++++++++++++++
drivers/clk/meson/g12a.h | 3 +-
2 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 3cb8196c8e29..3dedf8408405 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -3658,6 +3658,66 @@ static struct clk_regmap g12a_hdmi_tx = {
},
};
+/* MIPI DSI Host Clocks */
+
+static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] = {
+ &g12a_vid_pll.hw,
+ &g12a_gp0_pll.hw,
+ &g12a_hifi_pll.hw,
+ &g12a_mpll1.hw,
+ &g12a_fclk_div2.hw,
+ &g12a_fclk_div2p5.hw,
+ &g12a_fclk_div3.hw,
+ &g12a_fclk_div7.hw,
+};
+
+static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 12,
+ .flags = CLK_MUX_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mipi_dsi_pxclk_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
+ .num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mipi_dsi_pxclk_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &g12a_mipi_dsi_pxclk_sel.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap g12a_mipi_dsi_pxclk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "mipi_dsi_pxclk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &g12a_mipi_dsi_pxclk_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* HDMI Clocks */
static const struct clk_parent_data g12a_hdmi_parent_data[] = {
@@ -4403,6 +4463,9 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -4658,6 +4721,9 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -4904,6 +4970,9 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
[CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
[CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
[CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
+ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -5151,6 +5220,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
&sm1_nna_core_clk_sel,
&sm1_nna_core_clk_div,
&sm1_nna_core_clk,
+ &g12a_mipi_dsi_pxclk_sel,
+ &g12a_mipi_dsi_pxclk_div,
+ &g12a_mipi_dsi_pxclk,
};
static const struct reg_sequence g12a_init_regs[] = {
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 69b6a69549c7..a97613df38b3 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -264,8 +264,9 @@
#define CLKID_NNA_AXI_CLK_DIV 263
#define CLKID_NNA_CORE_CLK_SEL 265
#define CLKID_NNA_CORE_CLK_DIV 266
+#define CLKID_MIPI_DSI_PXCLK_DIV 268
-#define NR_CLKS 268
+#define NR_CLKS 271
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/g12a-clkc.h>
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock
2020-11-23 16:38 ` [PATCH 2/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock Neil Armstrong
@ 2020-11-25 17:32 ` Jerome Brunet
2020-11-26 14:08 ` Neil Armstrong
0 siblings, 1 reply; 5+ messages in thread
From: Jerome Brunet @ 2020-11-25 17:32 UTC (permalink / raw)
To: Neil Armstrong; +Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel
On Mon 23 Nov 2020 at 17:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
> This adds the MIPI DSI Host Pixel Clock, unlike AXG, the pixel clock can be different
> from the VPU ENCL output clock to feed the DSI Host controller with a different clock rate.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Series looks good.
2 minor comments below
> ---
> drivers/clk/meson/g12a.c | 72 ++++++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/g12a.h | 3 +-
> 2 files changed, 74 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
> index 3cb8196c8e29..3dedf8408405 100644
> --- a/drivers/clk/meson/g12a.c
> +++ b/drivers/clk/meson/g12a.c
> @@ -3658,6 +3658,66 @@ static struct clk_regmap g12a_hdmi_tx = {
> },
> };
>
> +/* MIPI DSI Host Clocks */
> +
> +static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] = {
> + &g12a_vid_pll.hw,
> + &g12a_gp0_pll.hw,
> + &g12a_hifi_pll.hw,
> + &g12a_mpll1.hw,
> + &g12a_fclk_div2.hw,
> + &g12a_fclk_div2p5.hw,
> + &g12a_fclk_div3.hw,
> + &g12a_fclk_div7.hw,
> +};
> +
> +static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
> + .mask = 0x7,
> + .shift = 12,
> + .flags = CLK_MUX_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mipi_dsi_pxclk_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
> + .num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
> + .flags = CLK_SET_RATE_PARENT,
The id of the mux is exposed which seems to hint the mux will be
manually controller but CLK_SET_RATE_NO_REPARENT is not set. Is this on
purpose ?
> + },
> +};
> +
> +static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
> + .shift = 0,
> + .width = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mipi_dsi_pxclk_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &g12a_mipi_dsi_pxclk_sel.hw },
Alignment here is weird compared to the reset of the file
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap g12a_mipi_dsi_pxclk = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "mipi_dsi_pxclk",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &g12a_mipi_dsi_pxclk_div.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> /* HDMI Clocks */
>
> static const struct clk_parent_data g12a_hdmi_parent_data[] = {
> @@ -4403,6 +4463,9 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
> [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
> [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
> [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
> + [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
> + [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
> + [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
> [NR_CLKS] = NULL,
> },
> .num = NR_CLKS,
> @@ -4658,6 +4721,9 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
> [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
> [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
> [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
> + [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
> + [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
> + [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
> [NR_CLKS] = NULL,
> },
> .num = NR_CLKS,
> @@ -4904,6 +4970,9 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
> [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
> [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
> [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
> + [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
> + [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
> + [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
> [NR_CLKS] = NULL,
> },
> .num = NR_CLKS,
> @@ -5151,6 +5220,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
> &sm1_nna_core_clk_sel,
> &sm1_nna_core_clk_div,
> &sm1_nna_core_clk,
> + &g12a_mipi_dsi_pxclk_sel,
> + &g12a_mipi_dsi_pxclk_div,
> + &g12a_mipi_dsi_pxclk,
> };
>
> static const struct reg_sequence g12a_init_regs[] = {
> diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
> index 69b6a69549c7..a97613df38b3 100644
> --- a/drivers/clk/meson/g12a.h
> +++ b/drivers/clk/meson/g12a.h
> @@ -264,8 +264,9 @@
> #define CLKID_NNA_AXI_CLK_DIV 263
> #define CLKID_NNA_CORE_CLK_SEL 265
> #define CLKID_NNA_CORE_CLK_DIV 266
> +#define CLKID_MIPI_DSI_PXCLK_DIV 268
>
> -#define NR_CLKS 268
> +#define NR_CLKS 271
>
> /* include the CLKIDs that have been made part of the DT binding */
> #include <dt-bindings/clock/g12a-clkc.h>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock
2020-11-25 17:32 ` Jerome Brunet
@ 2020-11-26 14:08 ` Neil Armstrong
0 siblings, 0 replies; 5+ messages in thread
From: Neil Armstrong @ 2020-11-26 14:08 UTC (permalink / raw)
To: Jerome Brunet; +Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel
On 25/11/2020 18:32, Jerome Brunet wrote:
>
> On Mon 23 Nov 2020 at 17:38, Neil Armstrong <narmstrong@baylibre.com> wrote:
>
>> This adds the MIPI DSI Host Pixel Clock, unlike AXG, the pixel clock can be different
>> from the VPU ENCL output clock to feed the DSI Host controller with a different clock rate.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>
> Series looks good.
> 2 minor comments below
>
>> ---
>> drivers/clk/meson/g12a.c | 72 ++++++++++++++++++++++++++++++++++++++++
>> drivers/clk/meson/g12a.h | 3 +-
>> 2 files changed, 74 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
>> index 3cb8196c8e29..3dedf8408405 100644
>> --- a/drivers/clk/meson/g12a.c
>> +++ b/drivers/clk/meson/g12a.c
>> @@ -3658,6 +3658,66 @@ static struct clk_regmap g12a_hdmi_tx = {
>> },
>> };
>>
>> +/* MIPI DSI Host Clocks */
>> +
>> +static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] = {
>> + &g12a_vid_pll.hw,
>> + &g12a_gp0_pll.hw,
>> + &g12a_hifi_pll.hw,
>> + &g12a_mpll1.hw,
>> + &g12a_fclk_div2.hw,
>> + &g12a_fclk_div2p5.hw,
>> + &g12a_fclk_div3.hw,
>> + &g12a_fclk_div7.hw,
>> +};
>> +
>> +static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
>> + .mask = 0x7,
>> + .shift = 12,
>> + .flags = CLK_MUX_ROUND_CLOSEST,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mipi_dsi_pxclk_sel",
>> + .ops = &clk_regmap_mux_ops,
>> + .parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
>> + .num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
>> + .flags = CLK_SET_RATE_PARENT,
>
> The id of the mux is exposed which seems to hint the mux will be
> manually controller but CLK_SET_RATE_NO_REPARENT is not set. Is this on
> purpose ?
You're right, it should be CLK_SET_RATE_NO_REPARENT here since we need to
control the source of the clock.
>
>> + },
>> +};
>> +
>> +static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
>> + .shift = 0,
>> + .width = 7,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mipi_dsi_pxclk_div",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &g12a_mipi_dsi_pxclk_sel.hw },
>
> Alignment here is weird compared to the reset of the file
ok
>
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap g12a_mipi_dsi_pxclk = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
>> + .bit_idx = 8,
>> + },
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "mipi_dsi_pxclk",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &g12a_mipi_dsi_pxclk_div.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> /* HDMI Clocks */
>>
>> static const struct clk_parent_data g12a_hdmi_parent_data[] = {
>> @@ -4403,6 +4463,9 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
>> [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
>> [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
>> [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
>> + [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
>> + [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
>> + [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
>> [NR_CLKS] = NULL,
>> },
>> .num = NR_CLKS,
>> @@ -4658,6 +4721,9 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
>> [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
>> [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
>> [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
>> + [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
>> + [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
>> + [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
>> [NR_CLKS] = NULL,
>> },
>> .num = NR_CLKS,
>> @@ -4904,6 +4970,9 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
>> [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
>> [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
>> [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
>> + [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
>> + [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
>> + [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
>> [NR_CLKS] = NULL,
>> },
>> .num = NR_CLKS,
>> @@ -5151,6 +5220,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
>> &sm1_nna_core_clk_sel,
>> &sm1_nna_core_clk_div,
>> &sm1_nna_core_clk,
>> + &g12a_mipi_dsi_pxclk_sel,
>> + &g12a_mipi_dsi_pxclk_div,
>> + &g12a_mipi_dsi_pxclk,
>> };
>>
>> static const struct reg_sequence g12a_init_regs[] = {
>> diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
>> index 69b6a69549c7..a97613df38b3 100644
>> --- a/drivers/clk/meson/g12a.h
>> +++ b/drivers/clk/meson/g12a.h
>> @@ -264,8 +264,9 @@
>> #define CLKID_NNA_AXI_CLK_DIV 263
>> #define CLKID_NNA_CORE_CLK_SEL 265
>> #define CLKID_NNA_CORE_CLK_DIV 266
>> +#define CLKID_MIPI_DSI_PXCLK_DIV 268
>>
>> -#define NR_CLKS 268
>> +#define NR_CLKS 271
>>
>> /* include the CLKIDs that have been made part of the DT binding */
>> #include <dt-bindings/clock/g12a-clkc.h>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-11-26 14:09 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-23 16:38 [PATCH 0/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock Neil Armstrong
2020-11-23 16:38 ` [PATCH 1/2] dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings Neil Armstrong
2020-11-23 16:38 ` [PATCH 2/2] clk: meson: g12a: add MIPI DSI Host Pixel Clock Neil Armstrong
2020-11-25 17:32 ` Jerome Brunet
2020-11-26 14:08 ` Neil Armstrong
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