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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	robh+dt@kernel.org
Cc: bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org,
	linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, sivaprak@codeaurora.org,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH 0/2] Add NAND support for SDX55
Date: Thu, 26 Nov 2020 14:27:03 +0530	[thread overview]
Message-ID: <20201126085705.48399-1-manivannan.sadhasivam@linaro.org> (raw)

Hello,

This series adds NAND controller support for SDX55 platform. SDX55 uses
QPIC IP v2 which slightly differs from the former ones. The difference
in the driver is handled by using 'qpic_v2' flag.

The major difference in QPIC IP v2 is the DEV_CMD* registers which got
moved to operational state, and access to them seems restricted. So in the
driver, access to DEV_CMD* registers is excluded. For reading the ONFI
parameters, a separate field 'OP_PAGE_READ_ONFI_READ' in 'NAND_FLASH_CMD'
register is used.

This series has been tested on SDX55 MTP along with the SMEM partition
parser [1].

Thanks,
Mani

[1] https://lore.kernel.org/patchwork/cover/1340600/

Manivannan Sadhasivam (2):
  dt-bindings: qcom_nandc: Add SDX55 QPIC NAND documentation
  mtd: rawnand: qcom: Add NAND controller support for SDX55

 .../devicetree/bindings/mtd/qcom_nandc.txt    |  2 +
 drivers/mtd/nand/raw/qcom_nandc.c             | 68 ++++++++++++++-----
 2 files changed, 53 insertions(+), 17 deletions(-)

-- 
2.25.1


             reply	other threads:[~2020-11-26  8:57 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-26  8:57 Manivannan Sadhasivam [this message]
2020-11-26  8:57 ` [PATCH 1/2] dt-bindings: qcom_nandc: Add SDX55 QPIC NAND documentation Manivannan Sadhasivam
2020-12-08 16:08   ` Rob Herring
2020-11-26  8:57 ` [PATCH 2/2] mtd: rawnand: qcom: Add NAND controller support for SDX55 Manivannan Sadhasivam

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