linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org,
	linux-kernel@vger.kernel.org, anshuman.khandual@arm.com,
	jonathan.zhouwen@huawei.com, coresight@lists.linaro.org,
	Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
	Tingwei Zhang <tingwei@codeaurora.org>
Subject: Re: [PATCH v4 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore
Date: Fri, 27 Nov 2020 11:55:22 -0700	[thread overview]
Message-ID: <20201127185522.GB1092947@xps15> (raw)
In-Reply-To: <20201119164547.2982871-3-suzuki.poulose@arm.com>

On Thu, Nov 19, 2020 at 04:45:24PM +0000, Suzuki K Poulose wrote:
> When the ETM is affected by Qualcomm errata, modifying the
> TRCPDCR could cause the system hang. Even though this is
> taken care of during enable/disable ETM, the ETM state
> save/restore could still access the TRCPDCR. Make sure
> we skip the access during the save/restore.
> 
> Found by code inspection.
> 
> Fixes: commit 02510a5aa78df45 ("coresight: etm4x: Add support to skip trace unit power up")

https://elixir.bootlin.com/linux/v5.10-rc5/source/Documentation/process/submitting-patches.rst#L121

> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Cc: Tingwei Zhang <tingwei@codeaurora.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 59a4a166adf4..ea2e317ddb7d 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1277,7 +1277,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
>  
>  	state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR);
>  
> -	state->trcpdcr = readl(drvdata->base + TRCPDCR);
> +	if (!drvdata->skip_power_up)
> +		state->trcpdcr = readl(drvdata->base + TRCPDCR);
>  
>  	/* wait for TRCSTATR.IDLE to go up */
>  	if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
> @@ -1295,9 +1296,9 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
>  	 * potentially save power on systems that respect the TRCPDCR_PU
>  	 * despite requesting software to save/restore state.
>  	 */
> -	writel_relaxed((state->trcpdcr & ~TRCPDCR_PU),
> -			drvdata->base + TRCPDCR);
> -
> +	if (!drvdata->skip_power_up)
> +		writel_relaxed((state->trcpdcr & ~TRCPDCR_PU),
> +				drvdata->base + TRCPDCR);
>  out:
>  	CS_LOCK(drvdata->base);
>  	return ret;
> @@ -1392,7 +1393,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>  
>  	writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
>  
> -	writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR);
> +	if (!drvdata->skip_power_up)
> +		writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR);
>  
>  	drvdata->state_needs_restore = false;
>  
> -- 
> 2.24.1
> 

  parent reply	other threads:[~2020-11-27 18:58 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-19 16:45 [PATCH v4 00/26] coresight: etm4x: Support for system instructions Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 01/25] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2020-11-20  5:40   ` Sai Prakash Ranjan
2020-11-27 18:55   ` Mathieu Poirier [this message]
2020-11-30  9:37     ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 03/25] coresight: Introduce device access abstraction Suzuki K Poulose
2020-11-27 19:11   ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 04/25] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 05/25] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-11-30 20:55   ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 06/25] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-11-30 21:04   ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 07/25] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 08/25] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 09/25] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 10/25] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 11/25] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-11-30 21:19   ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 12/25] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 13/25] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-11-30 21:25   ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 14/25] coresight: etm4x: Clean up " Suzuki K Poulose
2020-11-30 21:45   ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 15/25] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-11-30 21:48   ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 16/25] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-11-30 21:53   ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 17/25] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-11-27 18:28   ` Mathieu Poirier
2020-11-30  9:30     ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 18/25] coresight: etm4x: Expose trcdevarch via trcidr Suzuki K Poulose
2020-11-30 22:42   ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 19/25] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 20/25] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-11-23  7:58   ` Tingwei Zhang
2020-11-23  9:39     ` Suzuki K Poulose
2020-11-24  0:41       ` Tingwei Zhang
2020-11-24 11:38         ` Suzuki K Poulose
2020-11-25  4:57           ` Tingwei Zhang
2020-11-19 16:45 ` [PATCH v4 21/25] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 22/25] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 23/25] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 24/25] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2020-11-19 17:18   ` Catalin Marinas
2020-11-20 10:03     ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 25/25] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2020-11-19 17:22   ` Catalin Marinas
2020-11-20 10:03     ` Suzuki K Poulose

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201127185522.GB1092947@xps15 \
    --to=mathieu.poirier@linaro.org \
    --cc=anshuman.khandual@arm.com \
    --cc=coresight@lists.linaro.org \
    --cc=jonathan.zhouwen@huawei.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mike.leach@linaro.org \
    --cc=saiprakash.ranjan@codeaurora.org \
    --cc=suzuki.poulose@arm.com \
    --cc=tingwei@codeaurora.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).