* [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver
@ 2020-11-08 18:51 Michael Walle
2020-11-08 18:51 ` [PATCH v3 1/9] arm64: dts: ls1028a: fix ENETC PTP clock input Michael Walle
` (8 more replies)
0 siblings, 9 replies; 21+ messages in thread
From: Michael Walle @ 2020-11-08 18:51 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean,
Michael Walle
The first two patches fix clock references for the ENETC and the
FlexSPI on the LS1028A. These are intended to be picked up by the
stable branches.
To circumvent further mistakes, I new device tree constants for
the qoriq binding. This should make it far easier for humans to
read the clockgen nodes.
The 4th patch convert the LS1028A device tree include to use the
new constants.
The last five patches add a clock driver for the FlexSPI
controller on layerscape SoCs. There is a single register which
can control the divider value. Right now the LS1028A and the LX2160A
aren't able to switch the SCK frequency on the FlexSPI interface.
I've included the first four patches in this series, otherwise
there would be merge conflicts, because they depend on the new
qoriq device tree constants.
Michael Walle (9):
arm64: dts: ls1028a: fix ENETC PTP clock input
arm64: dts: ls1028a: fix FlexSPI clock input
clk: qoriq: provide constants for the type
arm64: dts: ls1028a: use constants in the clockgen phandle
clk: divider: add devm_clk_hw_register_divider_table()
dt-bindings: clock: document the fsl-flexspi-clk driver
clk: fsl-flexspi: new driver
arm64: dts: ls1028a: fix FlexSPI clock
arm64: dts: lx2160a: fix FlexSPI clock
.../bindings/clock/fsl,flexspi-clock.yaml | 55 ++++++
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 174 +++++++++++++-----
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 15 +-
drivers/clk/Kconfig | 8 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-divider.c | 34 ++++
drivers/clk/clk-fsl-flexspi.c | 106 +++++++++++
drivers/clk/clk-qoriq.c | 13 +-
.../dt-bindings/clock/fsl,qoriq-clockgen.h | 15 ++
include/linux/clk-provider.h | 27 +++
10 files changed, 393 insertions(+), 55 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml
create mode 100644 drivers/clk/clk-fsl-flexspi.c
create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 1/9] arm64: dts: ls1028a: fix ENETC PTP clock input
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
@ 2020-11-08 18:51 ` Michael Walle
2020-11-30 9:20 ` Shawn Guo
2020-11-08 18:51 ` [PATCH v3 2/9] arm64: dts: ls1028a: fix FlexSPI " Michael Walle
` (7 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Michael Walle @ 2020-11-08 18:51 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean,
Michael Walle
On the LS1028A the ENETC reference clock is connected to 4th HWA output,
see Figure 7 "Clock subsystem block diagram".
The PHC may run with a wrong frequency. ptp_qoriq_auto_config() will read
the clock speed of the clock given in the device tree. It is likely that,
on the reference board this wasn't noticed because both clocks have the
same frequency. But this must not be always the case. Fix it.
Fixes: 49401003e260 ("arm64: dts: fsl: ls1028a: add ENETC 1588 timer node")
Signed-off-by: Michael Walle <michael@walle.cc>
---
Changes since v2:
- new patch
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 2c831d814572..e22f29aa4658 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -961,7 +961,7 @@
ethernet@0,4 {
compatible = "fsl,enetc-ptp";
reg = <0x000400 0 0 0 0>;
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen 2 3>;
little-endian;
fsl,extts-fifo;
};
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 2/9] arm64: dts: ls1028a: fix FlexSPI clock input
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
2020-11-08 18:51 ` [PATCH v3 1/9] arm64: dts: ls1028a: fix ENETC PTP clock input Michael Walle
@ 2020-11-08 18:51 ` Michael Walle
2020-11-30 9:21 ` Shawn Guo
2020-11-08 18:51 ` [PATCH v3 3/9] clk: qoriq: provide constants for the type Michael Walle
` (6 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Michael Walle @ 2020-11-08 18:51 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean,
Michael Walle
On the LS1028A the FlexSPI clock is connected to the first HWA output,
see Figure 7 "Clock subsystem block diagram".
Fixes: c77fae5ba09a ("arm64: dts: ls1028a: Add FlexSPI support")
Signed-off-by: Michael Walle <michael@walle.cc>
---
Changes since v2:
- new patch
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index e22f29aa4658..2f60a6ba7e14 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -318,7 +318,7 @@
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 2 0>, <&clockgen 2 0>;
clock-names = "fspi_en", "fspi";
status = "disabled";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 3/9] clk: qoriq: provide constants for the type
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
2020-11-08 18:51 ` [PATCH v3 1/9] arm64: dts: ls1028a: fix ENETC PTP clock input Michael Walle
2020-11-08 18:51 ` [PATCH v3 2/9] arm64: dts: ls1028a: fix FlexSPI " Michael Walle
@ 2020-11-08 18:51 ` Michael Walle
2020-11-09 22:05 ` Rob Herring
2020-11-08 18:51 ` [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen phandle Michael Walle
` (5 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Michael Walle @ 2020-11-08 18:51 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean,
Michael Walle
To avoid future mistakes in the device tree for the clockgen module, add
constants for the clockgen subtype as well as a macro for the PLL
divider.
Signed-off-by: Michael Walle <michael@walle.cc>
---
Changes since v2:
- new patch
drivers/clk/clk-qoriq.c | 13 +++++++------
include/dt-bindings/clock/fsl,qoriq-clockgen.h | 15 +++++++++++++++
2 files changed, 22 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 46101c6a20f2..70aa521e7e7f 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -7,6 +7,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
@@ -1368,33 +1369,33 @@ static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
idx = clkspec->args[1];
switch (type) {
- case 0:
+ case QORIQ_CLK_SYSCLK:
if (idx != 0)
goto bad_args;
clk = cg->sysclk;
break;
- case 1:
+ case QORIQ_CLK_CMUX:
if (idx >= ARRAY_SIZE(cg->cmux))
goto bad_args;
clk = cg->cmux[idx];
break;
- case 2:
+ case QORIQ_CLK_HWACCEL:
if (idx >= ARRAY_SIZE(cg->hwaccel))
goto bad_args;
clk = cg->hwaccel[idx];
break;
- case 3:
+ case QORIQ_CLK_FMAN:
if (idx >= ARRAY_SIZE(cg->fman))
goto bad_args;
clk = cg->fman[idx];
break;
- case 4:
+ case QORIQ_CLK_PLATFORM_PLL:
pll = &cg->pll[PLATFORM_PLL];
if (idx >= ARRAY_SIZE(pll->div))
goto bad_args;
clk = pll->div[idx].clk;
break;
- case 5:
+ case QORIQ_CLK_CORECLK:
if (idx != 0)
goto bad_args;
clk = cg->coreclk;
diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
new file mode 100644
index 000000000000..ddec7d0bdc7f
--- /dev/null
+++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+
+#define QORIQ_CLK_SYSCLK 0
+#define QORIQ_CLK_CMUX 1
+#define QORIQ_CLK_HWACCEL 2
+#define QORIQ_CLK_FMAN 3
+#define QORIQ_CLK_PLATFORM_PLL 4
+#define QORIQ_CLK_CORECLK 5
+
+#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
+
+#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen phandle
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
` (2 preceding siblings ...)
2020-11-08 18:51 ` [PATCH v3 3/9] clk: qoriq: provide constants for the type Michael Walle
@ 2020-11-08 18:51 ` Michael Walle
2020-11-20 9:25 ` [EXT] " Ashish Kumar
2020-11-08 18:51 ` [PATCH v3 5/9] clk: divider: add devm_clk_hw_register_divider_table() Michael Walle
` (4 subsequent siblings)
8 siblings, 1 reply; 21+ messages in thread
From: Michael Walle @ 2020-11-08 18:51 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean,
Michael Walle
Now that we have constants, use them. This is just a mechanical change.
Signed-off-by: Michael Walle <michael@walle.cc>
---
Changes since v2:
- new patch
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 162 +++++++++++++-----
1 file changed, 116 insertions(+), 46 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 2f60a6ba7e14..055da2c710c3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -8,6 +8,7 @@
*
*/
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
@@ -32,7 +33,7 @@
compatible = "arm,cortex-a72";
reg = <0x0>;
enable-method = "psci";
- clocks = <&clockgen 1 0>;
+ clocks = <&clockgen QORIQ_CLK_CMUX 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>;
@@ -43,7 +44,7 @@
compatible = "arm,cortex-a72";
reg = <0x1>;
enable-method = "psci";
- clocks = <&clockgen 1 0>;
+ clocks = <&clockgen QORIQ_CLK_CMUX 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>;
@@ -236,7 +237,8 @@
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -246,7 +248,8 @@
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -256,7 +259,8 @@
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -266,7 +270,8 @@
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -276,7 +281,8 @@
#size-cells = <0>;
reg = <0x0 0x2040000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -286,7 +292,8 @@
#size-cells = <0>;
reg = <0x0 0x2050000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -296,7 +303,8 @@
#size-cells = <0>;
reg = <0x0 0x2060000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -306,7 +314,8 @@
#size-cells = <0>;
reg = <0x0 0x2070000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -318,7 +327,8 @@
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 2 0>, <&clockgen 2 0>;
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 0>,
+ <&clockgen QORIQ_CLK_HWACCEL 0>;
clock-names = "fspi_en", "fspi";
status = "disabled";
};
@@ -330,7 +340,8 @@
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
dmas = <&edma0 0 62>, <&edma0 0 60>;
dma-names = "tx", "rx";
spi-num-chipselects = <4>;
@@ -345,7 +356,8 @@
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
dmas = <&edma0 0 58>, <&edma0 0 56>;
dma-names = "tx", "rx";
spi-num-chipselects = <4>;
@@ -360,7 +372,8 @@
reg = <0x0 0x2120000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
dmas = <&edma0 0 54>, <&edma0 0 2>;
dma-names = "tx", "rx";
spi-num-chipselects = <3>;
@@ -373,7 +386,7 @@
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>; /* fixed up by bootloader */
- clocks = <&clockgen 2 1>;
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
@@ -386,7 +399,7 @@
reg = <0x0 0x2150000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>; /* fixed up by bootloader */
- clocks = <&clockgen 2 1>;
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
broken-cd;
@@ -399,7 +412,8 @@
compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan";
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sysclk>, <&clockgen 4 1>;
+ clocks = <&sysclk>, <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -408,7 +422,8 @@
compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan";
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sysclk>, <&clockgen 4 1>;
+ clocks = <&sysclk>, <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg", "per";
status = "disabled";
};
@@ -417,7 +432,8 @@
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
@@ -425,7 +441,8 @@
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
@@ -434,7 +451,8 @@
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2260000 0x0 0x1000>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 32>,
@@ -446,7 +464,8 @@
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2270000 0x0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 30>,
@@ -458,7 +477,8 @@
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2280000 0x0 0x1000>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 28>,
@@ -470,7 +490,8 @@
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2290000 0x0 0x1000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 26>,
@@ -482,7 +503,8 @@
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x22a0000 0x0 0x1000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 24>,
@@ -494,7 +516,8 @@
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x22b0000 0x0 0x1000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 22>,
@@ -513,8 +536,10 @@
interrupt-names = "edma-tx", "edma-err";
dma-channels = <32>;
clock-names = "dmamux0", "dmamux1";
- clocks = <&clockgen 4 1>,
- <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
};
gpio1: gpio@2300000 {
@@ -576,7 +601,8 @@
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
@@ -748,14 +774,20 @@
cluster1_core0_watchdog: watchdog@c000000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
- clocks = <&clockgen 4 15>, <&clockgen 4 15>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster1_core1_watchdog: watchdog@c010000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
- clocks = <&clockgen 4 15>, <&clockgen 4 15>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>;
clock-names = "wdog_clk", "apb_pclk";
};
@@ -764,8 +796,14 @@
compatible = "fsl,vf610-sai";
reg = <0x0 0xf100000 0x0 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>, <&clockgen 4 1>,
- <&clockgen 4 1>, <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 4>,
@@ -779,8 +817,14 @@
compatible = "fsl,vf610-sai";
reg = <0x0 0xf110000 0x0 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>, <&clockgen 4 1>,
- <&clockgen 4 1>, <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 6>,
@@ -794,8 +838,14 @@
compatible = "fsl,vf610-sai";
reg = <0x0 0xf120000 0x0 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>, <&clockgen 4 1>,
- <&clockgen 4 1>, <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 8>,
@@ -809,8 +859,14 @@
compatible = "fsl,vf610-sai";
reg = <0x0 0xf130000 0x0 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>, <&clockgen 4 1>,
- <&clockgen 4 1>, <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 10>,
@@ -824,8 +880,14 @@
compatible = "fsl,vf610-sai";
reg = <0x0 0xf140000 0x0 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>, <&clockgen 4 1>,
- <&clockgen 4 1>, <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 12>,
@@ -839,8 +901,14 @@
compatible = "fsl,vf610-sai";
reg = <0x0 0xf150000 0x0 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 1>, <&clockgen 4 1>,
- <&clockgen 4 1>, <&clockgen 4 1>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 1 14>,
@@ -961,7 +1029,7 @@
ethernet@0,4 {
compatible = "fsl,enetc-ptp";
reg = <0x000400 0 0 0 0>;
- clocks = <&clockgen 2 3>;
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
little-endian;
fsl,extts-fifo;
};
@@ -1056,8 +1124,10 @@
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
<0 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
- clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
- <&clockgen 2 2>;
+ clocks = <&dpclk>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-value = <0xd000d000>;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 5/9] clk: divider: add devm_clk_hw_register_divider_table()
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
` (3 preceding siblings ...)
2020-11-08 18:51 ` [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen phandle Michael Walle
@ 2020-11-08 18:51 ` Michael Walle
2020-11-08 18:51 ` [PATCH v3 6/9] dt-bindings: clock: document the fsl-flexspi-clk driver Michael Walle
` (3 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Michael Walle @ 2020-11-08 18:51 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean,
Michael Walle
This will simplify drivers which would only unregister the clk in their
remove() op.
Signed-off-by: Michael Walle <michael@walle.cc>
---
Changes since v2:
- none
Changes since v1:
- new patch
drivers/clk/clk-divider.c | 34 ++++++++++++++++++++++++++++++++++
include/linux/clk-provider.h | 27 +++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8de12cb0c43d..c499799693cc 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -8,6 +8,7 @@
*/
#include <linux/clk-provider.h>
+#include <linux/device.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
@@ -578,3 +579,36 @@ void clk_hw_unregister_divider(struct clk_hw *hw)
kfree(div);
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_divider);
+
+static void devm_clk_hw_release_divider(struct device *dev, void *res)
+{
+ clk_hw_unregister_divider(*(struct clk_hw **)res);
+}
+
+struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
+ struct device_node *np, const char *name,
+ const char *parent_name, const struct clk_hw *parent_hw,
+ const struct clk_parent_data *parent_data, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
+ const struct clk_div_table *table, spinlock_t *lock)
+{
+ struct clk_hw **ptr, *hw;
+
+ ptr = devres_alloc(devm_clk_hw_release_divider, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return ERR_PTR(-ENOMEM);
+
+ hw = __clk_hw_register_divider(dev, np, name, parent_name, parent_hw,
+ parent_data, flags, reg, shift, width,
+ clk_divider_flags, table, lock);
+
+ if (!IS_ERR(hw)) {
+ *ptr = hw;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return hw;
+}
+EXPORT_SYMBOL_GPL(__devm_clk_hw_register_divider);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 33db52ff83a0..5f896df01f83 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -639,6 +639,12 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
const struct clk_parent_data *parent_data, unsigned long flags,
void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
const struct clk_div_table *table, spinlock_t *lock);
+struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
+ struct device_node *np, const char *name,
+ const char *parent_name, const struct clk_hw *parent_hw,
+ const struct clk_parent_data *parent_data, unsigned long flags,
+ void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
+ const struct clk_div_table *table, spinlock_t *lock);
struct clk *clk_register_divider_table(struct device *dev, const char *name,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 shift, u8 width,
@@ -779,6 +785,27 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
(parent_data), (flags), (reg), (shift), \
(width), (clk_divider_flags), (table), \
(lock))
+/**
+ * devm_clk_hw_register_divider_table - register a table based divider clock
+ * with the clock framework (devres variant)
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust divider
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_divider_flags: divider-specific flags for this clock
+ * @table: array of divider/value pairs ending with a div set to 0
+ * @lock: shared register lock for this clock
+ */
+#define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
+ reg, shift, width, \
+ clk_divider_flags, table, lock) \
+ __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
+ NULL, NULL, (flags), (reg), (shift), \
+ (width), (clk_divider_flags), (table), \
+ (lock))
void clk_unregister_divider(struct clk *clk);
void clk_hw_unregister_divider(struct clk_hw *hw);
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 6/9] dt-bindings: clock: document the fsl-flexspi-clk driver
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
` (4 preceding siblings ...)
2020-11-08 18:51 ` [PATCH v3 5/9] clk: divider: add devm_clk_hw_register_divider_table() Michael Walle
@ 2020-11-08 18:51 ` Michael Walle
2020-11-08 18:51 ` [PATCH v3 7/9] clk: fsl-flexspi: new driver Michael Walle
` (2 subsequent siblings)
8 siblings, 0 replies; 21+ messages in thread
From: Michael Walle @ 2020-11-08 18:51 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean,
Michael Walle, Rob Herring
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since v2:
- none
Changes since v1:
- new patch
.../bindings/clock/fsl,flexspi-clock.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml
new file mode 100644
index 000000000000..1fa390ee7b9b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,flexspi-clock.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,flexspi-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale FlexSPI clock driver for Layerscape SoCs
+
+maintainers:
+ - Michael Walle <michael@walle.cc>
+
+description:
+ The Freescale Layerscape SoCs have a special FlexSPI clock which is
+ derived from the platform PLL.
+
+properties:
+ compatible:
+ enum:
+ - fsl,ls1028a-flexspi-clk
+ - fsl,lx2160a-flexspi-clk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ dcfg {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fspi_clk: clock-controller@900 {
+ compatible = "fsl,ls1028a-flexspi-clk";
+ reg = <0x900 0x4>;
+ #clock-cells = <0>;
+ clocks = <&parentclk>;
+ clock-output-names = "fspi_clk";
+ };
+ };
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 7/9] clk: fsl-flexspi: new driver
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
` (5 preceding siblings ...)
2020-11-08 18:51 ` [PATCH v3 6/9] dt-bindings: clock: document the fsl-flexspi-clk driver Michael Walle
@ 2020-11-08 18:51 ` Michael Walle
2020-11-08 18:51 ` [PATCH v3 8/9] arm64: dts: ls1028a: fix FlexSPI clock Michael Walle
2020-11-08 18:51 ` [RFC PATCH v3 9/9] arm64: dts: lx2160a: " Michael Walle
8 siblings, 0 replies; 21+ messages in thread
From: Michael Walle @ 2020-11-08 18:51 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean,
Michael Walle
Add support for the FlexSPI clock on Freescale Layerscape SoCs. The
clock is a simple divider based one and is located inside the device
configuration space (DCFG).
This will allow switching the SCK frequencies for the FlexSPI interface
on the LS1028A and the LX2160A.
Signed-off-by: Michael Walle <michael@walle.cc>
---
Changes since v2:
- none
Changes since v1:
- use devm_clk_hw_register_divider_table() and drop remove()
drivers/clk/Kconfig | 8 +++
drivers/clk/Makefile | 1 +
drivers/clk/clk-fsl-flexspi.c | 106 ++++++++++++++++++++++++++++++++++
3 files changed, 115 insertions(+)
create mode 100644 drivers/clk/clk-fsl-flexspi.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index c715d4681a0b..0066f5af9e77 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -188,6 +188,14 @@ config COMMON_CLK_CS2000_CP
help
If you say yes here you get support for the CS2000 clock multiplier.
+config COMMON_CLK_FSL_FLEXSPI
+ tristate "Clock driver for FlexSPI on Layerscape SoCs"
+ depends on ARCH_LAYERSCAPE || COMPILE_TEST
+ default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI
+ help
+ On Layerscape SoCs there is a special clock for the FlexSPI
+ interface.
+
config COMMON_CLK_FSL_SAI
bool "Clock driver for BCLK of Freescale SAI cores"
depends on ARCH_LAYERSCAPE || COMPILE_TEST
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index da8fcf147eb1..dbdc590e7de3 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
+obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o
obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
diff --git a/drivers/clk/clk-fsl-flexspi.c b/drivers/clk/clk-fsl-flexspi.c
new file mode 100644
index 000000000000..87d5d7b74f29
--- /dev/null
+++ b/drivers/clk/clk-fsl-flexspi.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Layerscape FlexSPI clock driver
+ *
+ * Copyright 2020 Michael Walle <michael@walle.cc>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+static const struct clk_div_table ls1028a_flexspi_divs[] = {
+ { .val = 0, .div = 1, },
+ { .val = 1, .div = 2, },
+ { .val = 2, .div = 3, },
+ { .val = 3, .div = 4, },
+ { .val = 4, .div = 5, },
+ { .val = 5, .div = 6, },
+ { .val = 6, .div = 7, },
+ { .val = 7, .div = 8, },
+ { .val = 11, .div = 12, },
+ { .val = 15, .div = 16, },
+ { .val = 16, .div = 20, },
+ { .val = 17, .div = 24, },
+ { .val = 18, .div = 28, },
+ { .val = 19, .div = 32, },
+ { .val = 20, .div = 80, },
+ {}
+};
+
+static const struct clk_div_table lx2160a_flexspi_divs[] = {
+ { .val = 1, .div = 2, },
+ { .val = 3, .div = 4, },
+ { .val = 5, .div = 6, },
+ { .val = 7, .div = 8, },
+ { .val = 11, .div = 12, },
+ { .val = 15, .div = 16, },
+ { .val = 16, .div = 20, },
+ { .val = 17, .div = 24, },
+ { .val = 18, .div = 28, },
+ { .val = 19, .div = 32, },
+ { .val = 20, .div = 80, },
+ {}
+};
+
+static int fsl_flexspi_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ const char *clk_name = np->name;
+ const char *clk_parent;
+ struct resource *res;
+ void __iomem *reg;
+ struct clk_hw *hw;
+ const struct clk_div_table *divs;
+
+ divs = device_get_match_data(dev);
+ if (!divs)
+ return -ENOENT;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOENT;
+
+ /*
+ * Can't use devm_ioremap_resource() or devm_of_iomap() because the
+ * resource might already be taken by the parent device.
+ */
+ reg = devm_ioremap(dev, res->start, resource_size(res));
+ if (!reg)
+ return -ENOMEM;
+
+ clk_parent = of_clk_get_parent_name(np, 0);
+ if (!clk_parent)
+ return -EINVAL;
+
+ of_property_read_string(np, "clock-output-names", &clk_name);
+
+ hw = devm_clk_hw_register_divider_table(dev, clk_name, clk_parent, 0,
+ reg, 0, 5, 0, divs, NULL);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+}
+
+static const struct of_device_id fsl_flexspi_clk_dt_ids[] = {
+ { .compatible = "fsl,ls1028a-flexspi-clk", .data = &ls1028a_flexspi_divs },
+ { .compatible = "fsl,lx2160a-flexspi-clk", .data = &lx2160a_flexspi_divs },
+ {}
+};
+
+static struct platform_driver fsl_flexspi_clk_driver = {
+ .driver = {
+ .name = "fsl-flexspi-clk",
+ .of_match_table = fsl_flexspi_clk_dt_ids,
+ },
+ .probe = fsl_flexspi_clk_probe,
+};
+module_platform_driver(fsl_flexspi_clk_driver);
+
+MODULE_DESCRIPTION("FlexSPI clock driver for Layerscape SoCs");
+MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:fsl-flexspi-clk");
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 8/9] arm64: dts: ls1028a: fix FlexSPI clock
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
` (6 preceding siblings ...)
2020-11-08 18:51 ` [PATCH v3 7/9] clk: fsl-flexspi: new driver Michael Walle
@ 2020-11-08 18:51 ` Michael Walle
2020-11-08 18:51 ` [RFC PATCH v3 9/9] arm64: dts: lx2160a: " Michael Walle
8 siblings, 0 replies; 21+ messages in thread
From: Michael Walle @ 2020-11-08 18:51 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean,
Michael Walle
Now that we have a proper driver for the FlexSPI interface use it. This
will fix SCK frequency switching on Layerscape SoCs.
This was tested on the Kontron sl28 board.
Signed-off-by: Michael Walle <michael@walle.cc>
---
Changes since v2:
- use device tree constants for clockgen
- also use &fspi_clk for fspi_en clock
Changes since v1:
- none
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 055da2c710c3..8f2f2e2ab87d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -207,9 +207,20 @@
};
dcfg: syscon@1e00000 {
- compatible = "fsl,ls1028a-dcfg", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";
reg = <0x0 0x1e00000 0x0 0x10000>;
+ ranges = <0x0 0x0 0x1e00000 0x10000>;
little-endian;
+
+ fspi_clk: clock-controller@900 {
+ compatible = "fsl,ls1028a-flexspi-clk";
+ reg = <0x900 0x4>;
+ #clock-cells = <0>;
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 0>;
+ clock-output-names = "fspi_clk";
+ };
};
rst: syscon@1e60000 {
@@ -327,8 +338,7 @@
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen QORIQ_CLK_HWACCEL 0>,
- <&clockgen QORIQ_CLK_HWACCEL 0>;
+ clocks = <&fspi_clk>, <&fspi_clk>;
clock-names = "fspi_en", "fspi";
status = "disabled";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC PATCH v3 9/9] arm64: dts: lx2160a: fix FlexSPI clock
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
` (7 preceding siblings ...)
2020-11-08 18:51 ` [PATCH v3 8/9] arm64: dts: ls1028a: fix FlexSPI clock Michael Walle
@ 2020-11-08 18:51 ` Michael Walle
2020-11-08 21:21 ` Vladimir Oltean
8 siblings, 1 reply; 21+ messages in thread
From: Michael Walle @ 2020-11-08 18:51 UTC (permalink / raw)
To: linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean,
Michael Walle
Now that we have a proper driver for the FlexSPI interface use it. This
will fix SCK frequency switching on Layerscape SoCs.
Signed-off-by: Michael Walle <michael@walle.cc>
---
Thanks to Vladimir Oltean, this was partially tested on a LX2160A RDB. But
this patch is marked as RFC nonetheless, because there is too much
difference in the clock tree between LS1028A and LX2160A. It would be nice
if someone could test it and add a Tested-by.
Changes since v2:
- none
Changes since v1:
- none
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 0a54a54ec770..130de5f7ff5e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -661,9 +661,20 @@
};
dcfg: syscon@1e00000 {
- compatible = "fsl,lx2160a-dcfg", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,lx2160a-dcfg", "syscon", "simple-mfd";
reg = <0x0 0x1e00000 0x0 0x10000>;
+ ranges = <0x0 0x0 0x1e00000 0x10000>;
little-endian;
+
+ fspi_clk: clock-controller@900 {
+ compatible = "fsl,lx2160a-flexspi-clk";
+ reg = <0x900 0x4>;
+ #clock-cells = <0>;
+ clocks = <&clockgen 4 0>;
+ clock-output-names = "fspi_clk";
+ };
};
tmu: tmu@1f80000 {
@@ -778,7 +789,7 @@
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 3>, <&fspi_clk>;
clock-names = "fspi_en", "fspi";
status = "disabled";
};
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [RFC PATCH v3 9/9] arm64: dts: lx2160a: fix FlexSPI clock
2020-11-08 18:51 ` [RFC PATCH v3 9/9] arm64: dts: lx2160a: " Michael Walle
@ 2020-11-08 21:21 ` Vladimir Oltean
2020-11-09 9:43 ` Michael Walle
0 siblings, 1 reply; 21+ messages in thread
From: Vladimir Oltean @ 2020-11-08 21:21 UTC (permalink / raw)
To: Michael Walle
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Leo Li,
Y.b. Lu, Xiaowei Bao, Ashish Kumar
On Sun, Nov 08, 2020 at 07:51:13PM +0100, Michael Walle wrote:
> Now that we have a proper driver for the FlexSPI interface use it. This
> will fix SCK frequency switching on Layerscape SoCs.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> Thanks to Vladimir Oltean, this was partially tested on a LX2160A RDB. But
> this patch is marked as RFC nonetheless, because there is too much
> difference in the clock tree between LS1028A and LX2160A. It would be nice
> if someone could test it and add a Tested-by.
You want someone to probe the SCK frequency? I expect that if frequency
switching works on LS1028A, and the lx2160a_flexspi_divs table is
correct (which, based on the documentation for FlexSPICR1[FlexSPI_CLK_DIV],
it is), then it would work on LX2160A too?
Is there a simple test that can be made in order to trivially determine
whether the frequencies are correct?
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [RFC PATCH v3 9/9] arm64: dts: lx2160a: fix FlexSPI clock
2020-11-08 21:21 ` Vladimir Oltean
@ 2020-11-09 9:43 ` Michael Walle
0 siblings, 0 replies; 21+ messages in thread
From: Michael Walle @ 2020-11-09 9:43 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Leo Li,
Y.b. Lu, Xiaowei Bao, Ashish Kumar
Am 2020-11-08 22:21, schrieb Vladimir Oltean:
> On Sun, Nov 08, 2020 at 07:51:13PM +0100, Michael Walle wrote:
>> Now that we have a proper driver for the FlexSPI interface use it.
>> This
>> will fix SCK frequency switching on Layerscape SoCs.
>>
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>> Thanks to Vladimir Oltean, this was partially tested on a LX2160A RDB.
>> But
>> this patch is marked as RFC nonetheless, because there is too much
>> difference in the clock tree between LS1028A and LX2160A. It would be
>> nice
>> if someone could test it and add a Tested-by.
>
> You want someone to probe the SCK frequency?
No not really, just a thorough test.
> I expect that if frequency
> switching works on LS1028A, and the lx2160a_flexspi_divs table is
> correct (which, based on the documentation for
> FlexSPICR1[FlexSPI_CLK_DIV],
> it is), then it would work on LX2160A too?
The switching should work. Finding out wether it is correct can be
checked
by reading the raw register value, i.e. 01E0_0900h. But the parent clock
is
what is bothering me a little. Getting that wrong would lead to a wrong
SCK
output frequency albeit the divider is set to a correct value.
> Is there a simple test that can be made in order to trivially determine
> whether the frequencies are correct?
We already found out that there seems to be kind of a saturation with
higher frequencies, i.e. octal SPI bus is capable of a much higher
throughput but we only achieve 50MB/s. I'd have expected a much higher
datarate (I mean it is advertised as high performance and it uses a 8
bit
wide databus..). But anyway, it might make sense to go the other way,
i.e.
find out the max datathroughput at lower frequencies and look if it
makes
sense. Assuming no DDR, the throughput should be around your frequency.
For
example, having 4 MHz should result in 4MB/s data throughput.
OTOH we already saw that after linux booted - with the current device
tree
which has a setting of 50MHz max SCK frequency - the programmed divider
by
my driver is the same as the former setting (0x13, div-by-32); so this
series
doesn't change the SCK frequency.
-michael
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/9] clk: qoriq: provide constants for the type
2020-11-08 18:51 ` [PATCH v3 3/9] clk: qoriq: provide constants for the type Michael Walle
@ 2020-11-09 22:05 ` Rob Herring
2020-11-09 22:39 ` Michael Walle
0 siblings, 1 reply; 21+ messages in thread
From: Rob Herring @ 2020-11-09 22:05 UTC (permalink / raw)
To: Michael Walle
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Michael Turquette, Stephen Boyd, Shawn Guo, Li Yang, Y . b . Lu,
Xiaowei Bao, Ashish Kumar, Vladimir Oltean
On Sun, Nov 08, 2020 at 07:51:07PM +0100, Michael Walle wrote:
> To avoid future mistakes in the device tree for the clockgen module, add
> constants for the clockgen subtype as well as a macro for the PLL
> divider.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> Changes since v2:
> - new patch
>
> drivers/clk/clk-qoriq.c | 13 +++++++------
> include/dt-bindings/clock/fsl,qoriq-clockgen.h | 15 +++++++++++++++
> 2 files changed, 22 insertions(+), 6 deletions(-)
> create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h
>
> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> index 46101c6a20f2..70aa521e7e7f 100644
> --- a/drivers/clk/clk-qoriq.c
> +++ b/drivers/clk/clk-qoriq.c
> @@ -7,6 +7,7 @@
>
> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>
> +#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
> #include <linux/clk.h>
> #include <linux/clk-provider.h>
> #include <linux/clkdev.h>
> @@ -1368,33 +1369,33 @@ static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
> idx = clkspec->args[1];
>
> switch (type) {
> - case 0:
> + case QORIQ_CLK_SYSCLK:
> if (idx != 0)
> goto bad_args;
> clk = cg->sysclk;
> break;
> - case 1:
> + case QORIQ_CLK_CMUX:
> if (idx >= ARRAY_SIZE(cg->cmux))
> goto bad_args;
> clk = cg->cmux[idx];
> break;
> - case 2:
> + case QORIQ_CLK_HWACCEL:
> if (idx >= ARRAY_SIZE(cg->hwaccel))
> goto bad_args;
> clk = cg->hwaccel[idx];
> break;
> - case 3:
> + case QORIQ_CLK_FMAN:
> if (idx >= ARRAY_SIZE(cg->fman))
> goto bad_args;
> clk = cg->fman[idx];
> break;
> - case 4:
> + case QORIQ_CLK_PLATFORM_PLL:
> pll = &cg->pll[PLATFORM_PLL];
> if (idx >= ARRAY_SIZE(pll->div))
> goto bad_args;
> clk = pll->div[idx].clk;
> break;
> - case 5:
> + case QORIQ_CLK_CORECLK:
> if (idx != 0)
> goto bad_args;
> clk = cg->coreclk;
> diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
> new file mode 100644
> index 000000000000..ddec7d0bdc7f
> --- /dev/null
> +++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
> +#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
> +
> +#define QORIQ_CLK_SYSCLK 0
> +#define QORIQ_CLK_CMUX 1
> +#define QORIQ_CLK_HWACCEL 2
> +#define QORIQ_CLK_FMAN 3
> +#define QORIQ_CLK_PLATFORM_PLL 4
> +#define QORIQ_CLK_CORECLK 5
> +
> +#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
This is not used and doesn't seem like part of the ABI (shared with dts
files).
> +
> +#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/9] clk: qoriq: provide constants for the type
2020-11-09 22:05 ` Rob Herring
@ 2020-11-09 22:39 ` Michael Walle
2020-11-09 22:55 ` Rob Herring
0 siblings, 1 reply; 21+ messages in thread
From: Michael Walle @ 2020-11-09 22:39 UTC (permalink / raw)
To: Rob Herring
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Michael Turquette, Stephen Boyd, Shawn Guo, Li Yang, Y . b . Lu,
Xiaowei Bao, Ashish Kumar, Vladimir Oltean
Am 2020-11-09 23:05, schrieb Rob Herring:
> On Sun, Nov 08, 2020 at 07:51:07PM +0100, Michael Walle wrote:
>> To avoid future mistakes in the device tree for the clockgen module,
>> add
>> constants for the clockgen subtype as well as a macro for the PLL
>> divider.
>>
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>> Changes since v2:
>> - new patch
>>
>> drivers/clk/clk-qoriq.c | 13 +++++++------
>> include/dt-bindings/clock/fsl,qoriq-clockgen.h | 15 +++++++++++++++
>> 2 files changed, 22 insertions(+), 6 deletions(-)
>> create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h
>>
>> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
>> index 46101c6a20f2..70aa521e7e7f 100644
>> --- a/drivers/clk/clk-qoriq.c
>> +++ b/drivers/clk/clk-qoriq.c
>> @@ -7,6 +7,7 @@
>>
>> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>>
>> +#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
>> #include <linux/clk.h>
>> #include <linux/clk-provider.h>
>> #include <linux/clkdev.h>
>> @@ -1368,33 +1369,33 @@ static struct clk *clockgen_clk_get(struct
>> of_phandle_args *clkspec, void *data)
>> idx = clkspec->args[1];
>>
>> switch (type) {
>> - case 0:
>> + case QORIQ_CLK_SYSCLK:
>> if (idx != 0)
>> goto bad_args;
>> clk = cg->sysclk;
>> break;
>> - case 1:
>> + case QORIQ_CLK_CMUX:
>> if (idx >= ARRAY_SIZE(cg->cmux))
>> goto bad_args;
>> clk = cg->cmux[idx];
>> break;
>> - case 2:
>> + case QORIQ_CLK_HWACCEL:
>> if (idx >= ARRAY_SIZE(cg->hwaccel))
>> goto bad_args;
>> clk = cg->hwaccel[idx];
>> break;
>> - case 3:
>> + case QORIQ_CLK_FMAN:
>> if (idx >= ARRAY_SIZE(cg->fman))
>> goto bad_args;
>> clk = cg->fman[idx];
>> break;
>> - case 4:
>> + case QORIQ_CLK_PLATFORM_PLL:
>> pll = &cg->pll[PLATFORM_PLL];
>> if (idx >= ARRAY_SIZE(pll->div))
>> goto bad_args;
>> clk = pll->div[idx].clk;
>> break;
>> - case 5:
>> + case QORIQ_CLK_CORECLK:
>> if (idx != 0)
>> goto bad_args;
>> clk = cg->coreclk;
>> diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h
>> b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
>> new file mode 100644
>> index 000000000000..ddec7d0bdc7f
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
>> @@ -0,0 +1,15 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +
>> +#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
>> +#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
>> +
>> +#define QORIQ_CLK_SYSCLK 0
>> +#define QORIQ_CLK_CMUX 1
>> +#define QORIQ_CLK_HWACCEL 2
>> +#define QORIQ_CLK_FMAN 3
>> +#define QORIQ_CLK_PLATFORM_PLL 4
>> +#define QORIQ_CLK_CORECLK 5
>> +
>> +#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
>
> This is not used and doesn't seem like part of the ABI (shared with dts
> files).
TBH I haven't found a nice way to integrate this macro into the clock
driver. It is used in the device tree for the type PLATFORM_PLL.
Previously, you had "<&clockgen 4 1>", where 4 is the PLATFORM_PLL and 1
is actually "div-by-2". Thus I replaced it by <&clockgen
QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>. (I just realized that
QORIQ_CLK_PLL_DIV_BY(2) might be a better name.)
I already figured, that this might be a problem, if that macro isn't
used in the driver.
-michael
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/9] clk: qoriq: provide constants for the type
2020-11-09 22:39 ` Michael Walle
@ 2020-11-09 22:55 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2020-11-09 22:55 UTC (permalink / raw)
To: Michael Walle
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Michael Turquette, Stephen Boyd, Shawn Guo, Li Yang, Y . b . Lu,
Xiaowei Bao, Ashish Kumar, Vladimir Oltean
On Mon, Nov 9, 2020 at 4:39 PM Michael Walle <michael@walle.cc> wrote:
>
> Am 2020-11-09 23:05, schrieb Rob Herring:
> > On Sun, Nov 08, 2020 at 07:51:07PM +0100, Michael Walle wrote:
> >> To avoid future mistakes in the device tree for the clockgen module,
> >> add
> >> constants for the clockgen subtype as well as a macro for the PLL
> >> divider.
> >>
> >> Signed-off-by: Michael Walle <michael@walle.cc>
> >> ---
> >> Changes since v2:
> >> - new patch
> >>
> >> drivers/clk/clk-qoriq.c | 13 +++++++------
> >> include/dt-bindings/clock/fsl,qoriq-clockgen.h | 15 +++++++++++++++
> >> 2 files changed, 22 insertions(+), 6 deletions(-)
> >> create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h
> >>
> >> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> >> index 46101c6a20f2..70aa521e7e7f 100644
> >> --- a/drivers/clk/clk-qoriq.c
> >> +++ b/drivers/clk/clk-qoriq.c
> >> @@ -7,6 +7,7 @@
> >>
> >> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> >>
> >> +#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
> >> #include <linux/clk.h>
> >> #include <linux/clk-provider.h>
> >> #include <linux/clkdev.h>
> >> @@ -1368,33 +1369,33 @@ static struct clk *clockgen_clk_get(struct
> >> of_phandle_args *clkspec, void *data)
> >> idx = clkspec->args[1];
> >>
> >> switch (type) {
> >> - case 0:
> >> + case QORIQ_CLK_SYSCLK:
> >> if (idx != 0)
> >> goto bad_args;
> >> clk = cg->sysclk;
> >> break;
> >> - case 1:
> >> + case QORIQ_CLK_CMUX:
> >> if (idx >= ARRAY_SIZE(cg->cmux))
> >> goto bad_args;
> >> clk = cg->cmux[idx];
> >> break;
> >> - case 2:
> >> + case QORIQ_CLK_HWACCEL:
> >> if (idx >= ARRAY_SIZE(cg->hwaccel))
> >> goto bad_args;
> >> clk = cg->hwaccel[idx];
> >> break;
> >> - case 3:
> >> + case QORIQ_CLK_FMAN:
> >> if (idx >= ARRAY_SIZE(cg->fman))
> >> goto bad_args;
> >> clk = cg->fman[idx];
> >> break;
> >> - case 4:
> >> + case QORIQ_CLK_PLATFORM_PLL:
> >> pll = &cg->pll[PLATFORM_PLL];
> >> if (idx >= ARRAY_SIZE(pll->div))
> >> goto bad_args;
> >> clk = pll->div[idx].clk;
> >> break;
> >> - case 5:
> >> + case QORIQ_CLK_CORECLK:
> >> if (idx != 0)
> >> goto bad_args;
> >> clk = cg->coreclk;
> >> diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h
> >> b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
> >> new file mode 100644
> >> index 000000000000..ddec7d0bdc7f
> >> --- /dev/null
> >> +++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
> >> @@ -0,0 +1,15 @@
> >> +/* SPDX-License-Identifier: GPL-2.0-only */
> >> +
> >> +#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
> >> +#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
> >> +
> >> +#define QORIQ_CLK_SYSCLK 0
> >> +#define QORIQ_CLK_CMUX 1
> >> +#define QORIQ_CLK_HWACCEL 2
> >> +#define QORIQ_CLK_FMAN 3
> >> +#define QORIQ_CLK_PLATFORM_PLL 4
> >> +#define QORIQ_CLK_CORECLK 5
> >> +
> >> +#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
> >
> > This is not used and doesn't seem like part of the ABI (shared with dts
> > files).
>
> TBH I haven't found a nice way to integrate this macro into the clock
> driver. It is used in the device tree for the type PLATFORM_PLL.
> Previously, you had "<&clockgen 4 1>", where 4 is the PLATFORM_PLL and 1
> is actually "div-by-2". Thus I replaced it by <&clockgen
> QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>. (I just realized that
> QORIQ_CLK_PLL_DIV_BY(2) might be a better name.)
Ah okay. I guess this is fine.
Acked-by: Rob Herring <robh@kernel.org>
Rob
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [EXT] [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen phandle
2020-11-08 18:51 ` [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen phandle Michael Walle
@ 2020-11-20 9:25 ` Ashish Kumar
2020-11-20 9:38 ` Michael Walle
0 siblings, 1 reply; 21+ messages in thread
From: Ashish Kumar @ 2020-11-20 9:25 UTC (permalink / raw)
To: Michael Walle, linux-clk, devicetree, linux-kernel, linux-arm-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Leo Li,
Y.b. Lu, Xiaowei Bao, Vladimir Oltean
HI Michael,
> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: Monday, November 9, 2020 12:21 AM
> To: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Cc: Michael Turquette <mturquette@baylibre.com>; Stephen Boyd
> <sboyd@kernel.org>; Rob Herring <robh+dt@kernel.org>; Shawn Guo
> <shawnguo@kernel.org>; Leo Li <leoyang.li@nxp.com>; Y.b. Lu
> <yangbo.lu@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>; Ashish Kumar
> <ashish.kumar@nxp.com>; Vladimir Oltean <vladimir.oltean@nxp.com>;
> Michael Walle <michael@walle.cc>
> Subject: [EXT] [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen
> phandle
>
> Caution: EXT Email
>
> Now that we have constants, use them. This is just a mechanical change.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> Changes since v2:
> - new patch
I am not able to apply this patch cleanly, does it have any dependency patch that I have missed?
My assumption is that this patch series is superset of
Series 1: [1/4] dt-bindings: clock: document the fsl-flexspi-clk driver
And
Series 2: [v2,1/5] clk: divider: add devm_clk_hw_register_divider_table()
Regards
Ashish
>
> .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 162 +++++++++++++-----
> 1 file changed, 116 insertions(+), 46 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 2f60a6ba7e14..055da2c710c3 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -8,6 +8,7 @@
> *
> */
>
> +#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/thermal/thermal.h>
>
> @@ -32,7 +33,7 @@
> compatible = "arm,cortex-a72";
> reg = <0x0>;
> enable-method = "psci";
> - clocks = <&clockgen 1 0>;
> + clocks = <&clockgen QORIQ_CLK_CMUX 0>;
> next-level-cache = <&l2>;
> cpu-idle-states = <&CPU_PW20>;
> #cooling-cells = <2>; @@ -43,7 +44,7 @@
> compatible = "arm,cortex-a72";
> reg = <0x1>;
> enable-method = "psci";
> - clocks = <&clockgen 1 0>;
> + clocks = <&clockgen QORIQ_CLK_CMUX 0>;
> next-level-cache = <&l2>;
> cpu-idle-states = <&CPU_PW20>;
> #cooling-cells = <2>; @@ -236,7 +237,8 @@
> #size-cells = <0>;
> reg = <0x0 0x2000000 0x0 0x10000>;
> interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(4)>;
> status = "disabled";
> };
>
> @@ -246,7 +248,8 @@
> #size-cells = <0>;
> reg = <0x0 0x2010000 0x0 0x10000>;
> interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(4)>;
> status = "disabled";
> };
>
> @@ -256,7 +259,8 @@
> #size-cells = <0>;
> reg = <0x0 0x2020000 0x0 0x10000>;
> interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(4)>;
> status = "disabled";
> };
>
> @@ -266,7 +270,8 @@
> #size-cells = <0>;
> reg = <0x0 0x2030000 0x0 0x10000>;
> interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(4)>;
> status = "disabled";
> };
>
> @@ -276,7 +281,8 @@
> #size-cells = <0>;
> reg = <0x0 0x2040000 0x0 0x10000>;
> interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(4)>;
> status = "disabled";
> };
>
> @@ -286,7 +292,8 @@
> #size-cells = <0>;
> reg = <0x0 0x2050000 0x0 0x10000>;
> interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(4)>;
> status = "disabled";
> };
>
> @@ -296,7 +303,8 @@
> #size-cells = <0>;
> reg = <0x0 0x2060000 0x0 0x10000>;
> interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(4)>;
> status = "disabled";
> };
>
> @@ -306,7 +314,8 @@
> #size-cells = <0>;
> reg = <0x0 0x2070000 0x0 0x10000>;
> interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 3>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(4)>;
> status = "disabled";
> };
>
> @@ -318,7 +327,8 @@
> <0x0 0x20000000 0x0 0x10000000>;
> reg-names = "fspi_base", "fspi_mmap";
> interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 2 0>, <&clockgen 2 0>;
> + clocks = <&clockgen QORIQ_CLK_HWACCEL 0>,
> + <&clockgen QORIQ_CLK_HWACCEL 0>;
> clock-names = "fspi_en", "fspi";
> status = "disabled";
> };
> @@ -330,7 +340,8 @@
> reg = <0x0 0x2100000 0x0 0x10000>;
> interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> clock-names = "dspi";
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> dmas = <&edma0 0 62>, <&edma0 0 60>;
> dma-names = "tx", "rx";
> spi-num-chipselects = <4>; @@ -345,7 +356,8 @@
> reg = <0x0 0x2110000 0x0 0x10000>;
> interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> clock-names = "dspi";
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> dmas = <&edma0 0 58>, <&edma0 0 56>;
> dma-names = "tx", "rx";
> spi-num-chipselects = <4>; @@ -360,7 +372,8 @@
> reg = <0x0 0x2120000 0x0 0x10000>;
> interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> clock-names = "dspi";
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> dmas = <&edma0 0 54>, <&edma0 0 2>;
> dma-names = "tx", "rx";
> spi-num-chipselects = <3>; @@ -373,7 +386,7 @@
> reg = <0x0 0x2140000 0x0 0x10000>;
> interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> clock-frequency = <0>; /* fixed up by bootloader */
> - clocks = <&clockgen 2 1>;
> + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
> voltage-ranges = <1800 1800 3300 3300>;
> sdhci,auto-cmd12;
> little-endian;
> @@ -386,7 +399,7 @@
> reg = <0x0 0x2150000 0x0 0x10000>;
> interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> clock-frequency = <0>; /* fixed up by bootloader */
> - clocks = <&clockgen 2 1>;
> + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
> voltage-ranges = <1800 1800 3300 3300>;
> sdhci,auto-cmd12;
> broken-cd;
> @@ -399,7 +412,8 @@
> compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan";
> reg = <0x0 0x2180000 0x0 0x10000>;
> interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&sysclk>, <&clockgen 4 1>;
> + clocks = <&sysclk>, <&clockgen QORIQ_CLK_PLATFORM_PLL
> +
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "ipg", "per";
> status = "disabled";
> };
> @@ -408,7 +422,8 @@
> compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan";
> reg = <0x0 0x2190000 0x0 0x10000>;
> interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&sysclk>, <&clockgen 4 1>;
> + clocks = <&sysclk>, <&clockgen QORIQ_CLK_PLATFORM_PLL
> +
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "ipg", "per";
> status = "disabled";
> };
> @@ -417,7 +432,8 @@
> compatible = "fsl,ns16550", "ns16550a";
> reg = <0x00 0x21c0500 0x0 0x100>;
> interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> status = "disabled";
> };
>
> @@ -425,7 +441,8 @@
> compatible = "fsl,ns16550", "ns16550a";
> reg = <0x00 0x21c0600 0x0 0x100>;
> interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> status = "disabled";
> };
>
> @@ -434,7 +451,8 @@
> compatible = "fsl,ls1028a-lpuart";
> reg = <0x0 0x2260000 0x0 0x1000>;
> interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "ipg";
> dma-names = "rx","tx";
> dmas = <&edma0 1 32>, @@ -446,7 +464,8 @@
> compatible = "fsl,ls1028a-lpuart";
> reg = <0x0 0x2270000 0x0 0x1000>;
> interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "ipg";
> dma-names = "rx","tx";
> dmas = <&edma0 1 30>, @@ -458,7 +477,8 @@
> compatible = "fsl,ls1028a-lpuart";
> reg = <0x0 0x2280000 0x0 0x1000>;
> interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "ipg";
> dma-names = "rx","tx";
> dmas = <&edma0 1 28>, @@ -470,7 +490,8 @@
> compatible = "fsl,ls1028a-lpuart";
> reg = <0x0 0x2290000 0x0 0x1000>;
> interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "ipg";
> dma-names = "rx","tx";
> dmas = <&edma0 1 26>, @@ -482,7 +503,8 @@
> compatible = "fsl,ls1028a-lpuart";
> reg = <0x0 0x22a0000 0x0 0x1000>;
> interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "ipg";
> dma-names = "rx","tx";
> dmas = <&edma0 1 24>, @@ -494,7 +516,8 @@
> compatible = "fsl,ls1028a-lpuart";
> reg = <0x0 0x22b0000 0x0 0x1000>;
> interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "ipg";
> dma-names = "rx","tx";
> dmas = <&edma0 1 22>, @@ -513,8 +536,10 @@
> interrupt-names = "edma-tx", "edma-err";
> dma-channels = <32>;
> clock-names = "dmamux0", "dmamux1";
> - clocks = <&clockgen 4 1>,
> - <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> };
>
> gpio1: gpio@2300000 {
> @@ -576,7 +601,8 @@
> <0x7 0x100520 0x0 0x4>;
> reg-names = "ahci", "sata-ecc";
> interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> status = "disabled";
> };
>
> @@ -748,14 +774,20 @@
> cluster1_core0_watchdog: watchdog@c000000 {
> compatible = "arm,sp805", "arm,primecell";
> reg = <0x0 0xc000000 0x0 0x1000>;
> - clocks = <&clockgen 4 15>, <&clockgen 4 15>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(16)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(16)>;
> clock-names = "wdog_clk", "apb_pclk";
> };
>
> cluster1_core1_watchdog: watchdog@c010000 {
> compatible = "arm,sp805", "arm,primecell";
> reg = <0x0 0xc010000 0x0 0x1000>;
> - clocks = <&clockgen 4 15>, <&clockgen 4 15>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(16)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(16)>;
> clock-names = "wdog_clk", "apb_pclk";
> };
>
> @@ -764,8 +796,14 @@
> compatible = "fsl,vf610-sai";
> reg = <0x0 0xf100000 0x0 0x10000>;
> interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> - <&clockgen 4 1>, <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "bus", "mclk1", "mclk2", "mclk3";
> dma-names = "tx", "rx";
> dmas = <&edma0 1 4>, @@ -779,8 +817,14 @@
> compatible = "fsl,vf610-sai";
> reg = <0x0 0xf110000 0x0 0x10000>;
> interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> - <&clockgen 4 1>, <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "bus", "mclk1", "mclk2", "mclk3";
> dma-names = "tx", "rx";
> dmas = <&edma0 1 6>, @@ -794,8 +838,14 @@
> compatible = "fsl,vf610-sai";
> reg = <0x0 0xf120000 0x0 0x10000>;
> interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> - <&clockgen 4 1>, <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "bus", "mclk1", "mclk2", "mclk3";
> dma-names = "tx", "rx";
> dmas = <&edma0 1 8>, @@ -809,8 +859,14 @@
> compatible = "fsl,vf610-sai";
> reg = <0x0 0xf130000 0x0 0x10000>;
> interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> - <&clockgen 4 1>, <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "bus", "mclk1", "mclk2", "mclk3";
> dma-names = "tx", "rx";
> dmas = <&edma0 1 10>, @@ -824,8 +880,14 @@
> compatible = "fsl,vf610-sai";
> reg = <0x0 0xf140000 0x0 0x10000>;
> interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> - <&clockgen 4 1>, <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "bus", "mclk1", "mclk2", "mclk3";
> dma-names = "tx", "rx";
> dmas = <&edma0 1 12>, @@ -839,8 +901,14 @@
> compatible = "fsl,vf610-sai";
> reg = <0x0 0xf150000 0x0 0x10000>;
> interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&clockgen 4 1>, <&clockgen 4 1>,
> - <&clockgen 4 1>, <&clockgen 4 1>;
> + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>,
> + <&clockgen QORIQ_CLK_PLATFORM_PLL
> + QORIQ_CLK_PLL_DIV(2)>;
> clock-names = "bus", "mclk1", "mclk2", "mclk3";
> dma-names = "tx", "rx";
> dmas = <&edma0 1 14>, @@ -961,7 +1029,7 @@
> ethernet@0,4 {
> compatible = "fsl,enetc-ptp";
> reg = <0x000400 0 0 0 0>;
> - clocks = <&clockgen 2 3>;
> + clocks = <&clockgen QORIQ_CLK_HWACCEL
> + 3>;
> little-endian;
> fsl,extts-fifo;
> };
> @@ -1056,8 +1124,10 @@
> interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
> <0 223 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "DE", "SE";
> - clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
> - <&clockgen 2 2>;
> + clocks = <&dpclk>,
> + <&clockgen QORIQ_CLK_HWACCEL 2>,
> + <&clockgen QORIQ_CLK_HWACCEL 2>,
> + <&clockgen QORIQ_CLK_HWACCEL 2>;
> clock-names = "pxlclk", "mclk", "aclk", "pclk";
> arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
> arm,malidp-arqos-value = <0xd000d000>;
> --
> 2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen phandle
2020-11-20 9:25 ` [EXT] " Ashish Kumar
@ 2020-11-20 9:38 ` Michael Walle
2020-11-20 9:51 ` [EXT] " Ashish Kumar
0 siblings, 1 reply; 21+ messages in thread
From: Michael Walle @ 2020-11-20 9:38 UTC (permalink / raw)
To: Ashish Kumar
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Leo Li,
Y.b. Lu, Xiaowei Bao, Vladimir Oltean
Hi Ashish,
Am 2020-11-20 10:25, schrieb Ashish Kumar:
> I am not able to apply this patch cleanly, does it have any dependency
> patch that I have missed?
What is your base? I've just tried to apply this series (stand-alone)
onto
linux-next and it applied cleanly.
> My assumption is that this patch series is superset of
> Series 1: [1/4] dt-bindings: clock: document the fsl-flexspi-clk
> driver
> And
> Series 2: [v2,1/5] clk: divider: add
> devm_clk_hw_register_divider_table()
That is correct.
-michael
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [EXT] Re: [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen phandle
2020-11-20 9:38 ` Michael Walle
@ 2020-11-20 9:51 ` Ashish Kumar
2020-11-20 10:05 ` Michael Walle
0 siblings, 1 reply; 21+ messages in thread
From: Ashish Kumar @ 2020-11-20 9:51 UTC (permalink / raw)
To: Michael Walle
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Leo Li,
Y.b. Lu, Xiaowei Bao, Vladimir Oltean
Hi Michelle,
> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: Friday, November 20, 2020 3:09 PM
> To: Ashish Kumar <ashish.kumar@nxp.com>
> Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Michael
> Turquette <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>;
> Rob Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Leo
> Li <leoyang.li@nxp.com>; Y.b. Lu <yangbo.lu@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>; Vladimir Oltean <vladimir.oltean@nxp.com>
> Subject: [EXT] Re: [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the
> clockgen phandle
>
> Caution: EXT Email
>
> Hi Ashish,
>
> Am 2020-11-20 10:25, schrieb Ashish Kumar:
> > I am not able to apply this patch cleanly, does it have any dependency
> > patch that I have missed?
>
> What is your base? I've just tried to apply this series (stand-alone) onto linux-
> next and it applied cleanly.
I used https://github.com/torvalds/linux.git should I try this git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git ?
Regards
Ashish
>
> > My assumption is that this patch series is superset of Series 1: [1/4]
> > dt-bindings: clock: document the fsl-flexspi-clk driver And Series 2:
> > [v2,1/5] clk: divider: add
> > devm_clk_hw_register_divider_table()
>
> That is correct.
>
> -michael
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen phandle
2020-11-20 9:51 ` [EXT] " Ashish Kumar
@ 2020-11-20 10:05 ` Michael Walle
0 siblings, 0 replies; 21+ messages in thread
From: Michael Walle @ 2020-11-20 10:05 UTC (permalink / raw)
To: Ashish Kumar
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Michael Turquette, Stephen Boyd, Rob Herring, Shawn Guo, Leo Li,
Y.b. Lu, Xiaowei Bao, Vladimir Oltean
Hi Ashish,
Am 2020-11-20 10:51, schrieb Ashish Kumar:
>> -----Original Message-----
>> From: Michael Walle <michael@walle.cc>
>> Sent: Friday, November 20, 2020 3:09 PM
>> To: Ashish Kumar <ashish.kumar@nxp.com>
>> Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
>> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Michael
>> Turquette <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>;
>> Rob Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Leo
>> Li <leoyang.li@nxp.com>; Y.b. Lu <yangbo.lu@nxp.com>; Xiaowei Bao
>> <xiaowei.bao@nxp.com>; Vladimir Oltean <vladimir.oltean@nxp.com>
>> Subject: [EXT] Re: [PATCH v3 4/9] arm64: dts: ls1028a: use constants
>> in the
>> clockgen phandle
>>
>> Caution: EXT Email
>>
>> Hi Ashish,
>>
>> Am 2020-11-20 10:25, schrieb Ashish Kumar:
>> > I am not able to apply this patch cleanly, does it have any dependency
>> > patch that I have missed?
>>
>> What is your base? I've just tried to apply this series (stand-alone)
>> onto linux-
>> next and it applied cleanly.
> I used https://github.com/torvalds/linux.git should I try this
> git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git ?
Mh, I just tried clk-next. clk-next is missing some device tree changes.
So,
parts of this series should go through the soc tree (shawnguo) and some
through
clk-next (or acked by Stephen Boyd).
If you want to apply it, use the for-next branch of the soc tree:
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
-michael
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 1/9] arm64: dts: ls1028a: fix ENETC PTP clock input
2020-11-08 18:51 ` [PATCH v3 1/9] arm64: dts: ls1028a: fix ENETC PTP clock input Michael Walle
@ 2020-11-30 9:20 ` Shawn Guo
0 siblings, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2020-11-30 9:20 UTC (permalink / raw)
To: Michael Walle
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Michael Turquette, Stephen Boyd, Rob Herring, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean
On Sun, Nov 08, 2020 at 07:51:05PM +0100, Michael Walle wrote:
> On the LS1028A the ENETC reference clock is connected to 4th HWA output,
> see Figure 7 "Clock subsystem block diagram".
>
> The PHC may run with a wrong frequency. ptp_qoriq_auto_config() will read
> the clock speed of the clock given in the device tree. It is likely that,
> on the reference board this wasn't noticed because both clocks have the
> same frequency. But this must not be always the case. Fix it.
>
> Fixes: 49401003e260 ("arm64: dts: fsl: ls1028a: add ENETC 1588 timer node")
> Signed-off-by: Michael Walle <michael@walle.cc>
Applied, thanks.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/9] arm64: dts: ls1028a: fix FlexSPI clock input
2020-11-08 18:51 ` [PATCH v3 2/9] arm64: dts: ls1028a: fix FlexSPI " Michael Walle
@ 2020-11-30 9:21 ` Shawn Guo
0 siblings, 0 replies; 21+ messages in thread
From: Shawn Guo @ 2020-11-30 9:21 UTC (permalink / raw)
To: Michael Walle
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Michael Turquette, Stephen Boyd, Rob Herring, Li Yang,
Y . b . Lu, Xiaowei Bao, Ashish Kumar, Vladimir Oltean
On Sun, Nov 08, 2020 at 07:51:06PM +0100, Michael Walle wrote:
> On the LS1028A the FlexSPI clock is connected to the first HWA output,
> see Figure 7 "Clock subsystem block diagram".
>
> Fixes: c77fae5ba09a ("arm64: dts: ls1028a: Add FlexSPI support")
> Signed-off-by: Michael Walle <michael@walle.cc>
Applied, thanks.
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2020-11-30 9:22 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
2020-11-08 18:51 ` [PATCH v3 1/9] arm64: dts: ls1028a: fix ENETC PTP clock input Michael Walle
2020-11-30 9:20 ` Shawn Guo
2020-11-08 18:51 ` [PATCH v3 2/9] arm64: dts: ls1028a: fix FlexSPI " Michael Walle
2020-11-30 9:21 ` Shawn Guo
2020-11-08 18:51 ` [PATCH v3 3/9] clk: qoriq: provide constants for the type Michael Walle
2020-11-09 22:05 ` Rob Herring
2020-11-09 22:39 ` Michael Walle
2020-11-09 22:55 ` Rob Herring
2020-11-08 18:51 ` [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen phandle Michael Walle
2020-11-20 9:25 ` [EXT] " Ashish Kumar
2020-11-20 9:38 ` Michael Walle
2020-11-20 9:51 ` [EXT] " Ashish Kumar
2020-11-20 10:05 ` Michael Walle
2020-11-08 18:51 ` [PATCH v3 5/9] clk: divider: add devm_clk_hw_register_divider_table() Michael Walle
2020-11-08 18:51 ` [PATCH v3 6/9] dt-bindings: clock: document the fsl-flexspi-clk driver Michael Walle
2020-11-08 18:51 ` [PATCH v3 7/9] clk: fsl-flexspi: new driver Michael Walle
2020-11-08 18:51 ` [PATCH v3 8/9] arm64: dts: ls1028a: fix FlexSPI clock Michael Walle
2020-11-08 18:51 ` [RFC PATCH v3 9/9] arm64: dts: lx2160a: " Michael Walle
2020-11-08 21:21 ` Vladimir Oltean
2020-11-09 9:43 ` Michael Walle
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